JP2602785Y2 - Address decoder / encoder circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address decoder / encoder circuit for decoding and encoding addresses in a plurality of modes.

[0002]

2. Description of the Related Art FIG. 3 shows an example of the configuration of a conventional address decoder / encoder circuit of this type. In the figure, 1 is a control circuit, 2 is an address counter circuit, 3 is an address decoder circuit, 4 is a plurality of mode 1, mode 2,
.. A mode selector circuit for inputting the mode N , 51,
.., 5n are encoder circuits. The same number of encoder circuits 51, 52,... As the plurality of modes are provided to the address decoder circuit via the mode selector circuit 4.
..5n is connected.

The address of the address counter circuit 2 counts up / down in response to an up / down signal from the control circuit 1. The output of the address counter circuit 2 becomes the input of the address decoder circuit 3, and the address of the address decoder circuit 3 is selected. The selected address is input to the encoder circuit of the mode by the mode selector circuit 4 and encoded.

[0004]

As described above, this type of conventional address decoder / encoder circuit is provided with an individual encoder circuit for each mode, so that the chip area increases and the chip cost increases. I was The present invention has been made to solve the above-described problem, and has as its object to obtain a circuit that can handle a plurality of mode addresses with one encoder circuit.

[0005]

Address decoder encoder circuit of the present invention Means for Solving the Problems] In order to achieve the above object, A
A control circuit to which a pull-down signal is input;
Up / down signal from control circuit is input
An address counter circuit, and
Address decoder to which the output address signal is input
Circuit and unique address decoder circuit, and said address
Encoder circuit to which the output signal of the decoder circuit is input
And a mode selector circuit to which a plurality of modes are input,
The output signal of the mode selector circuit is
Address decoder / encoder input to the coder circuit
A circuit, wherein the address of the address counter circuit is
Signal of the specified mode among the above-mentioned modes.
When the address is different from the address,
Sends a skip signal to the control circuit,
The troll circuit is output from the address counter circuit.
Skip the above address signal (count up /
) .

[0006]

FIG. 1 shows the configuration of an embodiment of the present invention. 1, 2, 3, 4 shows the one that the same or corresponding the same reference numerals of FIG. 3 in FIG. Up / down from control circuit 1
The address of the address counter circuit 2 is
Address count up / down, this address counter
The output of the circuit 2 becomes the input of the address decoder circuit 3,
The address of the address decoder circuit 3 is selected. 4 is
A plurality of mode 1, mode 2, ... mode N are input
FIG. 5 is an encoder circuit for encoding the output of the address decoder circuit 3, 6 is set to a mode designated by the mode selector circuit 4, decodes the output of the address counter circuit 2, and the decoded address is the address of the designated mode. If not, the address skip signal is sent to the control circuit 1 to skip the address signal.

FIG. 2 is a timing chart showing an example of the operation of the circuit of FIG. The mode selector circuit 4 includes:
It is assumed that mode 1 is input as the designated mode.
As an UP / DOWN signal of the control circuit 1 , FIG.
To input a signal of the A. If the UP / DOWN signal is at an intermediate level, the address is kept held. Next, UPX or UP / DOWN signal is one of an output of the control circuit 1 as shown in B of FIG. 2 becomes H level
From the address counter circuit 2
In the address is counted up, an address 001 (mode 1) to the address 010 (mode 1). Further , when an H level is input as the UP / DOWN signal , the address counter circuit 2 counts up and becomes the address 011. The address 011 is a fictitious address in mode 1 (for use in mode 2). At this time, an address skip signal shown in FIG. 2D is output from the unique address circuit 6 and sent to the control circuit 1.
Further, a signal for counting up by the address counter circuit 2 is input to the address counter circuit 2 so that the address 1
00 (mode 1).

[0008] Similarly Zhou of the address 100 (mode 1)
From state, as shown in A of FIG. 2, when the L level signal as the UP / DOWN signal is inputted, in C of FIG. 2 shows
As to a one output of the control circuit 1 DO
An L-level signal from WN enters the address counter circuit 2.
As a result, the address becomes 011 (mode 2), and the address as shown in FIG.
By skipping signal, the address is skipped (counted down), the address 010 (mode 1). Further, when an L-level signal is input as the UP / DOWN signal, the address becomes 001 (mode 1). As described above, not using any in the specified mode (mode 1), when it becomes to have an address used by another mode (mode 2), the address is skipped (count-up / down), The output of the address decoder circuit 3 is encoded by one encoder circuit 5 .

[0009]

[Effects of the Invention] As described above, according to the present invention,
One encoder circuit can handle addresses in a plurality of modes, so that the chip area can be reduced and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an example of the operation of the circuit in FIG. 1;

FIG. 3 is a block diagram showing a configuration of an example of a conventional decoder / encoder circuit of this type.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control circuit 2 Address counter circuit 3 Address decoder circuit 4 Mode selector circuit 5 Encoder circuit 6 Unique address decoder circuit

Claims (1)

(57) [Scope of request for utility model registration] A control to which an up / down signal is input
And an address counter circuit to which an up / down signal from the control circuit is input.
An address to which an address signal output from the
Dress decoder circuit and unique address decoder circuit
And the output signal of the address decoder circuit is input
An encoder circuit and a mode
And the output signal of the mode selector circuit is
Address decoding input to the unique address decoder circuit
A da encoder circuit, the address signal outputted from the address counter circuit
There when different from the address of the specified mode of the plurality of modes, the unique address decoder circuit sends a skip signal to said control circuit, said control circuit, on the output from the address counter circuit <br An address decoder / encoder circuit characterized in that the address signal is skipped.