JP2602330Y2 - Simultaneous measurement of pulse width and peak value - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width and peak value simultaneous measuring device which measures the pulse width of an input pulse with high accuracy and also measures the peak value in synchronization.

In general, an input pulse to be measured is a pulse train having various pulse widths and peak values. For example,
2. Description of the Related Art In an optical disk device, when an optical pickup or a disk is evaluated, highly accurate measurement of a read waveform is required.

[0003]

2. Description of the Related Art Conventional measuring means manually evaluates a waveform chart obtained by a digital oscilloscope or a wave memory.

FIG. 3 shows a conventional measurement example. Regarding the measurement waveform, measurement results of (1) the number of pulses, (2) the average pulse width, and (3) the area are obtained.

[0005]

The conventional measurement of the pulse width and the peak value has the following disadvantages.

[0006] When analyzing a waveform chart, it requires a considerable amount of manual work, and usually the number of data for producing one evaluation result is enormous (for example, 10 ⁶
Required), which is inefficient.

Further, the measurement of the pulse width and the peak value are performed by human eyes on the chart, and there is a problem that high accuracy cannot be obtained.

The present invention has been made in view of the above-mentioned problems of the prior art, and has a pulse width,
Simultaneous measurement and calculation of pulse interval and peak value, the pulse number and average pulse width and area can be obtained as final values, and a pulse width and peak value simultaneous measurement device that can obtain a modeled waveform display Is provided.

[0009]

[Means for Solving the Problems] In order to solve the above-mentioned problems
In the configuration of the present invention, a series of input pulses (signals to be measured)
In the case of measuring the pulse width and peak value of No.), measuring the
Comprises a first D / A converter 1 for generating a comparison voltage VT applying a predetermined threshold value to the constant signal, it receives a signal to be measured
Using the comparison voltage VT of the first D / A converter as a threshold
A first comparator 11 for converting and shaping into a compared logical signal is provided.
Measurement signal (leading edge signal of the signal under measurement) based on the comparator output.
And a measurement signal generation circuit 12 for generating a trailing edge signal).
And a continuous cycle measuring circuit 13 for measuring the pulse cycle is provided.
And one output terminal of the measurement signal generation circuit (before the signal under measurement)
Output signal of the continuous cycle measurement circuit
Is input by providing the first memory 14, and the pulse width is measured.
A time interval measurement circuit 15 for generating the measurement signal.
2 output terminals of the circuit (leading edge signal and trailing edge signal of the signal under measurement)
And output the output of the time interval measurement circuit to the second
A memory 16 is provided and input, and the peak measurement unit A17 increases the difference value.
Width device 201, peak hold circuit 202, and A / D converter
203 and a third memory 204, and the difference amplifier 20
At 1, the signal to be measured and the first D / A for giving a predetermined threshold
Receiving both signals with comparison voltage VT from converter 1
Signal is amplified and output to the peak hold circuit.
The path 202 receives the differential amplified signal and receives the differential amplified signal.
The pulse peak value of one polarity in the positive / negative voltage signal of
Hold and output a certain peak voltage and hold
The peak hold voltage is discharged by an external discharge signal
And the A / D converter 203 outputs the peak hold voltage signal.
Receives the A / D converted code data and outputs it to the third
The memory 204 receives the code data and sequentially stores data in the internal memory.
And the input of the signal to be measured with the above-described components.
Positive / negative with reference to the comparison voltage VT for the force pulse
The pulse height of one polarity at the negative pulse height
A peak measuring unit A17 for measuring is provided.
The same component as that of the part A17 is provided.
Peak connection condition of the positive / negative differential input value amplifier 201
It is connected in reverse to the measurement section A17 to generate a pulse of the signal under measurement.
On the other hand, positive / negative pulses using the comparison voltage VT as a reference level
Pulse height of the other polarity (ie opposite polarity) at peak value
A peak measuring unit B18 for measuring the value is provided.
As a discharge signal of the peak hold circuit of the measurement unit A17
Is a memory write signal generated by the continuous cycle measuring circuit 13.
Signal, and hold the peak of the peak measurement unit B18.
As the discharge signal of the circuit, the time interval measurement circuit 15
Connect the memory write signal generated by the
CPU 3 for executing the above-mentioned memory contents.
Equipped with a display 4 for displaying the calculation result,
Simultaneous measurement of pulse width and crest value
Device. FIG. 7 shows a solution according to the present invention.
I have. That is, in the above configuration, two systems of comparison voltages are generated.
First D / A converter 1 and second D / A converter 40
1 and outputs a comparison signal to be supplied to the measurement signal generation circuit 12.
A first comparator 11 and a second comparator 411 for generating a force
And the comparison power output from the first D / A converter 1 is provided.
The pressure VTL is calculated by the second comparator 411 and the peak measuring unit A17.
And the ratio output by the second D / A converter 401.
The comparison voltage VTH is equal to the first comparator 11 and the peak measuring unit B1.
8 and controlled by the two systems of comparison voltages VTL and VTH.
Pulse width characterized by measuring the pulse width and peak value
And a peak value simultaneous measurement device.

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

In the present invention, a D / A converter for generating a comparison voltage is provided, a comparator for shaping a rising edge or a falling edge is provided, and a measurement signal generation circuit for generating a measurement signal based on an output of the comparator. , A continuous cycle measuring circuit to measure the pulse cycle, input the result to memory, provide a time interval measuring circuit to measure the pulse width, input the result to memory, and measure the peak value of the pulse A part A is provided to input the result to the memory, and a peak measuring part B for measuring the peak value of the opposite polarity to the peak measuring part A is provided to input the result to the memory. The result of each memory can be read and operated by the CPU. The obtained data can be displayed on a display in a waveform modeled as a rectangle or a triangle. In addition, it is possible to calculate measured amounts for (1) the number of pulses, (2) the average number of pulses, and (3) the area, and display the results.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

As shown in FIG. 1, a measurement signal generation circuit 12 is provided, and a measurement signal is generated based on a shaped output from the comparator 11. In the comparator 11, one input terminal has D
A comparison voltage set by the A / A converter 1 is applied, and an input signal is applied to another input terminal, and a comparison output is obtained for both positive and negative waveforms.

Further, a switch 2 is provided in a stage preceding the comparator 11 so that the connection between the comparison voltage from the D / A converter 1 and the input signal can be switched so that the connection can be input to the comparator 11 in a reverse combination. The purpose of using the switch 2 is to switch between the positive pulse measurement mode and the negative pulse measurement mode. When the duty ratio of the pulse width of the input signal exceeds 50%, the input signal is inverted and measured at 50% or less. Switch 2
FIG. 4 shows the relationship between the measurement position of each measurement unit and the position setting.

The configuration of the measurement signal generation circuit 12 is, for example, the first
It can be realized by the technique disclosed in Japanese Patent Application No. 3-270726 of the reference, and a waveform corresponding to the cycle is obtained at one output terminal, and the other one is obtained.
At the output of the set, a waveform corresponding to the time interval is obtained. Up
The operation of the main part according to the first reference is based on the leading edge of the input pulse.
Sets the first flip-flop and the input pulse
The second flip-flop is set on the trailing edge and the next input
Write output by the time interval measurement circuit before receiving a pulse
Pulse resets both flip-flops to their initial state.
Set. Note that the write pulse generation timing is
It takes time to complete the measurement of the time interval with the interval measurement circuit.
The write pulse is applied at the timing after the measurement is completed.
appear. On the other hand, the timing before receiving the next input pulse
Write pulse needs to be generated in the first reference
4 (a) B input and FIG. 4 (a) G write pulse
Timing chart). Therefore, the input pulse
As the condition of the generation interval, at least the generation of the write pulse
After the timing, the generation interval at which the next input pulse arrives
The input pulse is the measurement target. Under these conditions, the first
The leading edge of the flip-flop output is
The signal is detected as a leading edge signal
Used for measurement. Also, the first flip flop and the second flip flop
Input pulse from leading edge of both outputs of two flip-flops
Detected as a signal corresponding to the pulse width from the leading edge to the trailing edge of
It is output and used for pulse width measurement in a subsequent circuit.

Further, a continuous cycle measuring circuit 13 is provided at one output terminal of the measuring signal generating circuit 12 and connected thereto. The continuous period measuring circuit 13 can be realized by, for example, adding an A / D converter to the output terminal having the configuration shown in Japanese Patent Application No. 62-25326. The output data is the sum of the main count data and the fractional part data, and a cycle value is obtained. This cycle data is provided in the memory 14,
Write here.

Further, a time interval measuring circuit 15 is provided and connected to another set of output terminals of the measuring signal generating circuit 12. The time interval measuring circuit 15 is disclosed in, for example, Japanese Patent Application No. 61-139661.
Can be realized by adding an A / D converter to the output of the configuration shown in FIG. The output data is the sum of the main count data and the fraction data, and a pulse width value is obtained. The pulse width data is provided in the memory 16 and written therein.

Further, a peak measuring section A17 is provided. The inside of the peak measuring section A17 is configured as follows. First, the difference value amplifier 201 is provided, and the output voltage of the D / A converter 1 is supplied to one input terminal. The other input terminals are provided with input signals.
The output of the difference amplifier 201 is provided to a peak hold circuit 202. The voltage of the peak hold circuit 202 is discharged and reset at a timing immediately after writing to the memory of the continuous cycle measuring circuit 13. The holding voltage value is converted by the A / D converter 203 into data, and
Write to. Here, the first reference shown in the description of the first reference is used.
After completing the time interval measurement in the time interval measurement circuit of the reference
A write pulse is generated at this time.
The raw time is measured by the time interval measurement circuit 15 or the continuous cycle measurement circuit.
Analogue by the A / D converter additionally built in the path 13
Conversion from conversion of hold voltage to code data
After a lapse of time, a write pulse is generated. This writing pal
Is the discharge timing, and the peak measurement unit A17 or
Are the peak hold circuits 202, 3 of the peak measuring section B18.
02 to discharge the hold voltage.

Further, a peak measuring section B18 is provided. The inside of the peak measuring section B18 is configured the same as the above-described peak measuring section A17. However, connect as follows. That is,
As for the input of the difference value amplifier 301, an output voltage of the D / A converter 1 is supplied to one input terminal, and an input signal is supplied to another input terminal. Accordingly, the peak to be measured can be always limited to a positive value in both the peak measuring unit A and the peak measuring unit B. The voltage of the peak hold circuit 302 is reset by discharging the held voltage at a timing immediately after writing to the memory of the time interval measuring circuit 15. The holding voltage value is A /
The data is converted by the D converter 303 and written into the memory 304. Here, first, the pulse peak value has the following meaning.
You. That is, the differential amplifier 201 amplifies and outputs the amplified differential value.
It means a positive peak value in the width signal. One peak
In the measuring section A17, the input pulse signal is non-inverted and amplified.
The positive peak value is the pulse peak value, and the other peak
The input pulse signal is inverted and amplified in the constant section B18,
The obtained positive peak value is the pulse peak value. Therefore, the opposite pole
Pulse peak value is the peak value of one peak measuring unit A17.
The pulse of the other peak measuring unit B18 for the peak value
It is a wave peak value.

A clock to each circuit is provided by providing a clock generator 6. Further, a CPU 3 is provided to read out the contents of each memory and transfer data. The occurrence of reset and a series of controls are performed through the operation unit 5, and the obtained data and the like are displayed on the display unit 4.

FIG. 2 shows the operation according to the timing chart.

The input signal is a negative pulse. Therefore, the switch 2 is set to the negative pulse width measurement mode. Operation unit 5
From the CPU 3 through the CPU 3. With this reset pulse, the peak hold circuit 202 is reset by discharging through the OR gate 19. Similarly, the peak hold circuit 302 is reset by discharging through the OR gate 20. Further, the continuous cycle measuring circuit 13 and the time interval measuring circuit 15 are also reset.

On the other hand, the peak hold circuit 302 starts operating immediately after the discharge, and holds the peak value of the difference amplifier 301. In this case, it holds the value of V _1. Similarly peak hold circuit 202 holds the peak value V ₂ of the difference value amplifier 201.

Next, the positive output of the comparator 11 is connected to the trigger terminal of the flip-flop 101 inside the measurement signal generation circuit 12. A high level is connected to the data terminal of the flip-flop 101. Therefore, the flip-flop output is inverted by the rising edge of the input signal.

Next, the negative output of the comparator 11 is connected to the trigger terminal of the flip-flop 102 inside the measurement signal generation circuit 12. The output of the flip-flop 101 is connected to the data terminal of the flip-flop 102.
Therefore, the flip-flop 102 is inverted by the falling edge of the input signal. Accordingly, the time difference between the two signals supplied to the time interval measuring circuit 15 is the pulse width W ₁
Is shown. After a certain time after the flip-flop 102 is inverted, the time interval measuring circuit 15 generates a write pulse to the memory 16. The write pulse resets the flip-flop 102 via the OR gate 20.
At the same time, the flip-flop 101 is also reset. Usually, the certain time is a time in which the time interval measuring circuit 15 takes time required for internal processing.

The write pulse causes the memory 304
Then, the data obtained by A / D conversion of the peak hold value is written to. The write pulse enters the peak hold circuit 302 via the OR gate 20 and starts discharging. Therefore, the time t ₁ up to this discharge is A / A of the peak hold value.
The time required for the D conversion is set to a value that allows for sufficient time.

Next, the next pulse of the input signal is applied to the trigger terminal of the flip-flop 101 in the measurement signal generation circuit 12. The continuous cycle measuring circuit 13 measures the time difference between this pulse and the previous pulse. This is the period P ₁
Is shown. The continuous cycle measuring circuit 13 generates a write pulse after the time t ₂ , similarly to the time interval measuring circuit 15, writes data into the memories 14 and 204, and starts discharging the peak hold circuit 202.

As a result, the data contents shown in FIG. 5 are written in each memory. Based on this data, FIG.
A screen as shown in (a) can be drawn and displayed on the display.
FIG. 6A shows a figure modeled as a rectangle. FIG.
(B) is a figure modeled by a triangle. However, in the case of this figure, it is necessary to calculate the formula in the shaded portion, and the waveform after this calculation is shown.

In each screen shown in FIG. 6, a waveform can be placed in a Vt plane on which an absolute value is scaled, like an oscilloscope. By displaying such a screen,
(1) An outline of a waveform can be grasped without an oscilloscope. (2) There is an advantage that the state of lack of data acquisition can be seen at a glance by comparing with a waveform of an oscilloscope.

Further, the required measurement amount described in the description of the prior art can be obtained as follows. (1) The number of pulses is obtained from the number of data stored in the memory 16. W ₁
There are four from to W _4. (2) The average pulse width is obtained by applying the following equation. (W ₁ + W ₂ + W ₃ + W ₄ ) / 4
(3) When the comparison voltage is V _REF , the area is (V _REF +
V _2i-1 ) / V _REF can be obtained by rounding down the decimal point and converting it to an integer, and calculating the sum from i = 1 to i = n. Here, the value of V _REF may be given as a constant or may be calculated as follows. That is, the value of V _2i is added from i = 1 to i = n−1, and the number is added to (n−
It may be obtained by dividing by 1), that is, by calculating an average value.

In FIG. 1, a switch is used for each mode switching between the positive pulse width measurement and the negative pulse width measurement, but the following configuration may be used without using this switch. That is, (1) inversion may be performed on the output side of the comparator, and (2) the write pulses reaching the peak measurement unit A and the peak measurement unit B may be exchanged with each other to realize the above.

In the above embodiment, one type of the comparison voltage _VT is generated from the D / A converter, and one comparator is used. As another embodiment, two comparators may be provided, and two D / A converters may be provided so that each threshold level can be individually set.

FIG. 7A shows this embodiment. Comparator 4
11 is provided, and the output of the D / A converter 1 is connected to one input terminal. Input signals are connected to other input terminals. The output terminal of the comparator 411 is connected to the trigger terminal of the flip-flop 102 in the measurement signal generation circuit 12. Next, a D / A converter 401 is provided. The output terminal is connected to one input terminal of the comparator 11. The output of the D / A converter 401 is also supplied to the difference amplifier 301. The D / A converter 1 has a threshold
The level _VTL is generated, and the D / A converter 401 generates a threshold level _VTH . Thus, with two different threshold levels, the pulse width measures from the rising edge across V _TH to the falling edge across V _TL . By using a plurality of comparators in this way, it is possible to detect the effects of irregular waveforms and noise, and to suppress the effects of noise. Although FIG. 7 is limited to the positive pulse width measurement mode, a negative pulse width can be measured by providing a mode switch or the like.

In the output of the peak hold circuit 202 in the waveform shown in FIG. 2, V ₂ is not always detected depending on the condition, and the immediately preceding peak is V 2.
_{If it is} larger than ₂ , the value may be retained. In this case, as another embodiment, an additional circuit is added as shown in FIG. A flip-flop 419 is provided, and a reset signal is connected to a reset terminal. The output terminal of the flip-flop 101 is connected to the trigger terminal of the flip-flop 419. Accordingly, the output of the flip-flop 419 becomes low level only when the flip-flop 101 is inverted, and thereafter, the peak hold circuit starts operating. That is, the peak V ₂ is accurately peak-held.

[0047]

[Effects of the Invention] As described above, the present invention has the following advantages.

By simultaneously measuring and calculating the pulse width, pulse interval, and peak value, the pulse number, average pulse width, and area can be obtained as final values, and a pulse width that can obtain a modeled waveform display. And a peak value simultaneous measurement device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a timing chart of the present invention.

FIG. 3 shows a conventional measurement example.

FIG. 4 is an explanatory diagram of a relationship between each measurement site and a switch position setting.

FIG. 5 is an explanatory diagram of data contents of each memory.

FIG. 6 is an example of a modeled graphic display.

FIG. 7 shows another embodiment having two comparators.

FIG. 8 shows another embodiment in which an additional circuit is added.

[Explanation of symbols]

 1, 401 D / A converter 2 Switch 3 CPU 4 Display 5 Operation unit 6 Clock generator 11, 411 Comparator 12 Measurement signal generation circuit 13 Continuous cycle measurement circuit 14, 16, 204, 304 Memory 15 Time interval measurement circuit 17 Peak measuring unit A 18 Peak measuring unit B 101, 102, 419 Flip-flop 201, 301 Difference value amplifier 202, 302 Peak hold circuit 203, 303 A / D converter

Claims (2)

(57) [Scope of request for utility model registration] When a pulse width and a peak value of a series of input pulses (signals to be measured) are measured , a comparison voltage (V) for giving a predetermined threshold value to the signal to be measured.
T) , a first D / A converter (1 ) for generating a signal to be measured, receiving a signal under measurement , and comparing the first D / A converter with a reference voltage
(VT) is used as a threshold to convert and shape a logical signal compared
A first comparator (11) is provided, and a measurement signal generation circuit (12) for generating a measurement signal ( leading edge signal and trailing edge signal of the signal under measurement ) based on the comparator output is provided, and a pulse period is measured. A continuous period measuring circuit (13) is provided, and one output terminal of the measuring signal generating circuit (before the signal under measurement)
Edge signal) , and inputs the output result of the continuous cycle measuring circuit by providing a first memory (14) and providing a time interval measuring circuit (15) for measuring a pulse width to generate the measurement signal. 2 output terminals of the circuit (before the signal under test
Edge signal and trailing edge signal) , and the output result of the time interval measurement circuit is input by providing a second memory (16). The peak measurement unit A (17) is connected to the difference amplifier (201)
Hold circuit (202) and A / D converter (203)
A third memory (204), and the difference amplifier (20)
In 1), the signal to be measured and the first D
/ A converter (1) and the comparison voltage (VT) from the two signals
And amplifies the difference signal between the two signals to a predetermined value and outputs the amplified signal.
A hold circuit (202) receives the differential amplified signal.
One of the positive / negative voltage signals of the differential amplified signal
Hold and output the peak voltage of the
The held peak hold voltage is applied to an external discharge signal.
Signal, and the A / D converter (203)
Code data that has been A / D converted by receiving a hold voltage signal
And the third memory (204) outputs the code data.
And stores them sequentially in the internal memory.
And the reference voltage for the input pulse of the signal under test
(VT) as the reference level.
A peak measuring unit A (17) for measuring a pulse peak value of one polarity, which has the same components as the peak measuring unit A (17),
Positive / negative differential input of the difference amplifier (201)
The connection condition of the force end was set in the opposite way to that of the peak measurement unit A (17).
Subsequently, a comparison voltage (VT) is applied to the pulse of the signal under measurement.
At the positive / negative pulse peak value with reference to
A peak measuring unit B (18) for measuring the pulse peak value of the polarity (that is, the opposite polarity) , and the discharge signal of the peak hold circuit of the peak measuring unit A (17) is the continuous cycle measuring circuit (13). A memory write signal generated from the time interval measuring circuit (15) is connected as a discharge signal of the peak hold circuit of the peak measuring unit B (18). And a display (4) for displaying the operation result of each of the above-mentioned memory contents. A simultaneous pulse width and peak value measuring apparatus comprising: . 2. A measurement signal generation circuit according to claim 1, further comprising a first D / A converter and a second D / A converter for generating two systems of comparison voltages. First comparator (11) and second comparator (411) for generating a comparison signal output to be supplied to
And a comparison voltage (V ) output from the first D / A converter (1).
TL) is the second comparator (411) and the peak measuring unit A
(17), and the comparison voltage output from the second D / A converter (401).
(VTH) is the first comparator (11) and the peak measuring unit B
(18), and the pulse width and the pulse width are determined by the above two comparison voltages (VTL, VTH).
Pulse width and pulse height simultaneous measurement device and measuring the beauty peak value.