JP2596156B2 - Sync signal detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal detection circuit used for a television, and more particularly to a synchronization signal detection circuit capable of detecting a vertical synchronization signal from a D2 standard digital video signal.

[Conventional technology]

It is well known that a television receiver separates a horizontal synchronization signal and a vertical synchronization signal from a transmitted video signal and obtains an image on a CRT based on the synchronization signal.

In particular, recently, with the development of digital technology, this digital technology has been applied to television receivers, video equipment, and the like. As described above, various standards are adopted in the television system employing the digital technology.

FIG. 3 is a circuit diagram showing a conventional synchronization signal detection circuit for detecting a vertical synchronization signal from a digital video signal adopting the D2 standard.

Third synchronizing signal detecting circuit shown, a monostable multivibrator MM _A a constant T _A is connected a resistor R _A and capacitor C _A to assay time, resistance R _B and the capacitor assayed constant T _B time and C _B monostable multivibrator connected to MM _B is constructed by serially connected.

Further, both the multivibrator MM _A, MM _B is Yes so as to input a signal to the inverting input terminal, the multivibrator
MM _A outputs the signal from the inverting output terminal, the multivibrator MM _B is outputting a signal from the non-inverting output terminal. Both the resistors R _A and R _B are connected to the power supply V _CC .

The operation of such a conventional synchronous signal detecting circuit will be described with reference to FIG. In FIG. 4, the horizontal axis represents time T, and the vertical axis represents the on / off state of each signal.

First, both multivibrator MM _A, constant T _A when MM _B, T _B
, When the period of the horizontal synchronizing signal and T _H, and is determined as _{T H> T A> T H} / 2 2T H> T B / T H.

Here, the period of the input horizontal synchronizing signal (a) is, when the T _H as shown in the period T ₁ through T ₂ of FIG. 4, since the period of the signal (a) is greater than the time constant T _A, multivibrator MM _a returns from the output of the pulse to be only "0" time constant T _a in the initial state.

The cycle of the input horizontal synchronization signal (a) is the fourth
When the T _H / 2, as shown in the period T ₂ through T ₃ in figure since the period of the signal (a) is smaller than the time constant T _A, multivibrator MM _A is restored to the initial state while outputting "0" do not do.

Furthermore, the period of the input horizontal synchronizing signal (a) is, when it comes to T _H as shown in the period T ₃ after the FIG. 4, the signal (a)
Since the period of is greater than the time constant T _A, multivibrator MM _A returns from the output of the pulse as a time constant T _A Only "0" in the initial state.

On the other hand, the multivibrator MM _B is FIG. 4 of the period T ₁ through T
In _2, the pulse signal of the time constant T _A time constant T _B is less than the period (b) is because it is constantly input from multivibrator MM _A, the initial state while outputting a signal (c) always "1" Does not return to

However, the multivibrator MM _B is operated during the period T in FIG.
In ₂ subsequent Since the pulse signal from the multivibrator MM _A (b) is not input, after a lapse of constant T _B when the homeland T _2, and outputs a signal (c) of "0".

Again, from the multi-vibrator MM _A to time T ₃ after the "1"
When the pulse signal (b) is input, the multivibrator MM _B is "1" and outputs a signal (c) of, to continue this state.

 Thus, the vertical synchronization signal (c) can be detected.

[Problems to be solved by the invention]

However, the detection of the vertical synchronizing signal by the conventional sync signal detection circuit, a vertical synchronizing signal detected (c), the phase relationship between the input signal (a) is by a constant T _B when multivibrator MM _B As a result, the following problem occurs. That is, a capacitor C _B that determine the constant T _B time, or changes the value is the temperature of the resistance R _B, when changes or due to aging, the above-mentioned phase relationship is changed.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide a synchronous signal detecting circuit whose phase relationship does not change with temperature or the like.

[Means for solving the problem]

According to the present invention, (a) a signal Sa formed by extracting a leading edge of a horizontal synchronization signal detected from a digital video signal, a leading edge of a horizontal synchronization signal detected from the digital video signal, and a signal before the equalization pulse. Equalization pulse by exclusive ORing with the signal Sb formed by extracting the edge part
An equalizing pulse detector for detecting Sd, and (b) a signal Sc and a signal Sa formed by extracting a trailing edge portion of the horizontal synchronization signal and a trailing edge portion of the equalization pulse detected from the digital video signal, A horizontal sync detector that outputs a horizontal sync signal Se only when the time difference between these signals Sc and Sa coincides with a time difference other than the vertical sync period; (c) the horizontal sync signal Se is taken in as a reset signal and an equalization pulse The synchronization signal detection circuit is provided with a counter that counts Sd and outputs a vertical synchronization signal Sf when the count reaches two or more predetermined count values.

As described above, according to the synchronization signal detection circuit, a vertical synchronization signal having a fixed phase relationship can be obtained without being affected by external conditions or the like.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronization signal detecting circuit according to the present invention.

The equalization pulse detector 1 shown in FIG. 1 has a signal Sa formed by extracting the leading edge of the horizontal synchronization signal detected from the D2 standard digital video signal and a signal Sa detected from the D2 standard digital video signal. A leading edge portion of the horizontal synchronization signal and a signal Sb formed by extracting the leading edge portion of the equalization pulse are supplied. This equalizing pulse detector 1 comprises a signal Sa and a signal Sb.
The circuit configuration is such that an equalization pulse Sd can be obtained by taking the exclusive OR of

The signal Sa is also supplied to a horizontal synchronization detector 2 for detecting a horizontal synchronization signal other than the vertical synchronization period. The horizontal synchronization detector 2 also receives a signal Sc formed by extracting the trailing edge of the horizontal synchronization signal and the trailing edge of the equalization pulse detected from the D2 standard digital video signal. The horizontal synchronization detector 2 counts the time difference between the signals Sa and Sc, outputs the horizontal synchronization signal Se only when the time difference between the signal Sa and the signal Se is outside the vertical synchronization period, and outputs the signal Sa outside the vertical synchronization period. And signal
The circuit is configured not to output the horizontal synchronization signal Se when the time difference is shorter or longer than the time difference of Sc, that is, during the vertical synchronization period.

The equalizing pulse Sd and the horizontal synchronizing signal Se are given to the counter 3. The counter 3 is configured to count the equalizing pulse Sd only when the horizontal synchronizing signal Se is not input, and to output the vertical synchronizing signal Sf when the counter value reaches a certain value.

The operation of the embodiment configured as described above will be described with reference to FIG.

In FIG. 2, the horizontal axis represents time, and the vertical axis represents signals Sa to
The state of the signal Sf is taken.

The signal Sa and the signal Sb are input to the equalization pulse detector 1. The equalizing pulse detector 1 performs an exclusive OR operation of the signal Sa and the signal Sb, and does not output the equalizing pulse Sd during the period from t _{1 to} t ₂ and the time t _{3 in} FIG. period t ₂ ~t ₃
Outputs the equalization pulse Sd. Of course, any time t ₃ after the equalization pulse detector 1, it is needless to say that the same operation as the period t ₂ ~t ₃ if the vertical synchronization period.
This equalizing pulse Sd is supplied to a signal input terminal of the counter 3.

The signal Sa and the signal Sc are input to the horizontal synchronization detector 2. The horizontal sync detector 2 counts the time difference between the signals Sa and Sc in built-in counter of the time difference between non-horizontal synchronizing signal (period t ₂ ~t ₃ in FIG. 2) the count value is the vertical synchronization period The horizontal synchronization signal Se is output only when they match. If the time difference between the signal Sa and the signal Sc is shorter or longer than the time difference between the signal Sa and the signal Sc other than the vertical synchronization period, the horizontal synchronization signal
Se is not output. Therefore, the horizontal synchronization signal Se is not output in the vertical synchronization signal section. This horizontal sync signal
Se is input to the reset terminal of the counter 3.

The counter 3, but is reset each time the horizontal synchronizing signal Se is input (or period t ₁ ~t _2, time t ₂ later), equalizing pulses Sd Since in the vertical synchronization period not input horizontal synchronizing signal Se Will be counted. And counter 3
Outputs the vertical synchronization signal Sf at a predetermined position of the equalization pulse Sd, thereby detecting the vertical synchronization signal Sf.

Such an operation is thereafter performed for each vertical synchronization period to detect a vertical synchronization signal.

〔The invention's effect〕

As described above, according to the present invention, the vertical synchronizing signal is digitally detected, so that a vertical synchronizing signal having a constant phase relationship can be obtained without being affected by external conditions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment, FIG. 3 is a block diagram showing a conventional synchronous signal detecting circuit, and FIG. FIG. 9 is a timing chart for explaining the operation of the conventional device. 1 ... Equalization pulse detector, 2 ... Horizontal synchronization detector, 3 ...
…counter.

Claims (1)

(57) [Claims] 1. A signal Sa formed by extracting a leading edge of a horizontal synchronization signal detected from a digital video signal, a leading edge of a horizontal synchronization signal detected from the digital video signal, and a leading edge of an equalization pulse. Sb
An equalization pulse detector that detects an equalization pulse Sd by taking an exclusive OR with the same, and extracts a trailing edge portion of the horizontal synchronization signal detected from the digital video signal and a trailing edge portion of the equalization pulse. A horizontal synchronization detector that inputs a signal Sc and the signal Sa formed in the above manner, and outputs a horizontal synchronization signal Se only when a time difference between the signal Sc and the signal Sa matches a time difference other than the vertical synchronization period; A synchronization signal detection circuit which receives the signal Se as a reset signal, counts the equalization pulse Sd, and outputs a vertical synchronization signal Sf when the count reaches two or more predetermined count values. .