JP2591466B2 - Power amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifying circuit, and more particularly to an FET power amplifying circuit having improved high-frequency power amplifying efficiency.

[0002]

2. Description of the Related Art There is a so-called class F amplifier as a method for increasing the efficiency of a conventional high frequency power amplifier circuit. This class F amplifier is designed to increase the efficiency by short-circuiting or opening a high frequency in an output matching circuit.

This method has an effect that the efficiency can be increased only when the signal level is near the saturation output and the high-frequency level is high, but there is a problem that it has no effect in the linear region where the input signal level is low.

Therefore, a technique disclosed in Japanese Patent Application Laid-Open No. 62-274906 has been proposed, and the configuration is shown in FIG. The signal from the input terminal 1 is a DC cut capacitor 2
Grounded source FET (field effect transistor)
The signal is amplified by the input to the gate of No. 3 and led out to the output terminal 5 via the DC cut capacitor 4.

The input signal is envelope-detected by an envelope detector 13 and amplified by a DC amplifier 11 to become a control input of a drain voltage control power supply 12. The drain voltage control power supply 12 changes and controls the voltage of the drain power supply terminal 9 according to the control input. This voltage becomes the drain voltage of the FET 3 via the choke coil 6 for blocking AC.

The gate bias of the FET 3 is supplied from a gate power supply terminal 8 via an AC blocking choke coil 7.

In such a configuration, the envelope component of the input signal is detected by the envelope detector 13 and amplified by the DC amplifier 11 to become a signal for drain voltage control. Therefore,
The drain voltage control power supply 12 directly applies the voltage supplied from the drain power supply terminal 9 to the FET 3 when the level of the input signal is maximum, and controls the drain voltage to be zero when the input signal level is zero. Make

At this time, the gate bias is set so that the operating point of the FET 3 becomes the class B amplification. By setting the gate bias in this manner, the change in the drain voltage and the change in the output signal are matched, and the power amplification is performed. It is designed to increase efficiency.

[0009]

In the configuration of such a conventional power amplifier, an envelope detector 13 for detecting an envelope component of an input signal is necessary, and particularly, an envelope detector 13 such as a microwave or a millimeter wave is required. In the frequency band, this detection circuit needs to be provided in the high frequency section, and there is a disadvantage that the configuration becomes complicated.

Accordingly, an object of the present invention is to provide an FET power amplifier circuit which has a very simple structure and does not cause a decrease in efficiency even when the envelope level is reduced, when the envelope level of the input signal changes. It is to provide.

[0011]

According to the present invention, there is provided an FET power amplifier circuit of a common-source type, comprising: detecting means for detecting a gate bias current of the FET; and detecting a drain voltage of the FET according to the detection result. and a drain voltage control means for varying control seen including, the drain voltage control means
Is a negative peak value of the gate current according to the detection voltage.
So that the drain voltage is controlled to be substantially equal to
Thus , a power amplifier circuit characterized by the following is obtained.

[0012]

In the FET, the fact that the efficiency is best at a drain voltage where the gate bias current is equal to the negative peak value is used to change the drain level which changes due to the change in the envelope level of the input signal. The bias current is detected, and the drain voltage is controlled to change in accordance with the detection result.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals. In this example, the gate bias current of the FET 3 is detected by the detection circuit 10, and the drain voltage control power supply 12 is controlled in accordance with the detected current value to change the drain voltage of the FET 3 so that the efficiency becomes the best. It is.

FIG. 2 shows the characteristics of the FET. It is assumed that the voltage of the gate bias terminal 8 is set so that the drain current becomes zero when there is no input signal. The gate current initially flows in the negative direction as the input signal increases, and changes in the positive direction as the input signal further increases.

Further, the gate terminal voltage of the FET 3 also changes due to the voltage drop of the gate bias resistor R in accordance with the change of the gate current at this time. At this time, as shown in FIG. 2, the efficiency shows the maximum at the input power at which the output voltage starts to be saturated. Therefore, when the power amplifier is used with high efficiency, it is necessary to always use it near the saturation output.

Since the saturation output varies depending on the drain voltage supplied to the FET, in the case of a signal in which the envelope level of the input signal changes, the bias set point (drain voltage) is efficiently adjusted according to the input signal level. Needs to be changed so as to be optimal.

The gate current flows in both positive and negative directions.
The gate current that can be detected by the bias circuit 10 is an average current due to the AC blocking function of the choke coil 7, and the efficiency becomes substantially maximum near a negative peak value where the detected average current changes from the negative direction to the positive direction. .

Therefore, this gate average current is detected by the resistance R (voltage across R) of the gate bias current detection circuit 10, and this detection signal is used as a control input of the drain voltage control power supply 12 via the DC amplifier 11, The drain voltage of the FET 3 is controlled so that the current has a negative peak value.

In this way, the drain voltage is controlled in accordance with the envelope level of the input signal, and the gate current always operates near the negative peak value, resulting in good efficiency.

As the drain voltage control power supply, a DC-DC converter circuit can be used by a switching power supply, and the on / off duty of the switching element is controlled (PWM control) according to the detection current of the gate bias current detection circuit 10. Configuration.

For example, as shown in the circuit example of FIG. 3, a switching transistor Q1 is inserted in series with the primary side of a transformer T1, and this transistor Q1 is turned on / off by a PWM control circuit 20, so that a positive power supply terminal 9 is provided.
Is turned on and off. The AC voltage induced on the secondary side of the transformer T1 by this on / off is converted into a rectifier diode D
1 and D2, the coil L1 and the capacitor C1.
To make the drain voltage Vd of the FET3.

A control input (output voltage of the DC amplifier 11) is applied to the PWM control circuit 20, and the duty of the on / off pulse of the switching transistor Q1 is controlled in accordance with the control input.

An example of the drain voltage control power supply 12 is shown in FIG.
It is apparent that various modifications are possible without being limited to the above circuit.

[0025]

As described above, according to the present invention, when amplifying an input signal whose envelope level changes, the bias current of the gate bias circuit can be detected without providing a special envelope detection circuit. With such a simple configuration, there is an effect that an FET amplifier circuit always having the best efficiency can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an operation characteristic of an FET.

FIG. 3 is a diagram showing a specific example of the drain voltage control power supply 12 of FIG.

FIG. 4 is a diagram illustrating an example of a conventional FET power amplifier circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2, 4 DC cut capacitor 3 FET 5 Output terminal 6, 7 AC blocking choke coil 8 Gate bias power supply terminal 9 Positive power supply terminal 10 Gate bias current detection circuit 11 DC amplifier 12 Drain voltage control power supply

Claims (2)

(57) [Claims] 1. A grounded-source FET power amplifier circuit, comprising: detection means for detecting a gate bias current of the FET; and drain voltage control means for changing and controlling a drain voltage of the FET according to a result of the detection. See,
The drain voltage control means controls the gate voltage in accordance with the detection voltage.
So that the drain current is approximately equal to the negative peak value.
A power amplifier circuit characterized in that a voltage is controlled . 2. The detecting means comprises means for detecting the gate bias current and generating a detection voltage in accordance with the detected current, and the drain voltage control means controls a drain voltage of the FET in accordance with the detected voltage. 2. The power amplifier circuit according to claim 1, wherein the power amplifier circuit is configured to perform change control.