JP2590251B2 - Method of manufacturing probe head for semiconductor LSI inspection apparatus and inspection apparatus - Google Patents

Description

The present invention relates to a method of manufacturing a probe head for an inspection device of a semiconductor device represented by an LSI, and particularly to a method of forming a probe with high precision in a high-density and multi-pin configuration. The present invention relates to a manufacturing method suitable for such a method and a semiconductor LSI inspection apparatus using the same.

[Conventional technology]

As a probe head that contacts an electrode pad of a semiconductor LSI and transmits an electric signal to an inspection device, a conventional device includes, for example, a probe pin separately prepared in advance in a probe structure to form a test probe. It has a structure inserted into the through hole. Also, the tip of the probe pin needs to be sharpened to improve the electrical contact characteristics, and after fixing the probe pin to the probe structure,
A flat surface is obtained by cutting and polishing, and the tip is exposed and formed in a hemispherical or conical shape by etching. In addition,
Related devices of this type include, for example, Japanese Unexamined Patent Publication No.
No. 80067.

[Problems to be Solved by the Invention] The above-mentioned prior art does not consider the point of increasing the density of the probe pins and increasing the number of pins. There were the above issues. In other words, in the prior art, since the probe pins are individually inserted into the probe structure having a through-hole and assembled,
A high-precision insertion / assembly technique is required for increasing the density of probe pins and increasing the number of pins, and there is a certain limit. Furthermore, the tip of the inserted probe pin is spring-less, particularly in the case of the tip contacting the electrode pad (solder bump) of the semiconductor wafer, and is fixed in a certain area (1) to ensure the contact resistance characteristics between the pin and the pad. It is necessary to align the positions in the height direction and the horizontal direction within the chip) with high precision. In the prior art, the tip of the probe pin is formed by etching, but the necessity of improving the accuracy of the tip, especially, is not considered.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to improve a pin assemblability of a probe head portion and to realize a method of manufacturing a probe head for realizing a highly accurate and accurate pin setting, and a semiconductor LSI using the same. An object of the present invention is to provide an inspection device.

[Means for solving the problem]

The purpose of the high-density multi-pin configuration is to form an electrode pad on a wiring board, form a conductive layer for pad protection, and then form a photoresist layer on the pad. It is etched and removed in a cylindrical shape until the conductive layer is exposed, a pin probe forming material is grown in the place where the etching is removed, and the surfaces of the pin probe forming material and the photoresist layer formed on the substrate are smoothed and used. This is achieved by etching the pin tip into a pin-shaped structure with this minute smooth surface.

The configuration of the present invention will be described in detail below.

In other words, the present invention, when manufacturing a probe head that contacts an electrode pad of a semiconductor LSI and transmits an electric signal to the inspection apparatus main body, includes a multilayer wiring structure therein, and electrode pad patterns on both surfaces are arranged at predetermined intervals in advance. A first step of preparing the provided multi-layer wiring board; a second step of forming a pad protection conductive layer on one surface of the multi-layer wiring board as necessary; and on the pad protection conductive layer A third step of forming a photoresist pattern on the photoresist layer; a fourth step of forming a mask pattern on the photoresist layer with the center axis aligned with the electrode pad; and the photoresist using the mask pattern as a mask. A fifth step of forming a pattern for forming a conductive layer for forming a pin probe by etching the layer; forming a conductive pattern for forming a pin probe between the patterns; A sixth step of flattening the surface to a thickness corresponding to the required height of the probe; and a seventh step of forming a mask pattern having the same central axis as the electrode pad on the probe forming conductive layer. An eighth step of forming a pin shape by etching the probe-forming conductive layer using the mask pattern as a mask; removing the photoresist layer and removing an exposed portion of the pad protective layer by etching; And a tenth step of removing the mask pattern on the probe-forming conductive layer. .

More preferably, an eleventh step of plating the pin surface with corrosion resistance, a good conductor or high hardness is added to the above-mentioned tenth step.

The outline of a representative one of the inventions of the semiconductor LSI inspection apparatus disclosed in the present application will be briefly described as follows.

That is, a plurality of sample tables that are movably supported on a plate-like inspection object (semiconductor wafer) and a plurality of multi-layer wiring boards protruding from a multilayer wiring board disposed opposite to the inspection object mounted on the sample table. An inspection apparatus comprising a pin probe and performing a predetermined inspection by contacting an object to be inspected with the pin probe by relatively displacing the sample table with respect to the multilayer wiring board,
At least one of the multilayer wiring board and the sample stage is provided with a piezoelectric actuator for displacing the pin probe and the object to be inspected in a relatively approaching direction.

[Action]

After forming an electrode pad on a wiring board, a pattern for forming a conductive layer for forming a pin probe is formed by etching using a desired mask pattern using a substrate on which a conductive layer for protecting a pad is formed and a photoresist layer is formed on a conductive layer for protecting a pad. And
A conductive layer for forming a pin probe is formed using this pattern, the surface thereof is flattened to a thickness corresponding to the required height of the probe, and then the pin probe is etched by using a desired mask pattern. By forming them all at once, the pin assemblability of the probe head can be improved in increasing the number of pins with high density. Furthermore, the number of pin assembling steps can be reduced as compared with the case where the electrode pad and the pin probe forming conductor sheet are brazed, and defects due to brazing variations at the time of forming the probe head can be eliminated.

Further, by forming a mask pattern for pin formation by smoothing the probe substrate surface serving as a pin tip portion, and by undercutting such that a fine flat surface remains in a portion located at the center of the electrode pad portion, The variation in the height direction of the pin tip can be at the same level as the smooth surface of the probe board, and the variation in the lateral direction can be brought to a level close to the dimensional accuracy of the mask pattern. Pinning can be realized.

According to the above-described semiconductor LSI inspection apparatus, for example, the first object that is placed on the sample table is brought closer to a pin probe protruding from the multilayer wiring board to a predetermined distance by the displacement of the sample table. By bringing the test object into contact with the pin probe through the step and the second step of bringing the test object into contact with the pin probe by displacement by the piezoelectric actuator, the test object can be simply moved by the relative movement of the sample alone. Compared to the contact operation between the inspection object and the pin probe, excessive plastic deformation of the inspection object due to overshoot due to inertia of the sample stage and the drive system of the sample stage is avoided.

This prevents an unstable gap between the pin probe and the test object due to excessive plastic deformation of the test object when coming into contact with the pin probe. Contact can be stably maintained.

〔Example〕

Hereinafter, the present invention will be described specifically with reference to examples. First
FIG. 1 shows a manufacturing process for forming multiple pins on a multilayer wiring board 1 according to an embodiment of the present invention in the order of steps.

FIG. 1A shows a state after a step of forming a photoresist layer 2 on a multilayer wiring board 1 having a power supply layer, a signal layer (input / output), and a ground layer. The multilayer wiring board 1 is a thick-film ceramic substrate, and has tungsten-based electrode pads 3, 4 on both sides.
The pads 3 and 4 on both sides are electrically connected to each other via a wiring structure (not shown) in the substrate. For example, copper is vapor-deposited on the electrode pad portion 3 as the pad protection conductive layer 5. The electrode pad portion 4 is provided with nickel plating 6 and gold plating 7. A pad protection layer may be formed as needed. The photoresist layer 2 is coated with, for example, TF-20, a positive type resist manufactured by Shipley Co., Ltd., on which the pad protecting conductive layer 5 is formed, and the coating thickness is controlled by the height of the pin probe. did.

FIG. 1B shows a state after the step of forming a layer 9 for photolithography on the photoresist layer 2. As the photolithography processing 9, a 0.3 μm-thick aluminum vapor-deposited film is deposited as a light shielding film 8 on the photoresist layer 2, and further a 1 μm thick photo-deposited film is formed to pattern the light shielding film 8. A resist film 9 is formed.

FIG. 1C shows a state after the step of forming the mask pattern 10 on the photoresist layer 2. This photoresist layer 2
The pattern processing of the upper masks 8 and 9 is performed in accordance with normal photolithography processing by chemical etching (etching solution: phosphoric acid, nitric acid, acetic acid, crystal liquid) to form a pin probe forming pattern 10.

Next, as shown in FIG. 1 (d), the multilayer wiring board 1 is immersed in a resist developer 11 and irradiated with light 12 at the same time. When a positive resist is used, only a portion irradiated with light dissolves in the developer 11. By repeating such exposure and phenomenon continuously, as shown in FIG. 1 (e), an increase in the side development amount with respect to the photoresist layer 2 such that the side development amount is 10 μm or less at a resist film thickness of 150 μm. A small and highly accurate pin probe forming pattern was processed.

Next, as shown in FIG. 1 (f), a pin probe forming layer 13 is formed by plating. As the pin probe forming layer 13, a conductive material such as copper or a nickel copper alloy is formed by ordinary electroless plating or electroplating so as to fill the pin probe forming pattern.

FIG. 1 (g) shows that after the pin probe forming layer 13 is formed, the surfaces of the pin probe forming layer 13 and the photoresist layer 2 are flattened by grinding or polishing to keep the height of the pin probe constant. This is shown after the step.

FIG. 1H shows a state after the step of forming the mask pattern 14 on the flat surface. The mask 14 may be a metal mask or a photosensitive resist. In this case, chromium (Cr) is used, chromium is deposited on a flat surface, a photosensitive resist is applied thereon, a circular pattern is exposed and developed, and unnecessary portions are removed. The chromium film is etched with a potassium ferricyanide aqueous solution using the resist as a mask, and the chromium mask is etched.
14 is formed. Note that the center axis of the electrode pad portion 3 and the center axis of the mask 14 are formed so as to coincide with each other from the condition of pinning. In addition, as a metal mask used for the mask 14, molybdenum (Mo), titanium (Ti), tantalum (Ta),
Niobium (Nb), magnesium (Mg), silicon (Si), silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or the like may be used.

FIG. 1 (i) shows the state after the etching step of the pin probe forming layer 13 is completed. For example, when a nickel copper alloy is used as the pin probe forming layer 13 and chromium is used as the mask 14, (NH ₄ ) ₂ S ₂ O ₈ and NH ₄ Cl
Electrolytic etching or the like using a mixed aqueous solution. By controlling the conditions of the electrolytic etching, the undercut (also referred to as side edge or side corrosion) is positively utilized, and the pin probe forming layer 13 is left so as to leave the vicinity of the electrode pad portion 3 so as to have a desired shape. Remove. As a result, the etching surface 15 is formed with the mask 14 left.

Further, as shown in FIG. 1 (j), an unnecessary portion of the resist is removed, and then the exposed portion of the pad protecting conductive layer 5 is removed by electrolytic etching to form an electrically isolated pin probe 16. Then, the mask 14 at the tip of the pin probe 16 is removed by selective etching to form the pin probe 16 having a minute flat surface at the tip shown in FIG. 1 (k).

After the mask 14 is selectively etched in FIG. 1 (j), the exposed portion of the pad protection conductive layer 5 may be removed by electrolytic etching to form the pin probe 16.

After that, by forming a gold or rhodium plating film on the surface of the pin probe 16, electrical contact characteristics can be stabilized and improved.

Other materials may be used as the material of the pin probe 16. For example, when copper is used, when chromium is used as the mask 14, electrolytic etching is performed using an aqueous solution of copper sulfate, and etching is performed to the shape of the pin probe 16, and then the surface is coated with copper such as nickel (Ni). After a surface treatment such as plating or sputtering or vapor deposition with a metal having a higher hardness than that of the metal, quenching and alloying can be performed to form a pin probe having a higher hardness. Further, the material of the pin probe 16 is molybdenum (Mo), titanium (T
i), chromium (Cr), tantalum (Ta), niobium (Nb),
A copper-beryllium (Be) -based alloy or a copper base material whose surface is plated with a metal harder than copper may be used.

Immediately after completion of the steps up to FIG.
As shown in FIG. 2, after the unnecessary portion of the photoresist layer 2 is removed, as shown in FIG. 2 (b), the exposed portion of the pad protecting conductive layer 5 and the underlayer during etching of the mask 14 on the probe forming layer 13 are removed. By actively using the cut, the probe forming layer 13 is removed so as to have a desired pin probe shape, and the mask 14 at the tip of the pin probe 16 is removed as shown in FIG.
May be removed to form the pin probe 16. According to the present embodiment, a pit of the electrode pad portion 3 is 250 μm, a pin probe having a height of 100 μm and a width of 100 μm is 1000 pins / 10 mm.
^{Produced at} the density of the ^mouth . In addition, the accuracy of the height of the pin was within ± 10 μm. Further, in this embodiment, it is possible to form the pitch of the electrode pads 3 up to 50 μm while keeping the ratio between the height and the width of the pin probe at 1: 1. When the height of the pin probe is h and the pitch between the electrode pads is d, according to this embodiment, a pin probe satisfying h = 0.3 to 5d can be formed.

As another method for forming the pattern for forming the pin probe forming conductive layer shown in FIG. 1E, a photosensitive polyimide may be used instead of the photoresist layer 2. FIG. 3 shows a part of the embodiment in this case.

FIG. 3A shows that after the step of forming the pad protecting conductive layer 5 on the electrode pads 3 formed on the surface of the multilayer wiring board 1, a probe is almost required on the pad protecting conductive layer. This shows a state after the step of laminating and forming a photosensitive polyimide layer (manufactured by E Merck, Selectilux HTR3) 17 having a thickness corresponding to the required height.

FIG. 3 (b) shows a mask pattern 18 prepared by aligning the center of the mask pattern on the central axis of the electrode pad 3 for forming a pin probe, and using the mask pattern 18 as a mask. Light 19 on polyimide layer 17
Is shown. When the positive mask pattern 18 is used, the photosensitive polyimide layer 20 is hardened only in the portion irradiated with the light 19.

FIG. 3 (c) is a view showing a state after the light-irradiated photosensitive polyimide layer 20 is developed with a developing solution (E Merck, Selectilast HTRD) and thermally cured. The following steps may be performed under the condition that the photoresist layer 2 is replaced with a photosensitive polyimide layer, as in the case where the above-described photoresist layer 2 shown in FIG. 1 (e) is used. in this case,
As an etching solution for the photosensitive polyimide layer 20 after heat curing, a Losoliu HTR manufactured by E Merck may be used.

FIG. 4 is an explanatory view showing a main part of an inspection apparatus which is an embodiment using the probe pins of the present invention.

In the present embodiment, the inspection device is configured as a wafer prober in manufacturing a semiconductor device.

That is, on the sample stage 21 provided substantially horizontally,
A semiconductor wafer 22 (inspection object) is removably mounted.

A plurality of solder bumps 22a as external connection electrodes are formed on the surface of the semiconductor wafer 22.

The sample stage 21 is supported by a vertical drive unit 24 via, for example, a stepping motor via a vertical vertical shaft 23. The vertical drive unit 24 is further mounted on an XY stage 26 supported by a housing 25. Fixed.

Then, by moving the XY stage 26 in the horizontal plane in combination with the vertical movement of the elevation drive unit 24, the horizontal and vertical positioning of the sample stage 21 is performed.

Further, the sample table 21 is provided with a rotation mechanism (not shown) so that the sample table 21 can be rotationally displaced in a horizontal plane.

A base 27 is provided above the sample table 21 in a posture facing the sample table 21 in parallel, and a probe card 28 and the multilayer wiring board 1 are horizontally fixed to a surface of the base 27 facing the sample table 21. Have been.

On the multilayer wiring board 1, the pin probes 16 arranged at a predetermined pitch so as to match each of the plurality of solder bumps 22a formed on the semiconductor wafer 22 are formed vertically downward. The pin probe 16 is a cable connected to a wiring board 28 connected to the multilayer wiring board 1.
It is connected to the tester 30 via 29.

In this case, a base 27 supporting a probe card 28,
A piezoelectric actuator 31 such as a duplicate piezo element is interposed between the upper housing 25 of the base 27 and a plurality of driving power supplies via a plurality of cables 32 to each piezoelectric actuator 31. 33 is connected.

This piezoelectric actuator 31 is, for example, 100 to 1000 V
By applying a voltage of the order, an elongation of about 10 to 100 μm occurs in the length direction in proportion to the voltage.

The vertical movement of the pin probe 16 formed on the multilayer wiring board 1 is caused by the vertical strain generated in the piezoelectric actuator 31 in response to the voltage applied to the piezoelectric actuator 31 from the driving power supply 33. Is realized without causing overshoot or the like.

The plurality of drive power supplies 33 are connected to a microprocessor 35 via a control bus 34, and the microprocessor 35
It is a structure that is controlled collectively by.

Similarly, the elevation drive control unit 24a that controls the operation of the elevation drive unit 24 described above is connected to the microprocessor 35 via the control bus 34. Multi-layer wiring board 1 by actuator 31
And the fine movement of the sample table 21 in the vertical direction can be performed in cooperation.

As means for detecting the amount of vertical movement of the probe, the object to be inspected (the solder bump 22a or the surface of the semiconductor wafer 22) itself or the vicinity thereof can be measured by changing the optical path of the laser reflected by the object to be inspected. The position information of the sample table 21 by the laser displacement meter 36 that detects the position of the inspection object by detecting the position information is transmitted to a drive mechanism of the sample table 21 via a control bus 34 connected to a displacement sensor control unit 37. By performing the feedback control, it is possible to perform a precise elevation drive.

 Hereinafter, operations and effects of the present embodiment will be described.

A semiconductor wafer 22 is fixed on a sample stage 21, and the solder bumps 22 a formed on the semiconductor wafer 22 are transferred to a pin probe formed on the multilayer wiring board 1 by using an XY stage 26 and a rotating mechanism. Adjust the position just below 16. Thereafter, the elevation drive unit 24 is operated via the elevation drive control unit 24a, and the sample table 21 is raised to a predetermined height, whereby the tip of the pin probe 16 of the multilayer wiring board 1 and the sample table 21 are moved.
Is brought close to a predetermined distance in a state of contact or contact with the solder bumps 22a of the semiconductor wafer 22 placed on the semiconductor wafer 22.
(First Step) Next, by gradually applying a voltage to each of the plurality of piezoelectric actuators 31 to a predetermined value from each of the plurality of driving power sources 33, each of the piezoelectric actuators 31 is extended by a predetermined amount, The multi-layered wiring board 1 is lowered by a predetermined distance on the sample base 21 while maintaining the attitude parallel to the sample base 21 without causing overshoot or the like, and a plurality of pin probes 16 formed on the multilayer wiring base 1 are formed. Of each of the plurality of solder bumps 22a of the target semiconductor device by a predetermined amount.
And the solder bumps 22a are electrically connected to each other.

(Second stage) In this state, the cable 29 and the plurality of pin probes 16
The operation power and the operation test signal are transmitted and received between the semiconductor element formed on the semiconductor wafer 22 and the tester 30 via, for example, to determine whether or not the semiconductor element has the operation characteristic. The above-described series of operations is performed for each of the plurality of semiconductor elements formed on the semiconductor wafer 22, and whether or not the operation characteristics of all the semiconductor elements are appropriate is determined.

As a result, by using a probe head having a very small variation in the height direction of the tip portion of the pin probe, the semiconductor wafer is inspected by the series of operations described above, whereby the sample stage 21 and the drive system of the sample stage are driven. Excessive plastic deformation of the solder bump 22a due to overshoot due to inertia or the like prevents generation of an unstable gap between the pin probe 16 and the solder bump 22a. An inspection apparatus capable of stably maintaining contact with the apparatus can be realized.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to this invention, in the high-density multi-pin configuration of the probe pins, high-density and high-quality multi-pins can be collectively formed on the electrode pad portion of the wiring board, so that the assemblability of the pin stand is greatly improved. There is.

Furthermore, the direction variation at the tip of the pin can be at the same level as the smooth surface of the probe substrate, and the variation in the lateral direction can be at a level close to the dimensional accuracy of the mask pattern. Has the effect of significantly improving

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process for forming a multi-pin probe substrate according to an embodiment of the present invention.
3 (b) and 3 (c) are cross-sectional views showing another embodiment to be carried out subsequent to the manufacturing process (h) of FIG. 1, and FIGS.
(B) and (c) show the manufacturing processes (a) to (e) in FIG.
FIG. 13 is a cross-sectional view showing an example of another manufacturing process used in place of FIG. FIG. 4 is a diagram showing a main part of the semiconductor LSI inspection apparatus according to the present invention. DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board, 2 ... Photoresist layer, 3 ... Electrode pad part, 4 ... Electrode pad part, 5 ... Conductive layer for pad protection, 6 ... Nickel plating, 7 ... Gold plating, 8 ... light shielding film, 9 ... photoresist film, 10 ... mask pattern, 11 ... resist developer, 12 ... light, 13 ... pin probe forming layer, 14 ... mask, 15 ... etched surface, 16 ... Pin probe, 17 ... Photosensitive polyimide layer, 18 ... Mask pattern, 19 ... Light, 20 ... Photosensitive polyimide layer, 21 ... Sample stand, 22 ... Semiconductor wafer, 22a ... Solder bump , 23 vertical elevator shaft, 24 vertical drive unit, 24a vertical drive control unit, 25 housing, 26 XY stage, 27 base, 28 probe card, 29 …… Cable, 30 …… Tester, 31 …… Piezoelectric actuator, 32 …… Cable, 33 …… Driver Dynamic power supply 34 Control bus 35 Microprocessor 36 Laser displacement meter 37 Displacement sensor controller.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenji Tobita 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (56) References JP-A-54-148484 (JP, A) JP-A-51 -97547 (JP, A) JP-A-63-187642 (JP, A) JP-A-1-141379 (JP, A)

Claims (10)

(57) [Claims] 1. A method of manufacturing a probe head for transmitting an electrical signal to a main body of an inspection device by contacting an electrode pad of a semiconductor LSI, wherein an electrode pad for forming a pin probe is arranged on one surface. On the back surface, electrode pads for transmitting electric signals between the inspection device and the above-mentioned LSI electrode pads are arranged, and a wiring board is prepared in which the front and back surface pads are electrically interconnected. First
Forming a pad-protecting conductive layer on the electrode pad for forming the pin probe as necessary.
And a third step of laminating a photoresist layer having a thickness substantially equivalent to the height required for a probe on the wiring board including the pad protection conductive layer; and forming the pin probe. Forming a mask pattern in which the center of the mask pattern is aligned on the central axis of the electrode pad for performing the etching; and etching the photoresist layer using the mask pattern as a mask to form a pin probe forming conductive layer. A fifth step of forming a pattern for forming a pin; and a sixth step of forming a conductive layer for forming a pin probe between the patterns and flattening the surface to a thickness corresponding to a required height of the probe. A seventh step of forming a mask pattern on the conductive layer for probe formation, the center pattern of which is aligned with the electrode pad; An eighth step of etching the probe forming conductive layer using a mask to form a pin shape; a ninth step of removing the photoresist layer and etching away an exposed portion of the pad protection layer; A tenth step of removing the mask pattern on the probe-forming conductive layer.
A method for manufacturing a probe head for an inspection apparatus. 2. A method of manufacturing a probe head for transmitting an electric signal to a main body of an inspection device by contacting an electrode pad of a semiconductor LSI, wherein an electrode pad for forming a pin probe is arranged on one surface. On the back surface, electrode pads for transmitting electric signals between the inspection device and the above-mentioned LSI electrode pads are arranged, and a wiring board is prepared in which the front and back surface pads are electrically interconnected. First
A second step of forming a pad protecting conductive layer on an electrode pad for forming the pin probe. The second step includes a pad protecting conductive layer. A third step of laminating and forming a photosensitive polyimide having a thickness of about 4 mm; and a fourth step of preparing a mask pattern in which the center of the mask pattern is aligned on the central axis of the electrode pad for forming the pin probe. A fifth step of forming a pattern for forming a pin probe forming conductive layer by etching the photosensitive polyimide layer using the mask pattern as a mask; and forming a pin probe forming conductive layer between the patterns; A sixth step of flattening the surface to a thickness corresponding to the required height of the probe; and forming the electrode pad on the probe-forming conductive layer. A seventh step of forming a mask pattern having the center axes coincident with each other; an eighth step of etching the probe forming conductive layer using the mask pattern as a mask to form a pin shape; and the photosensitive polyimide. A ninth step of removing a layer and etching away an exposed portion of the pad protective layer; and a tenth step of removing a mask pattern on the probe-forming conductive layer. Of manufacturing a probe head for a semiconductor LSI inspection device. 3. An eighth step of etching and removing the photoresist layer subsequent to the seventh step; and etching and removing exposed portions of the conductive layer for forming a probe and the pad protective layer to form a pin probe. 3. A probe head for a semiconductor LSI inspection device according to claim 1, comprising: a ninth step of forming a mask pattern; and a tenth step of removing a mask pattern on the probe-forming conductive layer. Manufacturing method. 4. A conductor is provided on the pin surface following the tenth step.
4. The semiconductor LSI according to claim 3, further comprising an eleventh step of applying a metal plating having high corrosion resistance or hardness.
A method for manufacturing a probe head for an inspection apparatus. 5. A method of manufacturing a probe head for a semiconductor LSI inspection apparatus according to claim 4, further comprising a twelfth step of firing the metal plating applied to the pin surface, following the eleventh step. . 6. The conductive layer for forming a pin probe is made of copper (Cu).
-Nickel (Ni) based alloys, copper (Cu), tungsten (W), molybdenum (Mo), titanium (Ti), chromium (C
r), tantalum (Ta), niobium and (Nb), and beryllium (Be) -copper (Cu) alloy. Claim 1, characterized in that it is formed
6. The method of manufacturing a probe head for a semiconductor LSI inspection device according to 2, 3, 4, or 5. 7. When the height of the pin probe from the wiring board is h and the pitch between the base electrode pads of adjacent pin probes is d, the pad protecting conductive material satisfies h = 0.3 to 5d. 7. A layer and a conductive layer for forming a pin probe are formed by lamination.
A method for manufacturing a probe head for a semiconductor LSI inspection apparatus according to the above. 8. The wiring board according to claim 1, wherein said wiring board comprises a multilayer wiring board having at least three types of wiring layers each comprising a power supply layer and a signal input / output layer and a ground layer. , 5,6
Or a method of manufacturing a probe head for a semiconductor LSI inspection device according to claim 7. 9. The semiconductor LSI according to claim 8, wherein said multilayer wiring board comprises a ceramic multilayer laminate.
A method for manufacturing a probe head for an inspection apparatus. 10. A semiconductor device according to claim 1, wherein said semiconductor wafer is displaceably supported on a sample stage, and said semiconductor wafer is mounted on said sample stage.
10. The probe head for a semiconductor LSI inspection device according to any one of claims 9 to 9, wherein the sample stage is relatively displaced with respect to the multilayer wiring board to thereby form an electrode formed on the semiconductor wafer and the pin probe. A piezoelectric actuator for displacing the pin probe and the electrode of the semiconductor wafer relative to at least one of the multi-layer substrate side and the sample stage in a direction relatively approaching the multilayer substrate or the sample stage. A semiconductor LSI inspection device, comprising: