JP2587078Y2 - RAM data guarantee device - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RAM data guarantee device, and more particularly, to a RAM data guarantee device provided in a microcomputer (hereinafter referred to as a CPU) of an automobile control device.

[0002]

2. Description of the Related Art In a control device for a vehicle equipped with a CPU, a self-diagnosis result, that is, learning data or various data required at the next start of operation may be stored in a RAM. RAM provided in the control device
It is necessary to apply a predetermined power supply voltage in order to reliably hold the stored data in the memory. For this purpose, the conventional control device is provided with a device for ensuring that a predetermined power supply voltage is applied.

An example of a constant voltage power supply circuit for applying the voltage will be described with reference to FIG. In the figure, a constant voltage power supply circuit 5 supplies two power supply voltages (VCC, VDD) for a peripheral circuit and a CPU to a control device. The power supply voltage VCC is supplied only when the ignition switch SW1 is turned on, that is, during operation of the vehicle, whereas the power supply voltage VDD is supplied to the control device not only during operation but also during stoppage. this is,
This is because it is necessary to keep the RAM data in the CPU constantly at the power supply voltage VDD.

[0006] The regulator 6 operates only when the ignition switch SW1 is turned on.
(Usually 12 V) is transformed and adjusted to a predetermined voltage (for example, 5 V) to generate a stabilized power supply voltage VCC. on the other hand,
The regulator 7 constantly converts and adjusts the battery voltage VB to a predetermined voltage to generate the power supply voltage VDD.

In the comparator 8, the power supply voltage VCC generated by the regulator 6 is compared with the reference voltage Vr1, and when the power supply voltage VCC is lower than the reference voltage Vr1, a voltage drop signal PD is output. The CPU (not shown) stops operating. At this time, a current for holding data in a RAM (not shown) is supplied.

In the comparator 9, the power supply voltage VDD generated by the regulator 7 is compared with the reference voltage Vr2. When the power supply voltage VDD is lower than the reference voltage Vr2, a reset signal RESET is output. Reset. In this case, the data stored in the RAM is not guaranteed.

[0007] In the comparators 8 and 9, not the voltages on the output side of the regulators 6 and 7 but the voltage on the input side,
That is, the battery voltage VB or the ignition voltage I
GP (substantially the same as battery voltage VB) and reference voltage Vr
1, Vr2.

Next, a description will be given of a configuration of a CPU that holds RAM data with a power supply voltage VDD supplied from the constant voltage power supply circuit 5, with reference to FIG. In FIG. 3, data stored in the RAM 2 in the CPU 1a is held by the power supply voltage VDD. The flip-flop 3a is set by processing by software, and whether or not the data in the RAM 2 can be guaranteed is detected by the state of the flip-flop 3a.

The power supply voltage VDD is compared in a comparator 4 with a reference voltage Vr3 that can guarantee RAM data. When the power supply voltage VDD is lower than the reference voltage Vr3,
A clear signal is output to the flip-flop 3a. The flip-flop 3a is cleared by this signal.

Thus, when the flip-flop 3a is set, data in the RAM 2 is guaranteed. In other words, it can be recognized that the RAM 2 is reliably held at a voltage higher than the predetermined value, and is in a state where new data can be securely stored.

On the other hand, when the flip-flop 3a is cleared, it is recognized that the data in the RAM 2 cannot be guaranteed, and the reading of the stored data is prohibited.

[0012]

The above-mentioned conventional CPU has the following problems. CPU 1 shown in FIG.
Then, the monitoring circuit for determining whether the power supply voltage VDD with respect to the reference voltage Vr3 is high or low, ie, the comparator 4
It was built into U1. In such an analog circuit configuration, there is a problem that the area of the semiconductor chip in which the CPU 1 is incorporated becomes large, and the current consumption for holding the data stored in the RAM 2 also becomes large. Also,
CP composed of both logic and analog
On the production side of U1, there is also a problem that the inspection process becomes complicated.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a RAM data assurance device with a reduced number of parts and a simplified configuration.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the invention of the present application is incorporated into a CPU together with a RAM.
Rarely, a flip-flop circuit as RAM data guarantee display flag disposed in parallel with the RAM to the RAM data retention power supply, CPU, wherein the RAM is built
And a monitoring circuit for generating a reset signal when the power supply voltage for holding RAM data is equal to or lower than a reference value, wherein the reset signal of the monitoring circuit is input to a clear terminal of the flip-flop circuit. There is a feature in the configuration.

[0015]

According to the present invention having the above-mentioned features, when the voltage of the power supply for holding RAM data falls below a predetermined value, the flip-flop circuit is cleared by the clearing means outside the CPU, that is, the monitoring circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing a main part of a RAM data guarantee device according to an embodiment of the present invention. In FIG. 1, a CPU 1 is built in a control device of an automobile. The CPU 1 is provided with a RAM 2 for storing learning data and various data necessary for starting the next operation. The data stored in the RAM 2 is held by the data holding voltage VDD.
The data supply voltage VDD supply line is connected to a RAM
The flip-flop 3 is connected in parallel with the flip-flop 2. The flip-flop 3 is provided as flag means for indicating that the data holding voltage VDD is maintained at the reference voltage, that is, that the data of the RAM 2 is guaranteed.

The flip-flop 3 is normally set by software processing, and when the data holding voltage VDD becomes equal to or lower than the reference voltage, a reset signal RESET is input to a clear terminal to be cleared. As the reset signal RESET, C
The output from the monitoring circuit provided outside the PU1 is used.

For example, the reset signal RESET is
The reset signal RESET output from the comparator 9 of the constant voltage power supply circuit 5 shown in FIG. 2 may be directly input to the clear terminal of the flip-flop 3.

As described above, the present embodiment eliminates the voltage monitoring conventionally provided in the CPU 1 and
U1 has a circuit configuration consisting of only logic.

[0020]

[Effects of the Invention] As described above, according to the present invention,
Since the CPU has a circuit configuration including only logic, the area of the semiconductor chip constituting the CPU can be reduced, and the current consumption of the CPU can be reduced. Also, the inspection process at the time of manufacturing the semiconductor chip is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a CPU showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a constant voltage power supply circuit.

FIG. 3 is a main block diagram of a CPU showing a conventional technique.

[Explanation of symbols]

 1. CPU, 2. RAM, 3. Flip-flop

Claims (2)

(57) [Scope of request for utility model registration] 1. A RAM data assurance device provided in the motor vehicle control device, incorporated in the CPU with RAM, disposed in parallel with the RAM to the RAM data holding power RAM
A flip-flop circuit as a data assurance display flag,
A monitoring circuit that generates a reset signal when the M data holding power supply voltage is equal to or lower than a reference value, wherein the reset signal of the monitoring circuit is input to a clear terminal of the flip-flop circuit. RAM data guarantee device. 2. The monitoring circuit according to claim 1, wherein the monitoring circuit is provided in a constant voltage supply circuit external to the CPU and generates a reset signal when a voltage supplied from a vehicle-mounted battery is equal to or lower than a reference value. 2. The RAM data guarantee device according to 1.