JP2584841B2 - Packet switching control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] When a plurality of incoming buses and a plurality of outgoing buses are laid in a matrix, an intersection buffer memory is connected to each of the intersections of these buses. A packet switching control device for writing once in the intersection buffer memory designated by an internal address assigned to each input packet and then transmitting the packet from the corresponding outgoing line bus, the packet being handled in a packet network It is an object of the present invention to propose a packet switching control device which can be configured with a small-capacity memory as long as it is high-speed as an intersection buffer memory. And a header flag is assigned to the first block, and a trailer flag is assigned to the last block. Information, the write internal to detect the presence or absence of the block in the specified intersection buffer memory by an address, the block group in each time of detecting the absence to the intersection buffer memory, in the outgoing line bus side,
A plurality of output buffer memories are provided for each of the outgoing buses,
By sequentially scanning each of the intersection buffer memories connected to each of the outgoing buses, monitoring the blocks in each of the intersection buffer memories, and detecting the header flag,
The output buffer memory is secured and the subsequent block group is fetched and stored. When the trailer flag is detected, the stored block group is discharged and the output buffer memory is released.

[Industrial applications]

According to the present invention, a plurality of incoming buses and a plurality of outgoing buses are laid out in a matrix and an intersection buffer memory is connected at each intersection of these buses, and for each packet input from the incoming bus. The present invention relates to a packet switching control device that temporarily stores the packet in the intersection buffer memory specified by the assigned internal address and then transmits the packet from the corresponding outgoing line bus.

As a form of switching connection, a packet switching system has been widely adopted in addition to the conventional circuit switching system. This is because the packet switching method is optimal for a so-called multimedia service in which voice data, image data, computer data, and the like are commonly handled by one network. Also, in order to satisfy the demand for high-speed packet communication in recent years, packet switching mainly using hardware is being adopted.

[Conventional technology]

FIG. 10 is a diagram showing a bus matrix type packet switch as a premise of the present invention. In FIG. 1, a high-speed packet switch 1 includes a plurality of incoming buses 2, a plurality of outgoing buses 3, and an intersection buffer memory (for each intersection of these buses 2 and 3 wired in a matrix). M)
And 4. Before entering the packet switch 1, the packet PKT input from the input bus 2 is assigned an internal address AD. This is performed by a central processing unit (not shown), and one outgoing bus 3 is set according to the destination address (the other party) of each call. In the figure, addresses "11", "10", "01" and "0" are respectively assigned to four outgoing buses 3.
0 "is assigned, for example, packet PKT (a
bcde) has "10" and "11" designated as internal addresses AD, and branches to the outgoing line bus 3 corresponding thereto. At the time of branching, the packet PKT is once written in the corresponding intersection buffer memory 4. Note that a header indicating a destination address or the like is added to the head of each packet PKT, but is not shown.

Most of such a high-speed packet switch of the bus matrix type is constructed by hardware, and enables high-speed packet switching. Also, once the intersection buffer memory 4
And the data is transmitted to the outgoing line bus, so that it is not necessary to strictly synchronize the incoming line and the outgoing line, and the hardware configuration is simplified. In this case, it is necessary to use a high-speed memory such as ECL as each intersection buffer memory 4. The delay at the time of switching is made as small as possible so that the voice quality is not deteriorated particularly in the case of voice packets.

[Problems to be solved by the invention]

As for the intersection buffer memory, generally, the memory is slower as the memory has a larger capacity, and the memory is faster as the memory is faster. With the development of memory technology in the future, small, large-capacity, high-speed memories will be available at low cost, but at present, such memories are still difficult to obtain.

On the other hand, in the case of a multimedia service, data to be written to the intersection buffer memory includes various data such as audio data, image data, and computer data. this house,
For computer data, the packet length is several kilobytes
It can extend to For example, there is a case of data transfer between files. Such a large-capacity packet cannot be accommodated in one intersection buffer memory. Therefore,
The maximum packet length that can be accommodated is set in advance, and the packet length is restricted for the source of the packet data.

However, the performance of the memory is constantly improving, and the maximum packet length that can be accommodated may fluctuate (increase gradually). In this case, the user of the packet network must always be aware of the packet length, which causes a problem of inconvenient operation.

SUMMARY OF THE INVENTION An object of the present invention is to propose a packet switching control device which can be configured with a small-capacity memory as long as it is high-speed as an intersection buffer memory, without being conscious of the packet length of packets handled in a packet network. Things.

[Means for solving the problem]

FIG. 1 is a diagram illustrating the principle of the present invention. Note that the same components are denoted by the same reference numerals or symbols throughout the drawings. In FIG. 1, 11 is an input control means, 12 is an output control means, and 13 is an output buffer memory. The input control means 11 is provided for each incoming line bus, and the output control means 12 is provided for each outgoing line. Output control means 12
Is provided with an output buffer memory 13, from which the exchanged packet is transmitted on the line side.

(Operation)

First, before being input to the high-speed packet switch 1, each packet PKT is divided into a group of blocks BK of a fixed length. The bit length to be divided may be arbitrarily set, but it is necessary that the bit length be smaller than the memory capacity of each intersection buffer memory 4. Further, blocks are added to both ends of each packet PKT. One is the top block BK _s. This is provided with a header (H) flag, but also includes the internal address AD described above. The other is the last block BK _e , which is a trailer
er) A flag T is added to indicate that this is the end of one packet. In this way, if each packet is divided into a plurality of small blocks and handled as one transfer unit, the switching of each packet can be performed irrespective of the length of the packet.

In the incoming line bus side to this, with each input control means 11 is activated by the first block BK _s, detects whether the block BK is in the one cross point buffer memory 4 designated by the internal address AD. If there is a block BK, the transfer is stopped, the absence of the block BK is detected, and the transfer to the memory 4 is performed. Similar operations subsequent performed on a series of blocks BK, continues until it detects a trailer flag T in the last block BK _e.

On the other hand, on the outgoing bus side, each output control means 12 sequentially scans the intersection buffer memory 4 connected to the corresponding outgoing bus 3. The blocks in each memory 4 are monitored by this scan. Block BK is present, when the block is detected from the head block BK _s header flag H to be, one being first freed output buffer memory 13
To secure. The subsequent block group BK is fetched and stored in the secured memory 13. And the last block
When the trailer flag T in the BK _e is detected, the packet stored in the output buffer memory 13 is discharged and released.

〔Example〕

FIG. 2 is a diagram showing a simplified flow of a packet according to the present invention. When a packet PKT is input to an input buffer memory 21 provided in a stage preceding the input control means 11, each packet is read every fixed-length read clock. Block BK is input control means 11
Then, it is taken into the high-speed packet switch 1 via the incoming line bus 2. Further, the signal is sent to the outgoing line bus 3 via a predetermined intersection buffer memory 4. Note that a filter function unit (not shown) is provided at the input stage of each intersection buffer memory 4, and selects and captures only packets that match the internal address AD of the packets. According to this figure, 1
Block BK (shown by hatching) is output control means 12
It is understood that the data is fetched into a predetermined output buffer memory 13 through the above.

FIG. 3 is an explanatory diagram for clarifying inconvenience that may occur in the switching of FIG. When executing the block transfer shown in FIG. 2, it must be taken into consideration that the packet length of the packet varies in the multimedia service. For example, in the figure, the packet PKT1
Therefore, the packet length may be extremely long, and the packet PKT2 may have an extremely short packet length. Here, it is assumed that both the packet PKT1 and the packet PKT2 are sent out to the same outgoing bus 3 and that the packet PKT1 arrives at the input control means 11 earlier than the packet PKT2, and the packet PKT2 has an inherently shorter time. While the packet PKT1 has to be sent to the network via the output buffer memory 13 before long, the packet PKT1 has a long packet length, so that it has to wait for a considerably long time. That is, there is an inconvenience that the throughput is reduced in the packet PKT2.

FIG. 4 is an explanatory diagram for clarifying the significance of the output control means, and eliminates the inconvenience described in FIG. In FIG. 4, the demultiplexer 22 and the output control line
23 is newly shown. The output control means 12 sequentially scans each intersection buffer memory 4 of its own system. This scanning is performed via the output control line 23. On the other hand, the content of the memory 4 detected by this scan is also read via the output control line 23. In the scan, if the header flag H is detected, the output control means 12 secures one output buffer memory (empty output buffer memory) 13 released by the demultiplexer 22. If the output buffer memory 13 is provided up to the number of the input buses 2 at the maximum, packets from any of the input buses 2 can be handled almost in real time irrespective of the length of other packets. Will be taken in. That is, the throughput does not decrease for any packet. Then, when all of the series of block groups BK are fetched, the output buffer memory 13 may be released when the trailer flag T is detected by the scan.

FIG. 5 is a diagram showing an embodiment for implementing the method of the present invention, FIG. 6 is a state transition diagram schematically showing the operation of the input control means in FIG. 5, and FIG. FIG. 6 is a state transition diagram schematically showing the operation of the output control means in FIG. 5. First, in order to understand the outline of the operation, a description will be given from a state transition diagram. Referring to FIG. 6, state A is a state in which there is no packet PKT in the input buffer memory 21, and is an idle state B. After that, the packet is stored in the input buffer memory 21.
When the PKT is input, the state becomes a state in which transfer to the corresponding intersection buffer memory 4 is possible (state C). State D is a state in which the intersection buffer memory 4 is in use (waiting because another block BK is contained. If it is detected that the intersection buffer memory 4 is empty, a state E in transfer is detected.
And a series of subsequent blocks BK are sequentially taken into the memory 4. That is, the transfer is repeated for each block other than the trailer flag T. And trailer flag T
To return to the original idle state by transferring the block BK _e including.

Next, referring to FIG. 7, state A is a state in which there is no transfer block (BK _s , BK, BK _e ) in the intersection buffer memory 4. On the other hand, in the state B, the output control means 12 sequentially performs the above-described scan on each intersection buffer memory. That is, the scan pointer is incremented as 1 → 2 → 3... And returns to 1. In this scan, when it is determined that there is a transfer block in a certain intersection buffer memory 4, the state C is reached. State C transfers the transfer block to the output control means 12. This block is the header flag H
, Then enter state D. In state D, one of the plurality of output buffer memories 13 which has been released
Allocate output buffer memory. When the securing of the buffer memory 13 is completed, the scan pointer is updated according to the state B. At the time of the next scan, the next transfer block BK is read from the intersection buffer memory 4 and transferred (state C), and the state moves to state E. If it is neither the header flag H nor the trailer flag T, it is a transfer block of the packet data itself and is stored in the corresponding output buffer memory 13. In this case, each time one block is stored,
The scan pointer is updated (state B), and the next block is stored in the same manner when the scan comes again. When the trailer flag T is transferred in the state C, the state changes to the state F in response to the transfer of the trailer flag T. In state F, the output buffer memory
Drain the blocks (BK) in 13 and release them.

Referring to FIG. 5 based on the state transition described above, the input control means 11 receives a state notification from the input buffer memory 21 and stores a packet (PKT) in the input buffer memory 21.
If it is determined that there is, a transfer instruction is issued and the transfer instruction is taken into the self. On the other hand, the input control means 11 receives the status notification from the one intersection buffer memory 4 that matches the internal address AD, and writes the transfer block to the empty one.

The output control means 12 scans each intersection buffer memory 4 as described above, provides a status notification from the output control line 23, and issues a transfer instruction from the output control line 23 'if a transfer block has been written. Incorporate the contents into themselves. If the header flag is H, the output buffer memory 13 is secured first, and a series of transfer blocks subsequent to the memory 13 are fetched and the process continues until the store flag and the trailer flag T appear.

FIG. 8 is a diagram showing a specific example of the input control means, and FIG.
The figure shows a specific example of the output control means. First, referring to FIG. 8, a status notification is first received from the input buffer memory 21. That is, a notification of DATA READY or NOT READY (shown at the lower left of the figure) is received. When the input buffer memory state detection unit 35 detects DATA READY, it outputs a read request signal to the read control unit 31. As a result, a transfer instruction is issued to the input buffer memory 21. That is, a read clock is sent. In response, the first transfer block is transmitted by the data bus 37. This transfer block is applied to the decoder 32, the data register 34, and the header flag / trailer flag detector 36. First, when the detecting section 36 detects the header flag H, it supplies an initialization request signal to the read control section 31 to output a destination latch clock. The internal address AD described above is analyzed by the decoder 32 using this clock, and a destination selection signal corresponding to this AD is output. Thus, one intersection buffer memory 4 corresponding to AD is specified. On the other hand, the read control unit
31 outputs a write request signal and a data latch clock, and applies them to a write control unit 33 and a data register 34, respectively. Therefore, the transfer block is stored in the register 34. However, the write control unit 33 sends a status notification from the specified intersection buffer memory 4, that is, READY / NO
See T READY, if this is not READY, it will not be invoked. RE
If it is ADY, this intersection buffer memory 4 is empty and sends a write clock. As a result, the contents of the data register 34 are supplied to the buffer memory 4 via the data bus 38. When a certain number of write clocks are output, the write controller 33 sends a write end signal to the input buffer memory state detector 35, and starts the same operation for the next block. When the detection unit 36 finally detects the trailer flag T, it returns to the idle state B in FIG. 6, and resets (clears) a required portion.

Next, referring to FIG. 9, first, an intersection buffer scan signal is output by the intersection buffer memory scanner 42, and the intersection buffer memory 4 is sequentially scanned. When the state notification from the intersection buffer memory 4 is DATA READY by the intersection buffer memory state detection unit 46, the transfer block is being written, and a scan stop signal is transmitted to the scanner 42 once. I do. At the same time, a transfer instruction, that is, a read clock is sent from the read control unit 41 to the intersection buffer memory 4. In response to this, a transfer block is output from the intersection buffer memory 4 through the data bus 48. This transfer block is taken into the data register 45 by the data latch clock. At this time, the header flag / trailer flag detection unit
If it is detected at 47 that the header flag is H, an initialization request signal is output and the address conversion table 44 is driven. This conversion table 44 specifies the address of the output buffer 13 to be allocated to the intersection buffer memory where scanning is currently stopped, and generates a write address corresponding to this. This temporarily secures the area of the output buffer. Subsequent transfer blocks are taken into the area updated one by one from the write address.
Writing to the output buffer 13 is started by a write request signal from the read control unit 41, and the area is updated by an update clock. The write control unit 43 receives the write request signal and sends a write clock to the output buffer 13. After outputting a certain number of write clocks, the control unit 43 gives a write end signal to the scanner 42. This is a scan stop release signal. When the next scan comes over again and the detection unit 46 detects that the next transfer block should be transferred, the scan stops again,
The transfer block received from the data bus 48 is written to the output buffer 13. When the trailer flag T is finally detected by the detection unit 47, an initialization request signal is sent to the write control unit 43, and the stop of the scanning by the scanner 42 is released accordingly.

Since the header flag H and the trailer flag T are unnecessary on the line, they may be deleted when they are used.

〔The invention's effect〕

As described above, according to the present invention, there is no need to be conscious of the length of the packet length of the packet handled in the packet network, and the operation becomes easy. In addition, since the subdivided blocks are processed as one unit, the intersection buffer memory may have a small capacity, and a higher-speed memory can be used, so that the speed of packet switching can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the method of the present invention, FIG. 2 is a diagram illustrating a simplified flow of a packet according to the present invention, and FIG. 3 clarifies inconveniences that may occur in the switching of FIG. FIG. 4 is an explanatory diagram for clarifying the significance of the output control means, FIG. 5 is a diagram showing an embodiment for implementing the method of the present invention, and FIG. 7 is a state transition diagram schematically showing the operation of the input control means, FIG. 7 is a state transition diagram schematically showing the operation of the output control means in FIG. 5, and FIG. 8 shows a specific example of the input control means. FIG. 9 is a diagram showing a specific example of the output control means. FIG. 10 is a diagram showing a bus matrix type packet switch as a premise of the present invention. In the drawing, 1 ... high-speed packet switch, 2 ... incoming bus, 3 ... outgoing bus, 4 ... intersection buffer memory, 11 ... input control means, 12 ... output control means, 13 ... output buffer memory 21 Input buffer memory PKT Packet AD Internal address BK Block BK _s First block BK _e Last block H Header flag T Trailer flag .

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tomohiko Awazu 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Susumu Tominaga 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-62-221238 (JP, A) JP-A-61-216545 (JP, A) JP-A-63-94730 (JP, A)

Claims (2)

(57) [Claims] 1. A plurality of incoming buses (2) and a plurality of outgoing buses (3) arranged in a matrix, and a plurality of intersection buffers connected at each intersection of these buses (2, 3). A memory (4); and the input bus (2) provided for each of the input buses (2).
Input control means (11) for temporarily writing each packet (PKT) input from the buffer memory (4) designated by the internal address (AD) assigned to each packet (PKT)
And the packet (PKT) provided for each of the outgoing buses (3) and corresponding to the once written packet (PKT).
A packet switching control device having output control means (12) for reading out the data, temporarily storing it in an output buffer memory (13), and then sending it out to the line side, wherein each of said input control means (11) Are fixed length blocks (B
K), a series of blocks is received in which the first block (BKs) is provided with a header flag (H) and the last block (BKe) is provided with a trailer flag (T). The presence / absence of the fixed length block (BK) written in the intersection buffer memory (4) specified by the internal address (AD) is detected, and each time the absence is detected, the series of block groups are read one by one. A packet switching control device configured to write data into the intersection buffer memory (4). 2. A plurality of incoming buses (2) and a plurality of outgoing buses (3) arranged in a matrix, and a plurality of intersection buffers connected at each intersection of these buses (2, 3). A memory (4) provided for each of the input buses (2), and each packet (PKT) input from the input bus (2) being designated by an internal address (AD) assigned to the packet (PKT). An input control means (11) for temporarily writing to the intersection buffer memory (4); and an output line bus (3) provided for each of the output line buses (3) and corresponding to the once written packet (PKT).
A packet switching control device having output control means (12) for reading out the data from the output buffer memory, temporarily storing it in the output buffer memory (13), and sending it out to the line side. ), And each of the output control means (12) is arranged such that each of the packets (PKT) is a block (B
K), the first block (BKs) is given a header flag (H), and the last block (BKe) is given a trailer flag (T). Each of the intersection buffer memories (4) in which one is written is sequentially scanned to monitor the block in each of the intersection buffer memories (4), and the output of 1 is detected by detecting the header flag (H). The buffer memory (13) is secured and the subsequent series of blocks are sequentially taken into the output buffer memory (13) and stored, and furthermore, the stored series of blocks is detected by detecting the trail flag (T). A packet switching control device characterized in that a group is discharged on the line side to release the output buffer memory (13).