JP2581289B2 - Index pulse generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spindle motor control circuit in a magnetic disk drive, and more particularly, to an INDEX (index) pulse generation circuit in the circuit.

[Conventional technology]

For magnetic disks, the IN
The INDEX input pulse obtained by detecting the passage of the DEX hole on the INDEX sensor is input to the INDEX pulse generation circuit to monitor the rotation state of the disk. The INDEX pulse generation circuit generates a signal (hereinafter referred to as a READY signal) indicating that the rotation state of the spindle motor is normal if the INDEX input pulse is input at an appropriate time interval. Outputs INDEX output pulse synchronously.

FIG. 3A shows an example of a conventional INDEX pulse generation circuit. Input terminal 1 is referred to as H or below H in this circuit), so that READY output 5 of READY circuit 10 becomes H,
This is an input for setting to the READY state. Input terminal 2
In this circuit, input H to make READY output 5 LOW.
This is an input for setting a state (hereinafter referred to as L), that is, a non-READY state. The input terminal 3 is an input terminal for an INDEX input pulse, and the READY circuit 10 outputs a READY signal 5 indicating that the rotation state of the spindle motor is normal when this pulse is input at an appropriate interval. Output terminal 6
Is an INDEX pulse output terminal, which outputs an INDEX output pulse according to the INDEX input pulse at the same time when the READY signal 5 becomes H.

Next, an input / output timing chart in the conventional INDEX pulse generation circuit is shown in FIG. 3 (b), and the operation of the circuit will be described in more detail.

In particular, the case where the timing at which the READY signal falls or rises and the INDEX input or output pulse overlaps will be described.

First, it is shown in FIG. As an initial state of the circuit, the inputs 1, 2, and 3 are L and the output 5 is L, that is, a non-READY state.

Subsequently, at a point A in FIG. At this time, the state is the non-READY state as set in the initial state, and the output 5 is L, so that the INDEX output 6 remains L.

Next, when the input 1 is set to H at the point B in FIG. 3B and the READY circuit 10 is set to the READY state, the READY output 5 becomes H, the INDEX output 6 becomes H, and an INDEX output pulse is obtained. However, the time width of this pulse takes various values depending on the timing of input 1 and INDEX input 3. Assuming that INDEX input 3 is L at point C in the figure, INDEX output 6 is also L
And the INDEX output ends.

Next, when the next INDEX input pulse is input at the point D, the READY output 5 is already at H, so that an INDEX output pulse is obtained. The time width of the INDEX output pulse is determined in one way by the width of the INDEX input pulse.

Next, at the point E in the figure, when the next INDEX input 3 is inputted, the INDEX output 6 becomes H again. Here, when the input 2 is set to H at the point F and the READY circuit 10 is released from the READY state, the READY output signal 5 becomes L and the INDEX output 6 becomes L
It cuts off on the way. Therefore, the INDEX output pulse time width takes various values depending on the timing of the input 2 and the INDEX input pulse.

[Problems to be solved by the invention]

In the INDEX pulse generating circuit, consider a case where the obtained INDEX output signal is input to a plurality of peripheral devices and circuits to perform an operation.

With the conventional circuit described above, the READY signal change and INDEX
When the timing of the input or output pulse overlaps, the time width of the INDEX output pulse takes various values. Therefore, when a peripheral device is operated by this pulse, particularly when the pulse width becomes equal to or less than a certain value, the signal cannot be detected depending on the device, and it is conceivable that both the operating device and the non-operating device exist. In this case, the operation of the entire system including the INDEX pulse generating circuit and the peripheral device is inconsistent, and a normal operation cannot be performed.

[Means for solving the problem]

An index pulse generating circuit according to the present invention includes an input terminal for an index input pulse, a ready circuit for detecting that the rotation of the disk is normal based on the index input pulse, and an index input pulse and a ready signal for the ready circuit. It uses a holding circuit that holds the value of the ready signal that was latched during the input of the index input pulse and passes the ready signal when the index input pulse is not input, and uses the output of the holding circuit and the index input pulse. , And a circuit for controlling the presence or absence of an index output pulse.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1A shows a first embodiment of the INDEX pulse generating circuit according to the present invention.

In the conventional INDEX pulse generation circuit, FIG.
As shown in (b), when the READY output changes, the output of the INDEX pulse starts or ends regardless of the presence or absence of the INDEX input pulse and the timing.

However, in the first embodiment of the present invention shown in FIG. 1 (a), by adding the D-LATCH circuit 15, the INDEX
If an input pulse is being input (this circuit latches when H is input to the latch input), the D input is latched and the READY signal is not transmitted to the gate 16 even if the READY output 5 changes. The INDEX output 6 has a circuit configuration for holding the value of the INDEX output before the value of the READY output 5 changes.

Next, an input / output timing chart in the first embodiment of the present invention is shown in FIG. 1B, and the operation of the circuit will be described in more detail.

Here, in order to consider a case where the operation differs from that of the conventional INDEX pulse generation circuit, a case where a change in the READY output signal and the timing of the INDEX output pulse overlap will be described.

First, input as an initial state of the circuit shown in FIG.
1, 2 and 3 are L, and outputs 5 and 6 are L, that is, non-READY state.

Subsequently, at the point A in FIG. 1 (b), the pulse input to the INDEX input 3 starts and becomes H. At this time, the outputs 5 and 8 are not in the READY state as set in the initial state, but are in the L state.
The INDEX output 6 remains at L.

Next, when the input 1 is set to H and the READY circuit 10 is set to the READY state at the point B in FIG.
Since DEX input 3 is H, by the operation of LATCH circuit 15,
The output 8 is kept at L and the INDEX output 6 is kept at L.

Next, at the point C in FIG.
When the pulse input ends, the LATCH circuit 15 outputs the READY output 5
Is read, and its output is set to H, but the INDEX output 6 remains at L.

Thus, when the timing of the change of the READY output 5 from L to H and the timing of the INDEX input pulse overlap, no INDEX output pulse is generated.

Next, when the next INDEX input pulse is input at point D in the figure, the output 8 of the LATCH circuit 15 is already at H at point C, so that an INDEX output pulse is obtained according to the INDEX input pulse. The time width of the INDEX output pulse is determined in one way depending on the time width of the INDEX input pulse.

Next, when a pulse is input to the next INDEX input 3 at the point E in the drawing, the INDEX output 6 becomes H again, and I
The NDEX output pulse starts.

Here, input 2 is set to H at point F in FIG.
When the READY state of the circuit 10 is released, the READY output 5 becomes L, but the output 8 thereof remains H and the INDEX output 6 remains H by the operation of the LATCH circuit 15.

Next, at the point G in FIG.
When the EX pulse is completed, the LATCH circuit 15 reads the value of the READY output 5 as L, sets the output 8 of the LATCH circuit 15 to L, and sets the INDEX output 6 to L.

As described above, when the timing of the change of the READY output 5 from H to L and the timing of the INDEX input pulse overlap, an INDEX output pulse having a time width determined by the time width of the INDEX input signal is generated.

FIG. 2 (a) shows a second embodiment of the INDEX pulse generating circuit according to the present invention.

The second embodiment is a method that can be used in the case of an INDEX pulse generating circuit having a differentiating circuit for an INDEX input pulse. The output signal 7 and the READY output 5 of the differentiating circuit 13 operating when the input in FIG.
By inputting to the gate circuits 11 and 12 constituting a flip-flop (hereinafter referred to as RS-FF), the READY output 5 becomes L
INDEX input 3 when it changes from H to H and becomes READY state
Starts falling when the pulse ends,
The circuit configuration is such that the output 8 of the LATCH circuit becomes H and an INDEX output pulse can be output.

Next, FIG. 2B shows an input / output timing chart in the second embodiment of the present invention, and the operation of the circuit will be described in more detail.

Here, in order to consider a case where the operation is different from that of the conventional INDEX pulse generation circuit, a case where the change of the READY output 5 and the timing of the INDEX output pulse overlap will be described.

First, an input is made as an initial state of the circuit shown in FIG.
1, 2, and 3 are L, and the outputs 5, 8 are L, that is, a non-READY state.

Subsequently, at point A in FIG.
, The input of the pulse starts, and the level becomes H. At this time, the output is not in the READY state as set in the initial state, and the outputs 5, 8 are at L level, so that the INDEX output 6 remains at L level.

Next, when the input 1 is set to H at the point B in the drawing and the READY circuit 10 is set to the READY state, the READY output 5 becomes H but the output 7 of the differentiating circuit 13 remains L, so that the INDEX output pulse does not appear. L is maintained.

Next, at the point C in the figure, the input 3 is set to L, and when the input of the INDEX pulse is completed, the output 7 from the differentiating circuit 10 becomes H once and the output 8 of the RSFF is set to H, but the INDEX input 3 is completed. Therefore, the INDEX output 6 remains at L.

Thus, when the timing of the change of the READY output 5 from L to H and the timing of the INDEX input pulse overlap, no INDEX output pulse is generated.

Next, when the next INDEX input pulse is input at point D in FIG.
An INDEX output pulse is obtained according to the EX input pulse. The time width of the INDEX output pulse is determined in one way depending on the time width of the INDEX input pulse.

Next, at the point E in the drawing, when the next INDEX input pulse is input, the INDEX output 6 becomes H again, and the INDEX output starts.

Here, when the input 2 is set to H at the point F in the figure and the READY state of the READY circuit 10 is released, the READY output 5 becomes L, whereby the output signal 8 of the RS-FF becomes L, and the INDEX output 6 changes from H to L. Expires.

Therefore, the time width of this signal takes various values depending on the timing of the input 2 and the INDEX input pulse.

〔The invention's effect〕

As described above, the INDEX pulse generation circuit according to the present invention
When the EX pulse is being input, the READY signal changes from the READY state to non-RE.
When changing to the ADY state or changing from the non-READY state to the READY state, the INDEX output signal keeps the previous state and the output INDEX pulse width becomes constant. This has the effect that the operation can be performed more reliably.

[Brief description of the drawings]

1A is a diagram showing a first embodiment of the present invention, FIG. 1B is a timing chart according to the first embodiment of the present invention, and FIG. 2A is a second embodiment of the present invention. FIG. 2 (b) is a timing chart according to a second embodiment of the present invention, FIG. 3 (a) is a diagram showing a conventional INDEX pulse generation circuit, and FIG. 3 (b) is a conventional INDEX pulse generation 6 is a timing chart by a circuit. 1 ... READY set terminal, 2 ... READY reset terminal, 3
…… INDEX pulse input terminal, 5 …… READY output terminal, 6…
... INDEX pulse output terminal, 7 ... Differential circuit output, 8 ...
Hold circuit output, 10: READY circuit, 11, 16: 2-input AND
Gate, 12 ... Two-input OR gate, 13 ... Differentiator, 14 ...
... RS-flip-flop circuit, 15... D-LATCH circuit.

Claims (1)

(57) [Claims] An input terminal for an index input pulse, a ready circuit for detecting normal rotation of a disk based on the index input pulse, and inputting the index input pulse and a ready signal of the ready circuit. ,
A holding circuit that holds the value of the latched ready signal during the input of the index input pulse, and passes the ready signal when the index input pulse is not input, and outputs the output of the holding circuit and the index input pulse. And a circuit for controlling the presence or absence of an index output pulse.