JP2580078B2 - Instruction prefetch device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction prefetch apparatus capable of executing a task after a context switch at a high speed.

[0002]

2. Description of the Related Art In a conventional instruction prefetch device, instruction prefetch is performed at the time of task switching. Therefore, in a banking system CPU, saving of a register group does not occur, but instructions are fetched after bank switching. Since the task is executed, there is a problem that an idle cycle exists in the pipeline processing.

To solve this problem, a subroutine or a specific procedure is fetched in advance and made resident,
A method that does not create a wait state when executing a task has also been considered. However, according to this method, the prefetch queue is always occupied, and since there are many subroutines and specific procedures depending on the program, it is necessary to prepare the prefetch queue by the number.

On the other hand, when a large-capacity prefetch queue is provided, instructions are fetched until the prefetch queue becomes full, so that the bus is not released, so that the throughput of the currently executing process is reduced. There is a problem.

In order to solve this problem, when a memory is provided inside one chip, an instruction bus and a data bus are provided independently, and the instruction execution throughput is reduced by instruction fetch. The device is devised so that it does not decrease. However, when accessing an external memory, if the bus for instructions and the bus for data are made independent,
The LSI terminal cannot be used as an IO port. For this reason, a method is used in which the external bus is shared internally even if it is a separate bus, and the bus is not released when accessing the external memory, so that the throughput of the currently executing process is reduced. is there.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem, and eliminates an idle cycle state of a pipeline due to an instruction prefetch wait state at the time of task switching and does not release a bus. It is another object of the present invention to provide an instruction prefetch apparatus capable of avoiding a decrease in the throughput of a process currently being executed as much as possible.

[0007]

In order to achieve the above object, an instruction prefetch apparatus according to the present invention includes a memory unit accessed by an instruction prefetch for a currently executing task and a memory unit to be executed next. When the instruction prefetch for the task is different from the memory unit to be accessed, two types of instruction prefetch are performed at the same time.

[0008] Specifically, the solution taken by the invention of claim 1 is a two-system instruction prefetch queue used as an instruction prefetch queue for a currently executing task or an instruction prefetch queue for a task to be executed next. Means for switching between the role of the instruction prefetch queue for the currently executing task and the role of the instruction prefetch queue for the next task to be executed at the time of context switching, and the instruction prefetch queue for the currently executing task accesses If the memory unit does not match the memory unit accessed by the instruction prefetch queue for the task to be executed next, the instruction prefetch for the currently executing task and the instruction prefetch for the next task to be executed are executed in parallel And means for causing it to be.

Further, the instruction prefetch apparatus according to the second aspect of the present invention has a configuration as set forth in the first aspect, in order to avoid contention between the two types of ROM data when two types of ROM data simultaneously access two types of instruction prefetch queues. A bus that allows two types of ROM data to be simultaneously accessed to the two types of instruction prefetch queues, and one RO when two types of simultaneously accessed ROM data are simultaneously stored in the two types of instruction prefetch queues
A means for temporarily storing M data in a temporary save memory to avoid conflict between the two types of ROM data accessed at the same time is added.

The instruction prefetch device according to the third aspect of the present invention has a configuration according to the first aspect, in order to avoid contention between two types of ROM data when two types of ROM data simultaneously access two types of instruction prefetch queues. A bus that allows two types of ROM data to be simultaneously accessed to the two types of instruction prefetch queues; and a bus that allows two types of simultaneously accessed ROM data to be stored in the two types of instruction prefetch queues. A means is provided which includes means for avoiding contention between the two types of ROM data accessed simultaneously by invalidating the accessed instruction prefetch once and then performing the fetch operation again.

Further, the instruction prefetch apparatus according to the present invention has two instruction prefetch queues. When two instruction prefetch queues are not required, one instruction prefetch queue can be programmed or externally input. Is used as

[0012] Specifically, a solution taken by the invention of claim 4 is a two-system instruction prefetch queue used as an instruction prefetch queue for a currently executing task or an instruction prefetch queue for a task to be executed next. Means for connecting the two instruction prefetch queues and using them as a single instruction prefetch queue or two independent instruction prefetch queues by means of a flag. It is.

[0013]

According to the first aspect of the present invention, if the memory unit accessed by the instruction prefetch queue for the currently executing task does not match the memory unit accessed by the instruction prefetch queue for the task to be executed next, the current execution is performed. The instruction prefetch for the middle task and the instruction prefetch for the next task to be executed can be executed in parallel.

According to the second aspect of the present invention, when two kinds of ROM data accessed at the same time are simultaneously stored in the instruction prefetch queues of two systems, one of the ROM data is temporarily stored in a temporary saving memory, thereby simultaneously storing the two ROM data. The conflict between the two types of accessed ROM data can be avoided.

According to the third aspect of the present invention, when two types of ROM data accessed at the same time are simultaneously stored in two types of instruction prefetch queues, the instruction prefetch accessing the internal memory is once invalidated and then fetched again. , Two types of R accessed simultaneously
OM data competition can be avoided.

According to the fourth aspect of the present invention, it is possible to switch between two instruction prefetch queues by connecting the two instruction prefetch queues and use them as one instruction prefetch queue or two independent instruction prefetch queues. The instruction prefetch queue can be
When a system is not required, it can be used as an instruction prefetch queue of one system.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an instruction prefetch queue for a task that is currently being executed and an instruction prefetch queue for a task to be executed next that can independently specify the number of valid instruction bytes stored in an instruction prefetch queue of two systems. FIG. 3 is a diagram illustrating a configuration of a prefetch device.

The data in the ROM 1 is prefetched to the queue a3 or the queue b4 via the queue input selector 2 under the control of the queue switching control unit 15. From the ROM access control unit 5 via the address bus 18
Of the data access synchronization signal 1 from the ROM 1 at the timing when the data in the ROM 1 is input.
9 is output. If the task currently being executed uses the queue a3, the task to be executed next uses the queue b4. When the currently executing task is completed, the queue b
4 is switched to the task currently being executed, and the queue a3 is used for the task to be executed next. The switching operation between the queue a3 and the queue b4 is performed by the queue switching control unit 15 inverting the queue switching signal 17 at the input timing of the final operand decoding signal 16.

The queues a3 and b4 are provided with a valid byte number register a6 and a valid byte number register b7 indicating the number of valid bytes in the queue, respectively. The ROM access control is performed at the timing when the data access synchronization signal 19 is output. The obtained data byte number information 20 from the unit 5 is added to the value of the valid byte number register a6 or the valid byte number register b7 selected by the selector 8 by the queue switching signal 17 by the addition / subtraction unit 9, and the addition result is The data is stored in the valid byte number register a6 or the valid byte number register b7 selected by the selector 10 by the queue switching signal 17. The acquired data byte number information 20 is R
It indicates the number of bytes of data in OM1 prefetched in queue a3 or queue b4. ROM1 when executing instructions
Is used, the used data byte number information 21
Is input to the addition / subtraction unit 9 and is subtracted.

The byte number specification registers a11 and b12 are
This register is used by the user to specify the task to be executed or the number of instruction prefetch bytes of the next instruction.
And the queue b4. Byte number designation registers a11 and b12 and effective byte number registers a6 and b7
The prefetch enable signal 22 is input to the selector 10 when (valid byte number)-(byte number designation register) <0.

The instruction prefetch is performed by the queue switching control unit 1.
5, unlike the timing of switching the instruction prefetch queue for the currently executing task or the next task to be executed by the final operand decoding signal 16, the instruction prefetch for the currently executing task is preferentially performed. When the instruction prefetch queue for the currently executing task reaches the ROM valid byte number specified by the byte number specification register a11 or b12, the instruction prefetch for the task to be executed next is executed. The value of the effective byte number register a6 or b7 of the instruction prefetch queue for the currently executing task is the used data byte number information 21.
The instruction prefetching queue for the task to be executed next has an instruction of the task currently being executed before the instruction prefetch queue for the next task to be executed reaches the ROM effective byte number specified by the byte number specification register a11 or b12. Prefetch is performed. The instruction prefetch for the task to be executed next is fetched up to the number of bytes specified by the effective byte number registers a6 and b7 for the task to be executed next.

As described above, according to the present embodiment,
The instruction prefetch queue for the currently executing task is preferentially designated, and the number of bytes to be prefetched can be designated by the byte number designation register a6 or b7, so that the fetch operation can be processed smoothly and the instruction prefetch cycle can be optimally suppressed. Therefore, the bus can be quickly opened.

FIG. 2 shows that when the memory unit accessed by the instruction prefetch for the currently executing task is different from the memory unit accessed by the instruction prefetch for the task to be executed next, two types of instruction prefetch are simultaneously executed. FIG. 3 is a diagram illustrating a configuration of an instruction prefetch device that performs the instruction prefetch;

An executing instruction pointer (hereinafter referred to as current IP) IPa23 indicating the memory address of the currently executed instruction and a prefetch instruction pointer (hereinafter referred to as prefetch IP) IPa25 indicating the head address of the data to be prefetched are each used for the queue a3. Is a pointer provided in the queue b4
For current IPb24 and prefetch IPb26
Is provided.

The current IP flag 27 indicates the current IPa
23 and the current IPb 24, and the prefetch IP flag 28 switches between the prefetch IPa 25 and the prefetch IPb 26. The current IP flag 27 and the prefetch IP flag 28 are switched using the queue switching signal 31 as a trigger, and the currently executed prefetch IPa 25 or prefetch IPb 26
When the prefetch IPa25 or the prefetch IPb26 to be executed next has a different address space,
The prefetch IP flag 28 switches.

The value of the prefetch IPa 25 or the prefetch IPb 26 is output to the address bus 32 via the selector 29, accesses the ROM 1, and is input to the comparator 30. The comparator 30 determines which address space the output prefetch IP value is in, and inputs it to the prefetch IP flag 28 as space information 33. The space information 33 is temporarily stored, and when the stored space information is a memory space requiring an access wait cycle, the prefetch IP flag 28 is inverted,
Next, the prefetch IPa 25 or the prefetch IPb 26 to be executed is selected. If the selected prefetch IP is different from the currently executing prefetch IP,
The prefetch address is output via the selector 29.

FIG. 3 is a diagram showing an arbiter configuration of an instruction prefetch device that saves one of competing data when instruction data acquisition timings are overlapped when two systems of instruction prefetch are performed simultaneously.

When the prefetch of the currently executed task is access to the external memory 35 and the prefetch of the next task to be executed is the internal ROM 34, the external memory 35 and the internal ROM 34 transfer the ROM data to the data bus 39. When the output timing is the same and a bus conflict occurs, the internal data bus access synchronization signal 40 which is enabled at the timing when the internal ROM 34 outputs the ROM data to the data bus 39 and the external memory 35 transmits the ROM data A latch 36 for temporarily storing ROM data of an internal ROM 34 by an AND gate 38 which receives an external data bus access synchronization signal 41 enabled at the timing of outputting to a bus 39.
, A latch enable signal 42 is output to latch data, and output to the data bus 39 is prohibited to avoid data conflict. Next, the pulse of the external data bus access synchronizing signal 41 is delayed by the delay circuit 37 to which the external data bus access synchronizing signal 41 is input.
6 from the latch 36 to the data bus 39
OM data is output. With this arbiter timing, avoidance of data conflict can be realized by a simple control circuit.

FIG. 4 is a diagram showing the timing of the arbiter configuration of the instruction prefetch device that saves one of competing data when the instruction data acquisition timings overlap when two systems of instruction prefetch are performed simultaneously.

When the internal data bus access synchronization signal 40 and the external data bus access synchronization signal 41 are output at the same time, a latch enable signal 42 is generated, and the latch 36 latches the data and outputs the latched data. Are prohibited, and a high impedance state (not shown) is set. The external data bus access synchronizing signal 41 is turned into a latch output enable signal 43 by the delay circuit 37 to enable the data output of the latch 36.

FIG. 5 is a diagram showing an arbiter configuration of an instruction prefetch device that fetches one of competing data again when instruction data acquisition timings overlap when two systems of instruction prefetch are performed simultaneously.

When the prefetch of the currently executing task is access to the external memory 49 and the prefetch of the next task to be executed is the internal ROM 48, the timing at which the external memory 49 and the internal ROM 48 output ROM data is determined. At the same time, when a bus conflict occurs, an internal data bus access synchronization signal 54 that is enabled when the internal ROM 48 outputs ROM data to the data bus, and an internal data bus access synchronization signal 54 that is enabled when the external memory 49 outputs ROM data. A queue latch inhibit signal 56 for inhibiting the input of data of the internal ROM 48 to the queue 51 is output from the AND gate 52 that receives the external data bus access synchronization signal 55 as an input.
Avoid data races. Next, the pulse of the external data bus access synchronizing signal 55 is delayed by the delay circuit 53 to which the external data bus access synchronizing signal 55 is input, and the pulse is input to the address generating unit 50, and the address is generated again. Acquire data.

FIG. 6 is a diagram showing a configuration of an instruction prefetch apparatus which can be used as one instruction prefetch queue in a programmable or external manner when two instruction prefetch queues are not required.

The data in the ROM 57 is input to the queue a 59 or the queue b 60 by the queue input selector 58. The data of the ROM address indicated by the prefetch IPa61 is input to the queue a59, and the current IPa6
The data in the queue a59 indicated by 3 is output to the instruction decoding unit (not shown). Similarly, the queue b60, the prefetch IPb62, and the current IPb64 form a set. Prefetch IPa61 and Prefetch IPb
62 is switched by the prefetch IP switching unit 65. When the queue a59 or b60 is used for the task currently being executed or for the task to be executed next, the dual / queue mode is set by the single / dual queue switching signal 67, and the role of the queue a59 and the role of the queue b60 are set by the external switching trigger signal 70. The role is switched.

Single / dual cue switching signal 67
In the single queue mode, the prefetch IPa61 and the prefetch IPb62 take the same value, and the prefetch IPb62 (or the prefetch
The bit position 3 (bp3) 68 of a61) is operated as a flag of the prefetch IP switching unit 65 to determine which of the queues a59 and b60 is to be input. Similarly, when the single / dual cue switching signal 67 is set to the single cue mode, the current IPa 63 and the current IPb 64 take the same value and the current IPb
The bit position 3 (bp3) 69 of 64 (or the current IPa 63) is operated as a flag of the current IP switching unit 66, and the input to the queue a59 or b60 is determined by controlling the queue input selector 58.

As described above, according to the present embodiment,
Depending on the application of the system, the single queue and the dual queue can be arbitrarily switched, so that flexibility in system construction can be provided.

FIG. 7 is a diagram showing a queue management method of an instruction prefetch device that can be used as one instruction prefetch queue either programmatically or by external input when two instruction prefetch queues are not required.

The queue a71 shown in FIG.
The number in the queue b72 shown in (b) indicates the correspondence with the prefetch IP bp3 to bp0 or the current IP bp3 to bp0 in the single queue mode. Each of the queues a and b is composed of eight blocks. When bp3 to bp0 of the prefetch IP or bp3 to bp0 of the current IP is (0011), the (0011) block in the queue a is selected, and (1011) At the time of (1), the (1011) block in the queue b is selected.
Therefore, either queue a or b is selected by bp3 of the IP information, and a block is selected by bp2-0. In the single queue mode, 16 blocks are allocated to one task. On the other hand, in the dual queue mode, the correspondence between the prefetch IP bp3 to bp0 of the queue b or the current IP bp3 to bp0 is the same as that of the queue a (not shown), and the switching of the queues a and b is performed by the IP.
Instead of information, another signal such as an instruction end signal or the like is used as a trigger, and each block is selected by bp 2 to 0 of IP.
In the dual queue mode, eight blocks are allocated to one task, and thus are allocated to a maximum of two tasks.

[0040]

As described above, according to the first aspect of the present invention, the memory unit accessed by the instruction prefetch queue for the currently executing task and the memory unit accessed by the instruction prefetch queue for the task to be executed next Do not match, the instruction prefetch for the currently executing task and the instruction prefetch for the next task to be executed can be executed in parallel, and
Since the ROM data of the system bus can be prefetched,
The system throughput is improved.

According to the second aspect of the present invention, when two types of ROM data accessed simultaneously are stored in two instruction prefetch queues simultaneously, one of the ROM data is temporarily stored in a temporary save memory. By
Since conflict between two types of ROM data accessed simultaneously can be avoided, bus conflict can be avoided with a simplified circuit.

According to the third aspect of the present invention, when two types of ROM data accessed simultaneously are simultaneously stored in two types of instruction prefetch queues, the instruction prefetch accessing the internal memory is once invalidated and then fetched again. By operating, 2 accessed simultaneously
Since the conflict between the different types of ROM data can be avoided, the conflict between the buses can also be avoided with a simplified circuit.

Further, according to the invention of claim 4, two instruction prefetch queues are connected and used as one instruction prefetch queue, or two independent instruction prefetch queues are used.
Since it is possible to switch whether to use the instruction prefetch queue as a system by using a flag, it is possible to use the instruction prefetch queue as a system instruction prefetch queue in a system mainly using a single task, thereby improving the system throughput. .

As described above, according to the first to fourth aspects of the present invention, the throughput of the system can be improved with a simple configuration, so that an instruction prefetch device with a high practical effect can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating two types of instruction prefetch queues for storing the number of valid instruction bytes stored in an instruction prefetch queue for a currently executing task and an instruction prefetch queue for a task to be executed next according to an embodiment of the present invention; FIG. 3 is a diagram showing a configuration of an instruction prefetch device that can be specified independently of the instruction prefetch device.

FIG. 2 relates to an embodiment of the present invention, in which, when an instruction prefetch for a currently executing task and an instruction prefetch for a task to be executed next are different from each other, two types of instruction prefetch are simultaneously performed. FIG. 2 is a diagram illustrating a configuration of an instruction prefetch device that performs the instruction.

FIG. 3 is a diagram showing an arbiter configuration of an instruction prefetch device that saves one of competing data when instruction data acquisition timings overlap in a case where two systems of instruction prefetch are performed simultaneously according to an embodiment of the present invention. It is.

FIG. 4 is a timing chart of an arbiter configuration of an instruction prefetch device for saving one of competing data when instruction data acquisition timings overlap in the case where two systems of instruction prefetch are performed simultaneously according to an embodiment of the present invention. FIG.

FIG. 5 shows an arbiter configuration of an instruction prefetch device that fetches one of competing data again when instruction data acquisition timings overlap in a case where two systems of instruction prefetch are performed simultaneously according to an embodiment of the present invention. FIG.

FIG. 6 is a diagram showing a configuration of an instruction prefetch apparatus according to the present invention which can be used as one instruction prefetch queue in a programmable manner when two instruction prefetch queues are not necessary or according to an embodiment of the present invention when external instruction is required; It is.

FIG. 7 relates to a queue management method for an instruction prefetch apparatus according to the present invention, which can be used as one instruction prefetch queue in a programmable manner when two instruction prefetch queues are not required or according to an embodiment of the present invention. FIG.

[Explanation of symbols]

1, 57 ROM 2, 58 queue input selector 3, 4, 51, 59, 60, 71, 72 queue 5 ROM access controller 6, 7 effective byte number register 8, 10, 13, 29 selector 9 Addition / subtraction unit 11, 12 Byte number designation register 14 Subtractor 15 Queue switching control unit 16 Final operand decoding signal 17, 31 Queue switching signal 18, 32 Address bus 19 Data access synchronization signal 20 Acquired data byte number information 21 ... Used data byte number information 22 ... Prefetch enable signal 23,24,63,64 ... Executing instruction pointer (current IP) 25,26,61,62 ... Prefetch instruction pointer (Prefetch IP) 27 ... Current IP plug 28 ... Prefetch IP flag Reference Signs List 30 comparator 33 spatial information 34, 48 internal ROM 35, 49 external memory 36 latch 37, 53 delay circuit 38, 52 AND gate 39 data bus 40, 54 internal data bus access synchronization signal 41, 55: External data bus access synchronization signal 42: Latch enable signal 43: Latch output enable signal 50: Address generation unit 56: Queue latch inhibit signal 65: Prefetch IP switching unit 66: Current IP switching unit 67: Single / dual Queue switching signal 68 ... bit position 3 (bp) of prefetch IP
3) 69: bit position 3 (bp3) of current IP 70: external switching trigger signal

Claims (4)

(57) [Claims] 1. A two-system instruction prefetch queue used as an instruction prefetch queue for a currently executing task or an instruction prefetch queue for a task to be executed next, and an instruction prefetch queue for a currently executing task at the time of context switching. Means for switching between the role of the instruction prefetch queue and the role of the instruction prefetch queue for the next task to be executed, a memory unit accessed by the instruction prefetch queue for the currently executed task, and the instruction prefetch queue for the next task to be executed An instruction prefetch for a task currently being executed and an instruction prefetch for the next task to be executed in parallel when the memory unit to be accessed does not match Prefetch device. 2. The instruction prefetch device according to claim 1, wherein a bus capable of simultaneously accessing two types of ROM data to said two types of instruction prefetch queues and said two types of ROM data accessed simultaneously are stored in said two lines. When stored in the instruction prefetch queue of one system, one ROM data is temporarily stored in a temporary save memory, so that the two types of ROs simultaneously accessed are stored.
Means for avoiding contention of M data. 3. The instruction prefetch device according to claim 1, wherein a bus capable of simultaneously accessing two types of ROM data to said two types of instruction prefetch queues and said two types of ROM data accessed simultaneously are simultaneously stored in said two lines. Means for avoiding a conflict between the two types of simultaneously accessed ROM data by temporarily invalidating the instruction prefetch accessing the internal memory and performing the fetch operation again when the instruction prefetch is stored in the system instruction prefetch queue. An instruction prefetch device characterized by the above-mentioned. 4. An instruction prefetch queue of two systems used as an instruction prefetch queue for a currently executing task or an instruction prefetch queue of a task to be executed next, and the two systems of instruction prefetch queues are connected to each other. An instruction prefetch device comprising: means for switching, using a flag, whether the instruction prefetch queue is used as a system instruction prefetch queue or used as two independent system instruction prefetch queues.