JP2576378B2 - Failure simulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault simulation apparatus for a parallel processor, and more particularly to a test vector creation and fault simulation apparatus for a logic circuit.

[0002]

2. Description of the Related Art Conventionally, this kind of failure simulation is
For example, as described in Kenji Koji, Hiroshi Kawanishi and Shigehiro Funatsu, "Basics of Ultra LSICAD.", Pp.169-172, (Ohm), it is performed in the same way as in a single processor. . However, this method requires a large amount of memory on a computer in order to simulate all of the target failure definitions. If data overflows from real memory, the overflowing data may be expanded to virtual memory,
This reduces the computing power.

[0003] Therefore, Chappell, SG, Eimendorf, CH, an
d LD, Schmidt, ”LAMP: Logic Circuit Simulation,” Th
e Bell System Technical Journal, Vol.53, pp.1451-147
As described in 6, October 1974, in order to improve execution time efficiency, specific faults are excluded from detection and are reduced from data that are defined so that simulation data does not overflow from real memory. It is known that techniques have been used. In this method, since a specific fault is deleted as a non-detection target, the coverage of the simulation is not guaranteed. Therefore, in order to increase the coverage, a method of executing a fault simulation again from the beginning of the test vector for a fault that is not detected is used.

[0004]

In the above-described conventional fault simulation method, a simulation to be deleted is executed again from the beginning of the test vector for the fault to be deleted, and after the deleted simulation is completed. Otherwise, it cannot be executed, so that it takes time.

[0005]

According to the present invention, there is provided an apparatus for simulating a fault in a parallel processor.
Means for transferring a part of the failed circuit data to another inactive processor when the data of the failed circuit increases and a memory overflow occurs during execution of the failure simulation in one processor; The present invention is characterized in that it comprises means for deleting circuit data from internal data, and means for causing the other processor to execute a failure simulation based on the partial failure circuit data.

[0006]

FIG. 1 shows an embodiment of the present invention.
In this embodiment, the bus 2 is used in a parallel processor system.
Are shown, two processors 1 and 1 'connected via the.

When a failure simulation is performed in the processor 1, a failure simulator module 3 is loaded into the processor 1. The failure simulation module 3 includes a failure simulator core 4 for executing and controlling a failure simulation and internal data. The internal data includes one positive circuit data 10 and fault circuit data equal to the defined number of faults.

As the simulation progresses, if a fault propagates in the circuit, the data of each faulty circuit increases.
As a result, when the internal data 5 overflows from the real memory, the fault simulator core 4 determines a fault that consumes a large amount of memory among the fault circuit data as the fault circuit data 11 to be deleted. The failure simulation core 4 loads a new failure simulation module 3 'into the free processor 1'. The failure simulator core 4 'is the same as the failure simulator core 4. The failure simulator module 3 'includes a failure simulator core 4' and internal data 5 '.

The fault simulator core 4 receives the correct circuit data 10 and the delete target fault circuit data 11 via the correct circuit data extractor a and the delete target fault circuit data extractor b.
And the extracted data is transferred to the bus 2 by the data transfer means d.
To the fault simulator core 4 ′ through the interface, and deletes unnecessary fault circuit data 11 to be deleted by the fault circuit data deleting means c.

The fault simulator core 4 'converts the data transmitted via the bus 2 into the normal circuit data 10' and the fault circuit data 11 'via the normal circuit data expanding means e and the fault circuit data expanding means f into the internal data 5'. 'To expand. After this,
The simulation is subsequently executed on each processor.

FIG. 2 is a flowchart of the above embodiment. The simulator is started by starting the failure simulation (S1). First, after completion of the operation (S2) at each time, it is checked whether or not a memory overflow exists (S3). If no memory overflow has occurred, NO is selected and the operation at the next time (S2) is performed. ).

If a memory overflow has occurred, YES is selected, a fault simulator is activated on another processor (S4), and a fault to be deleted is determined to eliminate the memory overflow (S5). ,
The correct answer data 5 and the deletion target fault circuit data 11 are transferred to the startup fault simulator (S6, S7). After deleting the fault to be deleted (S8), the simulation is continuously executed. On the other hand, in processor 1 ',
The failure simulation is started by starting the failure simulator (S4) (S10). The failure simulator expands the received positive circuit data (S11) and expands the failed circuit data (S12), and executes a simulation.

[0013]

According to the present invention, the information which has been discarded at the time when the fault is not detected is continuously executed by another processor.
This has the effect of shortening the processing time.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart of one embodiment of FIG. 1;

[Explanation of symbols]

 1 Processor 1 'Processor 2 Bus 3 Fault Simulator Module 3' Fault Simulator Module 4 Fault Simulator Core 4 'Fault Simulator Core 5 Internal Data 5' Internal Data 10 Correct Answer Data 10 'Correct Answer Data 11 Deletion Target Fault Circuit Data 11' Fault Circuit data a Positive circuit data extraction means b Deletion target fault circuit data extraction means c Deletion target fault circuit data deletion means d Data transfer means e Correct answer data expansion means f Faulty circuit data expansion means

Claims (2)

(57) [Claims] In a fault simulation device for a parallel processor, when a fault overflow occurs in one of the processors and a memory overflow occurs due to an increase in the data of the faulty circuit, a part of the faulty circuit data is inactive. Means for forwarding to the processor of the
A failure simulation apparatus comprising: means for deleting the part of the failed circuit data from the internal data; and means for causing the other processor to execute a failure simulation based on the part of the failed circuit data. 2. The failure simulation apparatus according to claim 1, wherein each of said means is constituted by a program module that can be loaded into each of said processors.