JP2576271B2 - PGA structure - Google Patents
PGA structureInfo
- Publication number
- JP2576271B2 JP2576271B2 JP2198889A JP19888990A JP2576271B2 JP 2576271 B2 JP2576271 B2 JP 2576271B2 JP 2198889 A JP2198889 A JP 2198889A JP 19888990 A JP19888990 A JP 19888990A JP 2576271 B2 JP2576271 B2 JP 2576271B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- substrate
- cap
- pga
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子装置等に使用されるPGAの構造に関
し、特にセラミック基板を用いたPGAに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a PGA used for an electronic device or the like, and particularly to a PGA using a ceramic substrate.
入出力ピン付基板に半導体部品をフェイスアップもし
くはフェイスダウンで実装するPGAには第４図，第５図
に示す２種類の構造のものがある。FIGS. 4 and 5 show two types of PGAs in which semiconductor components are mounted face-up or face-down on a board with input / output pins.
第４図に示すPGAは、効率よく放熱するために下面に
設けた凹部25に半導体部品27をフェイスダウンで収容す
る基板21の上面にヒートシンク23を設け、基板21の下面
にキャップ24をシール材26にて設けたものである（例え
ば特開昭56−85842号）。22は入出力ピン、28はリード
である。In the PGA shown in FIG. 4, a heat sink 23 is provided on an upper surface of a substrate 21 for accommodating a semiconductor component 27 face down in a concave portion 25 provided on the lower surface for efficient heat radiation, and a cap 24 is provided on a lower surface of the substrate 21 with a sealing material. 26 (for example, JP-A-56-85842). 22 is an input / output pin and 28 is a lead.
第５図に示すPGAは基板21′の上面に設けた凹部25に
半導体部品27を収容し、キャップ24′を設け、基板21′
の下面に入出力ピン22を設けたものである。In the PGA shown in FIG. 5, a semiconductor component 27 is accommodated in a concave portion 25 provided on the upper surface of a substrate 21 ', a cap 24' is provided, and the substrate 21 '
Are provided with input / output pins 22 on the lower surface thereof.
第４図に示す従来のPGAは、基板21内の凹部25の開口
側に入出力ピン22を設け、前記凹部25を入出力ピン22側
からキャップ24にて閉塞しているため、キャップ24によ
り入出力ピン22の数に制限を受け、多くの入出力ピンを
設けようとした場合基板外形が大きくなってしまうとい
う欠点があった。また第５図に示すPGAは、ヒートシン
クを備えておらず、放熱に対して考慮されていない欠点
があった。In the conventional PGA shown in FIG. 4, the input / output pin 22 is provided on the opening side of the concave portion 25 in the substrate 21, and the concave portion 25 is closed by the cap 24 from the input / output pin 22 side. When the number of input / output pins 22 is limited and many input / output pins are provided, there is a disadvantage that the outer shape of the board becomes large. Further, the PGA shown in FIG. 5 does not have a heat sink, and has a drawback that heat radiation is not considered.
本発明のPGA構造は、下面に設けた凹部に半導体部品
をフェイスダウンで搭載する基板と、前記凹部を覆うよ
うに前記基板に固着されたキャップと、前記基板の下面
の前記キャップを除く部分に設けられた長い入出力ピン
および短い入出力ピンと、前記基板の下側に配置された
多層配線基板と、この多層配線基板の上面に設けられ前
記短い入出力ピンに半田付けされる導体回路と、前記多
層配線基板に設けられ前記長い入出力ピンを貫通させる
貫通穴と、前記多層配線基板の下面の前記キャップの下
側に対応する部分に設けられ前記導体回路と電気的に接
続された入出力ピンとを有している。The PGA structure of the present invention includes a substrate on which semiconductor components are mounted face-down in a concave portion provided on the lower surface, a cap fixed to the substrate so as to cover the concave portion, and a portion of the lower surface of the substrate other than the cap. Provided long input / output pins and short input / output pins, a multilayer wiring board disposed on the lower side of the board, and a conductor circuit provided on an upper surface of the multilayer wiring board and soldered to the short input / output pins, A through hole provided in the multilayer wiring board for penetrating the long input / output pin, and an input / output provided in a portion corresponding to a lower side of the cap on a lower surface of the multilayer wiring board and electrically connected to the conductor circuit; And a pin.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図〜第３図はそれぞれ本発明の一実施例を示す断
面図、PGA本体９の断面図および乗せ換え基板10の断面
図である。1 to 3 are a sectional view showing an embodiment of the present invention, a sectional view of a PGA main body 9 and a sectional view of a transfer board 10, respectively.
第２図に示すPGA本体９は、第４図に示すPGAと基本的
に同一であり、特徴とする点は短い入出力ピン2aと、長
い入出力ピン2bが設けてあることである。乗せ換え基板
10の多層配線基板16にはPGA本体９の長い入出力ピン2b
に対応する位置に入出力ピン2aの通る貫通穴14が設けて
あり、多層配線基板16の上面には、PGA本体９の短い入
出力ピン2bに対応する位置に導体回路15が設けてある。
導体回路15は、多層配線基板16の絶縁層12（例えばアル
ミナ等のセラミックス）にはさまれたタングステン等の
導体層11を介して下面のキャップ４に対応する位置に設
けられた入出力ピン17へと接続されている。The PGA body 9 shown in FIG. 2 is basically the same as the PGA shown in FIG. 4, and is characterized in that a short input / output pin 2a and a long input / output pin 2b are provided. Transfer board
10 multilayer wiring board 16 has long input / output pins 2b of PGA body 9
A through-hole 14 through which the input / output pin 2a passes is provided at a position corresponding to, and a conductor circuit 15 is provided on the upper surface of the multilayer wiring board 16 at a position corresponding to the short input / output pin 2b of the PGA body 9.
The conductor circuit 15 is provided with an input / output pin 17 provided at a position corresponding to the cap 4 on the lower surface via a conductor layer 11 such as tungsten sandwiched between insulating layers 12 (for example, ceramics such as alumina) of the multilayer wiring board 16. Connected to.
本実施例の、PGA本体９の乗せ換え基板10への実装方
法は、多層配線基板16の上面の導体回路15に、Sn/Pb（6
3/37wt％）等の予備半田13を設け、第１図に示すよう
に、多層配線基板16の貫通穴14にPGA本体９の入出力ピ
ン2bを通すように重ね合わせる。この状態では貫通穴14
に入出力ピン2bが通っているためセルファライメントの
効果があり、予備半田13と入出力ピン2aが位置ずれを起
こすことはない。そして加熱リフロー、例えば220℃加
熱を行い、冷却、洗浄を行うと、予備半田13は半田18に
変わり、実装が終了する。この実装方法では、PGA本体
９の長い入出力ピン2aは、乗せ換え基板10の貫通穴14を
貫通しているだけで固定されておらず、隙間によるがた
が発生することが考えられる。これを解決する手段とし
て貫通穴14の上面にメタライズ（例えばCr/Pd/Cu）を設
け、入出力ピン2aを半田付けする方法が考えられるが、
導体回路15上の予備半田13と同様に予備半田を設けると
貫通穴14をふさいでしまう。そこで、入出力ピン2aにリ
ング半田を通し、加熱リフローによる半田付けを行なえ
ばよい。In this embodiment, the mounting method of the PGA body 9 on the transfer board 10 is such that Sn / Pb (6
3/37 wt%), and superimposed such that the input / output pins 2b of the PGA body 9 pass through the through holes 14 of the multilayer wiring board 16 as shown in FIG. In this state, the through hole 14
Since the input / output pin 2b passes through the second solder, there is an effect of self-alignment, and the misalignment between the preliminary solder 13 and the input / output pin 2a does not occur. Then, when heating reflow, for example, heating at 220 ° C., and cooling and washing are performed, the spare solder 13 is changed to the solder 18 and the mounting is completed. In this mounting method, the long input / output pins 2a of the PGA main body 9 only penetrate the through-holes 14 of the transfer board 10 and are not fixed. As a means to solve this, a method of providing metallization (for example, Cr / Pd / Cu) on the upper surface of the through hole 14 and soldering the input / output pin 2a is considered.
If the preliminary solder is provided in the same manner as the preliminary solder 13 on the conductor circuit 15, the through hole 14 will be blocked. Therefore, a ring solder may be passed through the input / output pins 2a and soldering by heating reflow may be performed.
放熱手段としては、一つの手段として第１図に示すよ
うにヒートシンク３を取り付けているが、別の手段とし
て放熱モジュールを取り付けてもよい。As the heat dissipating means, the heat sink 3 is attached as one means as shown in FIG. 1, but a heat dissipating module may be attached as another means.
第２図に示すPGA本体９の入出力ピン2a,2bのピッチａ
は、1.0mm〜1.5mmと微細であり、第１図に示す入出力ピ
ン2b,17のピッチb,c,dは、2.0mm〜3.0mmである。Pitch a of input / output pins 2a and 2b of PGA body 9 shown in FIG.
Are as small as 1.0 mm to 1.5 mm, and the pitches b, c, d of the input / output pins 2b, 17 shown in FIG. 1 are 2.0 mm to 3.0 mm.
以上説明したように、本発明は、半導体部品をフェイ
スダウンで搭載した基板のPGA本体と多層配線基板に導
体回路と貫通穴を設けた乗せ換え基板を重ね合わせるこ
とにより、キャップの面積による入出力ピンの本数制限
を受けずPGA全面に多くの入出力ピンを設けることがで
きる効果があり、さらに本発明は、乗せ換え基板を用い
ることにより、入出力ピンのピッチを大きく展開し、容
易にプリント基板等に実装することができる効果があ
る。また、半導体部品の発生する熱をPGA本体の基板の
表面から放散できるので、放熱性のよい、高密度多ピン
化にすぐれたPGAが得られうという効果がある。As described above, according to the present invention, the input / output based on the area of the cap is achieved by overlapping the PGA body of the board on which the semiconductor components are mounted face-down with the transfer board provided with the conductor circuit and the through hole on the multilayer wiring board. There is an effect that many input / output pins can be provided on the entire surface of the PGA without being limited by the number of pins. Further, the present invention uses a transfer board to greatly expand the pitch of the input / output pins and easily print. There is an effect that it can be mounted on a substrate or the like. Further, since heat generated by the semiconductor component can be radiated from the surface of the substrate of the PGA main body, there is an effect that a PGA excellent in heat dissipation and excellent in high density and high pin count can be obtained.
第１図〜第３図はそれぞれ本発明の一実施例を示す断面
図、PGA本体９の断面図および乗せ換え基板10の断面
図、第４図（ａ）および（ｂ）はそれぞれ従来のPGA構
造を示す断面図と斜視図、第５図は従来の他のPGA構造
を示す断面図である。 1,21,21′……基板、2a,2b,17,22……入出力ピン、3,23
……ヒートシンク、4,24,24′……キャップ、2,25……
凹部、6,26……シール材、7,27……半導体部品、8,28…
…リード、９……PGA、10……乗せ換え基板、11……導
体層、12……絶縁層、13……予備半田、14……貫通穴、
15……導体回路、16……多層配線基板、18……半田。1 to 3 are cross-sectional views showing an embodiment of the present invention, a cross-sectional view of a PGA main body 9 and a cross-sectional view of a transfer board 10, respectively. FIGS. FIG. 5 is a sectional view and a perspective view showing the structure, and FIG. 5 is a sectional view showing another conventional PGA structure. 1,21,21 '... substrate, 2a, 2b, 17,22 ... I / O pins, 3,23
…… heat sink, 4,24,24 ′ …… cap, 2,25 ……
Recess, 6,26 …… Seal material, 7,27 …… Semiconductor component, 8,28…
... Lead, 9 ... PGA, 10 ... Replacement board, 11 ... Conductor layer, 12 ... Insulating layer, 13 ... Pre-soldering, 14 ... Through hole,
15 ... conductor circuit, 16 ... multilayer wiring board, 18 ... solder.
Claims (3)
ダウンで搭載する基板と、前記凹部を覆うように前記基
板に固着されたキャップと、前記基板の下面の前記キャ
ップを除く部分に設けられた長い入出力ピンおよび短い
入出力ピンと、前記基板の下側に配置された多層配線基
板と、この多層配線基板の上面に設けられ前記短い入出
力ピンに半田付けされる導体回路と、前記多層配線基板
に設けられ前記長い入出力ピンを貫通させる貫通穴と、
前記多層配線基板の下面の前記キャップの下側に対応す
る部分に設けられ前記導体回路と電気的に接続された入
出力ピンとを含むことを特徴とするPGA構造。1. A substrate on which a semiconductor component is mounted face down in a concave portion provided on a lower surface, a cap fixed to the substrate so as to cover the concave portion, and a cap provided on a lower surface of the substrate except for the cap. A long I / O pin and a short I / O pin, a multilayer wiring board disposed below the substrate, a conductor circuit provided on an upper surface of the multilayer wiring board and soldered to the short I / O pin, A through hole provided in the wiring board and penetrating the long input / output pin,
A PGA structure comprising: an input / output pin provided on a lower surface of the multilayer wiring board at a portion corresponding to a lower side of the cap and electrically connected to the conductor circuit.
ダウンで搭載する基板と、前記凹部を覆うように前記基
板に固着されたキャップと、前記基板の下面の前記キャ
ップを除く部分に設けられた長い入出力ピンおよび短い
入出力ピンとを含むことを特徴とする請求項１記載のPG
A構造。2. A substrate on which a semiconductor component is mounted face-down in a concave portion provided on a lower surface, a cap fixed to the substrate so as to cover the concave portion, and a cap provided on the lower surface of the substrate except for the cap. 2. The PG according to claim 1, further comprising a long input / output pin and a short input / output pin.
A structure.
求項１または２記載のPGA構造。3. The PGA structure according to claim 1, wherein a cooling member is mounted on the upper surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2198889A JP2576271B2 (en) | 1990-07-26 | 1990-07-26 | PGA structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2198889A JP2576271B2 (en) | 1990-07-26 | 1990-07-26 | PGA structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0485863A JPH0485863A (en) | 1992-03-18 |
| JP2576271B2 true JP2576271B2 (en) | 1997-01-29 |
Family
ID=16398626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2198889A Expired - Lifetime JP2576271B2 (en) | 1990-07-26 | 1990-07-26 | PGA structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2576271B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6052634U (en) * | 1983-09-19 | 1985-04-13 | 日本電気株式会社 | semiconductor equipment |
| JPS6066828A (en) * | 1983-09-22 | 1985-04-17 | Nec Corp | Semiconductor integrated circuit package |
| JPH02181958A (en) * | 1989-01-09 | 1990-07-16 | Nec Corp | Semiconductor device |
-
1990
- 1990-07-26 JP JP2198889A patent/JP2576271B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0485863A (en) | 1992-03-18 |
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