JPS6066828A - Semiconductor integrated circuit package - Google Patents

Semiconductor integrated circuit package

Info

Publication number
JPS6066828A
JPS6066828A JP58175435A JP17543583A JPS6066828A JP S6066828 A JPS6066828 A JP S6066828A JP 58175435 A JP58175435 A JP 58175435A JP 17543583 A JP17543583 A JP 17543583A JP S6066828 A JPS6066828 A JP S6066828A
Authority
JP
Japan
Prior art keywords
integrated circuit
external lead
semiconductor integrated
pins
tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58175435A
Other languages
Japanese (ja)
Inventor
Takahisa Nishimura
西村　孝久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58175435A priority Critical patent/JPS6066828A/en
Publication of JPS6066828A publication Critical patent/JPS6066828A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H01L2224/78314—Shape
    • H01L2224/78317—Shape of other portions
    • H01L2224/78318—Shape of other portions inside the capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the workability in the assembling step of an IC by shortening inside pins as compared with outside pins of external lead pins of a plurality of rows. CONSTITUTION:Even if the angle of the end of a bonding tool is not particularly reduced since inside pins 6b are shorter than outside pins 6a, wirings 5 can be performed without contacting the tool with the outside pins. Accordingly, a decrease in the bonding workability due to the reduction in the thickness of the end of the tool can be avoided, thereby preventing the increase in the size of a package 1.

Description

【発明の詳細な説明】 本発明は、半導体集積回路容器、特に、外部リードビン
を４１する半導体毛積回路容器の構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit container, and more particularly to the structure of a semiconductor integrated circuit container having an external lead bin.

近年の集積回路の設計並びに製造技術の進歩により、そ
の↓ｉｓ　ｈ、度は向上の一途を辿っている。集積度の
向上は、特にランダム論理と呼ばれる集１’＋Ｔ回路に
とり−Ｃは、集積回路チップの外部と没パ穿１−ベき信
号端子数の増加全もたらしている。このｔめ一、集積回
路容器も、従来の外部リードビン百−１列に配列する構
造では実装面積が大きくなり過ぎるので、外部リードビ
ンを・濃数列に配列した１１゛ダ造のものが使用される
ようになってきた。この’ｉｉｌ！ｉ果外部リードビン
がチップへ近接しておかｆしるよりになシ・集積回路チ
ップと実績回路容器とを咋絖する場合、この接続に用い
る接続工具がりｔｈｒＩｌｕ　−ドビンと接触するとい
う問題が生じている。Due to recent advances in integrated circuit design and manufacturing technology, the degree of ↓ish has continued to improve. The increase in the degree of integration, especially for integrated 1'+T circuits called random logic, has resulted in an increase in the number of signal terminals external to the integrated circuit chip and uncircumcised. First, since the conventional structure of arranging external lead bins in 100-1 rows of integrated circuit containers would require too large a mounting area, an 11-da structure with external lead bins arranged in 100-1 rows was used. It's starting to look like this. This 'iil! It is better to keep the external lead bin close to the chip.When connecting the integrated circuit chip and the circuit container, a problem arises in that the connecting tool used for this connection comes into contact with the lead bin. ing.

すなわち、ボ】図は従来のプラグイン型半導イベ集積回
路容器に集、Ｘ＊回路チップヶ固着し、ワイヤボンディ
ングを行う状態全示す断１ｊ図である。、第１図におい
て、容器本体１の１且偵回路チッグ収、階部に固着され
た集積回路チップ゛３のボンデ、イング覗極４と、容器
本体１のポンティングバッド２との聞分、ボンディング
用工具１．１．　ＶＣより金λ・１４泗１ｊ線５の接続
全行う場合、金属、Ｉ（ＩＩ線５ヶ急峻に折り曲げない
ように、ボンディング用工具］１には七の作！ｉｖＪ方
向に対しである角度をもった導入部１２が設けられてい
る０しかして、この工具１１により金属線ｂメ５の接続
を行う場合、容器本体１のチップ収納部両側の平面部の
それぞれに２列に眩けられている外部リードビン６のう
ち、内側のリードビンにボンディング用工具１１が接触
しないようにするためＫｉ、−ｊ：、内１ｉｔｏの外部
リードビンから容器本体】のポンディングパッド２まで
の距離を広げるか、葦たは、工具】１の先端の角度？小
さくする必要がある。しかし、前者の場合゛は、結果と
して容器の寸法が大きくなり、後者の場合は、作業中に
金属細線が祈すし易く、作業性が悪くなるという欠点が
生じる。That is, FIG. 1J is a cross-sectional view showing the state in which X* circuit chips are assembled in a conventional plug-in type semiconductor integrated circuit container, fixed, and wire bonded. In FIG. 1, the distance between the bonding and ing sight pole 4 of the integrated circuit chip 3 fixed to the bottom of the container body 1 and the ponting pad 2 of the container body 1; Bonding tools 1.1. When connecting all of the gold λ, 14, However, when connecting the metal wire b 5 with this tool 11, the introduction part 12 is provided with two rows on each of the flat parts on both sides of the chip storage part of the container body 1. In order to prevent the bonding tool 11 from coming into contact with the inner lead bin of the external lead bins 6, either increase the distance from the external lead bin of Ki, -j:, to the bonding pad 2 of the container body, or Or the angle of the tip of tool 1? It is necessary to reduce the angle. However, in the former case, the dimensions of the container will become larger, and in the latter case, the thin metal wire will easily break during work, making the work difficult. The disadvantage is that the sex becomes worse.

本発明の目的は、このような従来の半導体集積回路容器
の欠点を改善した、半導体集積回路の組立工程での作業
性を向上できる半導体集積回路容器全提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit container that overcomes the drawbacks of the conventional semiconductor integrated circuit container and can improve workability in the assembly process of semiconductor integrated circuits.

本発明の容器は、集積回路チップ収納部全問にはさむ両
側の平面部のそれぞれに外部リードビンが複叙列に配列
されており、かつ、前記外部１７−ドビンのうち、内側
の外部リードビンの長さが外側の外部リードビンの長さ
より短くさね、てＩハる偶成を有する。In the container of the present invention, external lead bins are arranged in double rows on each of the flat parts on both sides sandwiched between all the integrated circuit chip storage parts, and the length of the inner external lead bin among the external 17 bins is The length is shorter than the length of the outer external lead bin, and has a concatenated shape.

つぎに本発明を笑施例によシ説明する。Next, the present invention will be explained using examples.

第２図は本発明の一実施例を用いた半導体集積回路の断
面図である。第２図に赴いて、集積１ｍ回路ップ３が収
納され、金属側−４５により、チップ３の電極と容器本
体１のボンティングバッドとの間を接続後、蓋７によシ
蓋をされ／ζ果集積路チップ収納部ケ間にはさむ両画の
平面部のそれぞれＶｒ−は、外部リードビン６ａと６ｂ
が２列に設けられている。しかしで、内側の外部リード
ビン６ｂの長さは、外側の外部リードビン６ａの長さよ
り短くなっている。したがって、４３図に示し、たよう
に、ボンディング工具１１により金＠　；ｉ、ｌ！Ｉ　
＋９ｉｉ　５の斑続を行う場合、内側の外部リードビン
の長さがｈｊくなっているため、ボンディング用工具１
１の先端の角度を・特に小さくしなくとも、ボンディン
グ用工具が外部リードビンに接触することはなくなり、
よって、ボンディング用工具の先・副部の７７１１ｕｇ
全小さくすることによる作業性の低下は回避される。ま
た、多数の外部リードビンを備えだ半導体集積回路全容
器寸法の増大なしＶこ作業性よく製造できる効果が得ら
れる。FIG. 2 is a sectional view of a semiconductor integrated circuit using an embodiment of the present invention. 2, the integrated 1 m circuit chip 3 is housed, and after connecting the electrode of the chip 3 and the bonding pad of the container body 1 through the metal side 45, the lid 7 is closed. /ζRespective Vr- of the plane part of both images sandwiched between the chip storage part and the external lead bin 6a and 6b
are arranged in two rows. However, the length of the inner external lead bin 6b is shorter than the length of the outer external lead bin 6a. Therefore, as shown in FIG. 43, the bonding tool 11 produces gold@;i,l! I
+9ii When performing uneven bonding of 5, the length of the inner external lead bin is hj, so the bonding tool 1
Even without making the angle of the tip of 1 particularly small, the bonding tool will no longer come into contact with the external lead bin.
Therefore, 7711ug of the tip/sub part of the bonding tool
Decrease in workability due to overall miniaturization is avoided. In addition, it is possible to manufacture semiconductor integrated circuits with good workability without increasing the size of the entire container including a large number of external lead bins.

【図面の簡単な説明】[Brief explanation of drawings]

？Ｊ！Ｊ１図は従来の半導体集積回路容器に集積回路集
積回路の断面図である。 １・・・・・・容器本体、２・・・・・・ポンディング
パッド。 ３・・・・・・集積回路チップ、４・・・・・・ボンデ
ィングｔｉ！　４’ｋ、５・・・・・・金属＃ｆｌｌ線
、６・・・・・・外部リードビン、６ａ・・・・・・外
側の外部リードビン、６ｂ・・団・内側の外部リードビ
ン、７・・・・・・蓋、１１・旧・・ボンディング用工
具、１２・・・・・・金属細線導入部。 代理人　弁理士　内　原　訝? J! Figure J1 is a sectional view of a conventional integrated circuit integrated circuit in a semiconductor integrated circuit container. 1... Container body, 2... Ponding pad. 3... Integrated circuit chip, 4... Bonding ti! 4'k, 5...Metal #fll wire, 6...External lead bin, 6a...Outer external lead bin, 6b...Group, inner external lead bin, 7. ...Lid, 11. Old bonding tool, 12.. Thin metal wire introduction part. Agent Patent Attorney Uchihara Sho

Claims (1)

【特許請求の範囲】[Claims] 集Ａ’ｌｔ回路チップ収納部を間にはさむ両側の平面部
のそれぞれに外部リードピンが複数列に配列されている
半導体集積回路容器において、前記外部リードピンのう
ち内側に配列された外部リードピンの長さを外側に配列
きれた外部リードビンの長さより短かくしたことを特徴
とする半導体集積回路容器。In a semiconductor integrated circuit container in which external lead pins are arranged in a plurality of rows on each of the flat parts on both sides with a circuit chip storage section in between, the length of the external lead pins arranged on the inside among the external lead pins. A semiconductor integrated circuit container characterized in that the length of the external lead bin is shorter than the length of the external lead bin arranged on the outside.
JP58175435A 1983-09-22 1983-09-22 Semiconductor integrated circuit package Pending JPS6066828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58175435A JPS6066828A (en) 1983-09-22 1983-09-22 Semiconductor integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58175435A JPS6066828A (en) 1983-09-22 1983-09-22 Semiconductor integrated circuit package

Publications (1)

Publication Number Publication Date
JPS6066828A true JPS6066828A (en) 1985-04-17

Family

ID=15996042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58175435A Pending JPS6066828A (en) 1983-09-22 1983-09-22 Semiconductor integrated circuit package

Country Status (1)

Country Link
JP (1) JPS6066828A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0485863A (en) * 1990-07-26 1992-03-18 Nec Corp Pga structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0485863A (en) * 1990-07-26 1992-03-18 Nec Corp Pga structure

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