JP2575608B2 - Flash photographing system and flash device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a single-light or multiple-light electronic flash light emitting device (hereinafter referred to as a flash device) connected directly or indirectly to a camera, and emitting light in synchronization with opening of a shutter of the camera. And an apparatus for performing flash photography.

2. Description of the Related Art It is well known that whether or not a flash device emits light is determined by the state of charge of a main capacitor. With this method, there is an effect that when flash photography is performed, the amount of light emission is insufficient and underexposure does not occur, thereby preventing malfunction.

By the way, when performing multiple flash photography using a plurality of such flash devices, if one flash device is fully charged and the other flash device is not charged, only one flash device emits light and the other flash device emits light. The flash device does not emit light, and there is a problem that the amount of exposure is insufficient, or that flash photography of intended tasting cannot be performed.

Japanese Utility Model Publication No. 56-134025 and its corresponding U.S. Patent No. 4,333,719
The signal is a connector for multi-flash photography, and a charge completion signal from a plurality of flash devices is detected by an AND circuit. Is sent to the camera. However, in a flash system using this connector, since each flash device does not know the charging status of the other flash devices, if the flash device itself is in a fully charged state, it emits light in response to a flash command signal from the camera. At that time, since the camera has not received the completion signal, the camera does not switch to the flash photographing mode and operates in the natural light photographing mode.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a flash system which does not cause a malfunction in which each flash device is controlled in accordance with the state of charge of all flash devices in a multi-flash photography.

Embodiment FIG. 1 is a block diagram showing the overall configuration of a flash photography system to which the present invention is applied. Note that in this figure, the following circuit diagrams, and block diagrams, a thick line indicates a plurality of signal lines, and a thin line indicates one signal line. (V) is a lens interchangeable single-lens reflex camera main body, which is provided with connectors (CN9) and (CN3) for electrically connecting to a flash device. Connector (CN9)
Is provided on a hot shoe (not shown) above the camera, and when an electronic flash light emitting device (hereinafter referred to as a flash device) is mounted on the camera via the hot shoe, it is directly electrically connected to a circuit of the flash device. . Connector (CN3)
Is provided at the bottom of the camera and is electrically connected to a flash device via a flash controller (IV) described later,
The flash device is not electrically connected directly to the camera via the connector (CN3). Further, a connector (CN1) is provided on the camera body (V). The connector (CN1) is provided at an attachment position of an interchangeable lens such as a seat plate of a lens mount, and the interchangeable lens (VI) is provided. When mounted on the camera, it is connected to the connector (CN2) of the interchangeable lens (VI), and various data from the lens circuit (LEC) is taken into the camera body (V).

(IV) is a flash controller for controlling a flash device connected thereto, which is electrically connected to a connector (CN3) at the bottom of the camera body via a connector (CN4). The flash controller (IV) is further provided with connectors (CN5) and (CN7).
5) has four electrical terminals, and the connector (CN7) has two electrical terminals. The flash device connected to the connector (CN5) exchanges signals with the flash controller (IV) for data transfer and emission control, and the flash device connected to the connector (CN7) Only transmits a light emission start signal from the flash controller (IV).

(I) is a two-light type flash device. In the example of FIG. 1, a connector (CN) is connected to a flash controller (IV).
5), connected via (CN6). (II) is a one-lamp type flash device, which has a connector (CN9) and a connector (CN10) provided on the hot shoe of the camera body (V).
Are electrically connected via (III) is a one-lamp flash device having the same configuration as the flash device (II). In this example, the flash device is electrically connected to the flash controller (IV) via connectors (CN7) and (CN8).

FIG. 1 shows a camera body (V), a flash controller (IV), and flash devices (I), (II), and (III).
This is an example of how to connect the flash devices (I) and (II) with each other.
The flash device (III) is not mounted, the flash device (I) or (II) is mounted only at the position of the hot shoe, the flash controller (IV) is mounted on the camera body (V), and the connector (CN5 )
The flash controller (I) or (II) is mounted only at the position of (1), or the flash device (I) or (II) is mounted at the position of the hot shoe and mounted on the camera body (V). The flash device can be left unattached to (IV). Furthermore, a flash controller (IV) is attached, and the flash device (I) or (I
I) may be simply attached, and furthermore, only the flash controller (IV) may be attached to the camera body (V), and the camera may be operated without attaching the flash device anywhere. When only the flash controller (IV) is attached to the camera body (V), flash photography is not performed, and steady light photography is performed. In addition, a general-purpose flash device or a non-dedicated flash device that does not have the functions required for the system of the present invention is mounted at the position of the hot shoe of the camera body (V) and the connector (CN5) of the flash controller (IV). In this case, the flash photography according to the present invention is not performed, and the attached general-purpose or non-dedicated flash device only emits light. The flash photography according to the present invention is performed regardless of whether the flash device is mounted at the position of the connector (CN7) of the flash controller (IV), a general purpose device or a non-dedicated type.

Next, the inside of the camera body (V) will be described. (BA1) is a power supply battery, and (MS1) is a main switch. (S1) is a photometric switch that is closed at the first step of pressing a release button (not shown), (S2) is a release switch that is closed at the second step of pressing a release button (not shown), The closing signal of the photometric switch (S1) is input to the interrupt terminal (it) and input terminal (i1) of the microcomputer (hereinafter referred to as microcomputer) (MC1), and the closing signal of the release switch (S2) is applied to the microcomputer (MC1). ) Input to the input terminal (i2). (S
The reset switch 4) is opened when the exposure control operation is completed, and is closed when the charging of an exposure control mechanism (not shown) such as a shutter mechanism and an aperture mechanism is completed. The signal is a microcomputer (MC
1) Input terminal (i3) ni input. (D0) is a circuit that outputs data according to set values such as an exposure control mode film sensitivity, an exposure time, and an aperture value, that is, setting data,
The signal of the setting data is input to the input terminal (IP1) of the microcomputer (MC1). The setting of the film sensitivity value may be performed in such a manner that the film sensitivity data marked on a film container (not shown) is automatically read and set as the setting data instead of the manual setting. (LM) is a photometric circuit, and the output of the photometric circuit (LM) is the AD of the microcomputer (MC1).
The analog input terminal (AN1) for conversion is input, and the output of a reference voltage source (not shown) provided in the photometric circuit (LM) is the reference voltage input terminal for analog-to-digital conversion (VR1) of the microcomputer (MC1).
Has been entered.

(AF) is an automatic focus adjustment circuit that detects a focus adjustment state of the photographing lens and drives the photographing lens to a focus position. This automatic focus adjustment circuit (AF)
The operation is performed according to the command transmitted from 1) through the data bus (DB), and the shift direction and the shift amount of the subject image formed by the photographing lens from the expected focal plane are detected. Then, based on the detected displacement amount data and the data from the interchangeable lens (VI), the moving amount of the photographing lens (actually, the moving amount of the focusing lens system of the photographing lens that moves for focus adjustment) ) Is calculated, the lens is moved by the amount of movement, and the focus adjustment state of the photographing lens is displayed.
(RL) is a release circuit for starting the operation of the exposure control mechanism, and is set to “H” from the terminal (O2) of the microcomputer (MC1).
ihgh "signal. (DP) is a display circuit, exposure control value (expected aperture value to be controlled, exposure time value, etc.), exposure control mode, film sensitivity, flash device status, etc. This display circuit (DP) performs display based on data from the output terminal (OP2) of the microcomputer (MC1). (ECC) is a circuit for exposure control, and is displayed from the output terminal (OP1). The transistor (BT1) is a power supply transistor and the inverter (IN1) is turned on when the terminal (O1) of the microcomputer (MC1) becomes "High" based on the data of the exposure time and the number of stops. , The transistor (BT1) is rendered conductive, and power is supplied via the power supply line (+ V).
From this line (+ V), the circuits (LM), (AF), (EC
Power is supplied to (C), (RL), (FST) and the lens circuit (LEC).

The switch (Sx) is a synchro switch that is closed when the traveling of the shutter first curtain is completed. It is transmitted to the flash device (I). (FST) is a light emission amount control circuit for controlling the light emission amount of the flash device, and a specific example thereof is shown in FIG. (IOC) is an input / output controller that controls the transmission and reception of signals between the camera body (V) and the interchangeable lens (VI), the flash device (II), and the flash controller (IV). It is shown in

The terminal (CKO) of the microcomputer (MC1) outputs a clock pulse from inside the microcomputer, and this pulse (φ1) is used for the circuit for automatic focus adjustment (AF), the circuit for setting data output (DO),
The exposure control circuit (ECC), the display circuit (DP), and the release circuit (RL) are supplied as their reference clocks. A terminal (ANO) of the microcomputer (MC1) outputs a signal obtained by DA conversion of the film sensitivity for controlling the light emission amount of the flash device. Terminals (SCK), (SOU), and (SIN) are serial input / output terminals for data. When a serial input / output command is issued, eight clock pulses are output from the terminal (SCK). In synchronization with the rising edge of this clock pulse, data is output bit by bit from the input / output register in the microcomputer (MC1) to the terminal (SOU), and synchronized with the falling edge of the clock pulse from the terminal (SCK). SIN) is sequentially taken into the input / output register. (O3) is “High” when exchanging data with the interchangeable lens (VI)
The terminal (O4) is a terminal that becomes “High” when data is exchanged with one or both of the flash device and the flash controller, and the terminal (O5) is a signal that indicates the operation state of the camera to the flash device and the flash controller. A terminal for transmitting data from one or both of the flash device and the flash controller to the camera body during a predetermined period T1 (for example, 90 μsec).
Interval) When a “High” pulse is output and data is output from the camera body to one or both of the flash device and the flash controller during a predetermined period T2 (for example,
The pulse of “High” is output (for 150 μsec), and when the camera body starts the exposure control operation, the pulse of “High” is output for a predetermined period T3 (for example, for 210 μsec). The terminal (O6) is a terminal that becomes “High” when transferring one or both of data from the camera body to the flash device and the flash controller.

(LEC) is a circuit provided in the interchangeable lens (VI) and is supplied with power from a power supply line (+ V) of the camera body.
Then, when the terminal (O3) of the microcomputer (MC1) becomes “High”, the line (L1) becomes “High” and the circuit in the lens enters an operating state. Then, based on the clock pulse sent from the line (L2), the data fixedly stored in the in-lens circuit (LEC) is sequentially output from the line (L3) in series. The fixedly stored data includes an open aperture value,
Maximum aperture value, focal length, shooting distance, various data for automatic focus adjustment, check (whether or not an interchangeable lens compatible with the system of this embodiment is mounted, and if such an interchangeable lens is Data for confirming whether or not the camera is mounted).

(1) is a signal line to which the closing signal of the synchro switch (Sx) is transmitted as described above. (L2), when data is exchanged between the camera body and one or both of the flash controller and the flash device, serial data from one or both of the flash device and the flash controller and serial data from the camera body are transmitted. Function as a bidirectional data bus. When the flash device emits light, a "Low" signal is output from the flash device for a fixed time (a time longer than the time required for full light emission of the flash device, for example, 2.5 msec). Is output, and then a "Low" signal is output for a certain period of time (for example, 5.5 msec) required for the two lamps to emit all light in turn. When the flash device is in a charging completed state, a signal of "High" is output when the flash device is in a charging completed state, and a signal of "Low" is output when the flash device is not in a charging completed state except during data transmission and emission. Note that “Low”, “H”
The igh "and" Low "signals serve as signals for controlling the amount of light emission, as will be described later. A line (l3) is a terminal (SCK ) Is output from the camera body, and a signal indicating the operation state of the camera body is output from the terminal (O5) from the line (l3). A light emission stop signal is output from the control circuit (FST).

Next, the inside of the flash device (I) will be described. (BA
3) is a power supply battery, and (MS3) is a main switch. (FL
C1) is a control circuit, which has functions such as data transmission / reception, display calculation, light emission control, etc. The specific internal structure is shown in FIGS. 9, 10, 11, 12, and 12. Fig. 13, Fig. 14
This will be described later with reference to the drawings. (FDP1) is a display of a light emission mode (parent / child light emission, first light emission or post light emission in sequential light emission, simultaneous light emission, single light emission), display of whether or not a bounce state, and aperture based on data sent from the camera body. Value, film sensitivity, focal length display, display of the set irradiation angle when the irradiation angle of the flash device is variable, and based on the aperture value and film sensitivity data and light emission amount data sent from the camera body, In the automatic light control mode, the interlocking range (shooting distance range in which automatic light control is possible) is set. indicate. (CHC1) is a transistor (BT2) and a booster (DD) according to signals from the charge completion detection circuit (CHD1) and (CHD2).
This is a step-up control circuit that controls the operation of D1). The booster circuit (DD1) operates when the transistor (BT2) is turned on to boost the voltage of the power supply (BA3) to a required voltage (for example, 300V),
This output is connected to a capacitor (C
In 1), the capacitor (C2) is charged through the diode (D2). Then, the charge completion detection circuits (CHD1), (CH
D2) outputs a "High" signal (hereinafter, this signal is referred to as a complete signal) when the charging voltage of the capacitors (C1) and (C2) is charged to a voltage that can compensate for the maximum light emission amount of the flash device. The boost control circuit (CHC1) is connected to both detection circuits (CH
When the charge completion signal is output from D1) and (CHD2), the transistor (BT2) is deactivated and the operation of the booster circuit (DD1) is stopped. (BT2) is turned on to operate the booster circuit (DD1).

(FLO1) and (FLO2) are light-emitting units, respectively, and signals (ST1), (SP1), and (ST1) from the control circuit (FLC1).
2) and (SP2) control light emission. The light emitting unit (FLO2) has a variable irradiation direction. When only the flash device (I) is connected to the camera body (V) directly or via the flash controller (IV) as the flash device, if the light emitting unit (FLO2) faces the front ( This light emitting unit (FLO2)
If only the light-emitting part (FLO2) faces in a direction other than the front (hereinafter referred to as bounce state), the light-emitting part (FLO2) first emits about 2/3 of the proper exposure, and then emits light Part (F
LO1) emits light only about 1/3 of the proper exposure (hereinafter, such a light emission mode is referred to as a parent-child light emission mode). On the other hand, as shown in FIG. 1, when two or more flash units including the flash unit (I) are electrically connected to the camera body (V), the light emitting unit (FLO2) is placed in front. In both the light state and the bounce state, only the light emitting portion (FLO2) emits light, and (FLO1) does not emit light. Light emitting unit (FLO1), (FL
O2) starts emitting light when the terminals (ST1) and (ST2) become “High”. Since the capacity of the capacitor (C1) is much smaller than the capacity of the capacitor (C2), the maximum light emission amount of the light emitting unit (FLO1) is
It is much smaller than the maximum light emission of 2).
Therefore, the maximum light emission amount of the light emitting unit (FLO2) is, for example, 40 as a guide number, while the maximum light emission amount of (FLO1) is, for example, 8 as a guide number. Further, the light emitting unit (FLO2) has a variable irradiation angle, while the light emitting unit (FLO1) has a fixed irradiation angle. Terminals (SP1) and (SP2) are terminals for stopping light emission, and terminals (SP
When the “High” signal is output from 1), the light emitting unit (FLO1) stops emitting light, and when the “Hihg” signal is output from the terminal (SP2), the light emitting unit (FLO2) stops emitting light. .

Next, the flash device (II) will be described. (BA
5) is a power supply battery, and (MS5) is a main switch. (FL
C3) is the control circuit (FLC) of the flash unit (I)
A control circuit that performs the same function as 1), sends display data to the display unit (FDP3), and for the light-emitting unit (FLO4), emits a start signal to the terminal (ST4) and emits light from the terminal (SP4) Outputs stop signal. This control circuit (FLC
3), a specific example of which will be described later based on FIGS. 15, 16, and 17. The boost control circuit (CHC3) responds to the charge completion signal from the detection circuit (CHD4) by using the transistor (BT
4) Control the operation and non-operation of the booster circuit (DD3). The light emitting unit (FLO4) is switched between a front light state and a bounce state, and the irradiation angle is also variable. Flash device (II
I) has the same configuration as the flash device (II).

Next, the flash controller (IV) will be described. (BA2) is a power supply battery, and (MS2) is a main switch. (CNC) is a processing circuit which reads data from the flash units (I) and (II) based on a clock pulse from the camera body (V) to determine the mounted state of the flash unit and the internal state of the flash unit. The light emission mode is determined, the light emission mode is determined, and a light emission mode signal is sent to the flash device based on a clock pulse from the camera. Then, based on the clock pulse from the camera body, a signal indicating the light emission mode and the state of the flash device is sent to the camera. Further, it is determined whether or not the flash device (III) should emit light according to the result of the determination of the light emission mode,
To emit light (sequential light emission mode), a light emission start signal is output to the terminal (l21) of the two flash devices after light emission. A specific example of this processing circuit (CNC) is shown in FIG.

Next, light emission modes by various combinations will be described. If only the flash device (I) is directly connected to the camera body via the hot shoe or via the flash controller (IV) and the light emitting unit (FLO2) is in the front light state, the light emitting unit (FLO2) Only in the single light emission mode in which only the light is emitted, and the interlocking range is displayed based on the maximum light emission amount of the light emitting unit (FLO2). If the flash unit (FLO2) is in a bounce state, the flash unit (FLO2) emits 2/3 of the proper exposure, and then the flash unit (FLO1) emits 1/3 of the proper exposure. The interlocking range is displayed based on the maximum light emission amount of the light emitting unit (FLO1). Flash device (II)
When only the camera body (V) is electrically connected to the camera body (V) via a hot shoe or a flash controller, the light emitting section (FLO4) emits light until proper exposure is performed regardless of whether the light emitting section (FLO4) is in a front light state or a bounce state. It becomes a single light emission mode. In this case, if the light emitting unit (FLO4) is in the bounce state, the interlocking range is not displayed. If the light emitting unit (FLO4) is in the front light state, the interlocking range based on the maximum light emission amount of the light emitting unit (FLO4) is displayed.

Next, a case where a flash device is mounted on each of the hot shoe and the flash controller will be described. At this time, if one or both flash units are of the type (I), the light emitting unit (FLO1) does not emit light even if the light emitting unit (FLO2) is in the bounce state or the front light state, and (FLO2)
Only emits light. When the flash controller (IV) selects the simultaneous mode, the two flash devices emit light at the same time and stop emitting light at the same time when the combined light emission amount reaches the appropriate exposure. In this case, the interlocking range is displayed based on the maximum light emission amount of each light emitting unit,
If the light emitting unit is in the bounce state, no display is made. When the flash controller (IV) is sequentially selecting the flash mode, the flash device mounted on the flash controller (IV) first emits only 2/3 of the proper exposure, and then the hot flash of the camera body (V). The flash device mounted on the shoe emits light for only 1/3 of the proper exposure. The interlocking range at this time is not displayed in the flash device that emits light first, and the interlocking range based on the maximum light emission amount of the flash device is displayed in the flash device that emits light later.

As shown in the figure, when the flash device is mounted on each of the hot shoe and the flash controller, and the flash device is mounted on the connector (CN7) of the flash controller, the light emission mode is as follows. When the flash controller (IV) selects the simultaneous mode, no emission start signal is output from the terminal (l21), and the flash device (III) does not emit light. If the flash controller (IV) sequentially selects the flash mode, after the two flash units (II) and (I) sequentially emit light, a flash start signal is output from the terminal (l21) and the flash unit (III) Emits light. Flash device (II
Since only the connection of the ground line (l4) and transmission of the light emission start signal are performed on I), the signal from the light emission control circuit (FST) on the camera side is not transmitted, and the light emission amount set manually is set. Or full light emission in the automatic light control mode. This flash device (II
In the case of I), since only the light emission start signal is input, it is not necessary to use a dedicated flash device, and a general-purpose flash device may be used. This third flash unit (III)
If, for example, only the background is illuminated,
Even if the two lamps emit light so as to continuously illuminate the main subject, an unnatural shadow caused by the main subject on the background can be removed. The third flash unit (III) emits light after proper exposure is achieved by the first and second flash units (I) and (II), and the amount of light emission is controlled by a camera. Therefore, it is not desirable to irradiate the main subject, and light emission that covers unnaturalness of lighting may be performed.

Next, based on FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG.
The operation of the entire system of FIG. 1 will be described. Figure 2 shows the first
4 is a flowchart for explaining the operation of the microcomputer (MC1) in FIG. Hereinafter, description will be made focusing on this flowchart. When the main switch (MS1) of the camera body (V) is closed, power supply to the microcomputer (MC1) starts, and the microcomputer (MC1) starts operation when power supply is started. First # 1
In the step (1), the output terminals (O1) to (O6) are set to "Low", and then data for turning off the display by the display unit (DP) is output.
Then, in step # 3, the data for operating the automatic focus adjustment circuit (AF) is not transmitted from the data bus (DB), and in step # 4, the interrupt signal to the interrupt terminal (it) is accepted. The microcomputer (MC1) stops operating.

When the photometric switch (S1) is closed, a "Low" interrupt signal is input to the interrupt terminal (it), the microcomputer (MC1) starts operating, and performs the operation from step # 10. In step # 10, the terminal (O1) is set to “High” and the inverter (IN
The transistor (BT1) is made conductive through 1), and power is supplied from the power supply line (+ V), and power is supplied to circuits other than the microcomputer (MC1) and to the lens circuit (LEC). In step # 11, the terminal (O3) is set to "High" to start reading data from the lens circuit (LEC).
First, a register BR in the microcomputer (MC1) (hereinafter, a register indicated by a code without parentheses,
The flags and the like are set in a program in the microcomputer. ) Is set to "O" and the operation by the serial input / output instruction is performed in the step # 13. As a result, data from the lens (LEC) is read into the serial input / output register IOR. The contents of this register IOR are taken into the determined register, "1" is added to the contents of register BR, "1" is added to the contents of register BR, and the contents of register BR are set to "N".
Is determined. If it is not "N", the flow returns to step # 13 to read the next lens data, and if it is "N", the flow proceeds to step # 17.

Here, reading of lens data will be described based on FIG. 1 and FIG. FIG. 7 is a specific example of the input control circuit (IOC) of FIG. When the terminal (O3) of the microcomputer (MC1) becomes “High”, the AND circuits (AN1) and (AN3)
Becomes active, and the lens circuit (LEC) is also supplied with its "High" signal via the line (L1), and becomes operable. When eight clock pulses are output from the terminal (SCK) of the microcomputer (MC1), the clock pulses are sent to the lens circuit (LEC) via the AND circuit (AN3) and the line (L2). And the lens circuit (LE
From C), the first data is sequentially output to the line (L3) in synchronization with the rise of the clock pulse. This data is input to the terminal (SIN) of the microcomputer (MC1) via the AND circuit (AN1) and the OR circuit (OR1). This data is sequentially read into the register IRO in synchronization with the falling edge of the clock pulse output from the terminal (SCK).

The lens circuit (LEC) includes a ROM in which a plurality of data are fixedly stored in a determined order, addressing means for sequentially designating addresses of the ROM, and data output means for sequentially outputting data from the ROM in series. I have. The addressing means sequentially updates the address data every time eight clock pulses are input from the line (L2), and outputs the data in the order of the determined data type. Then, the microcomputer (MC1) sets the data in the determined register in the order of the input data, so that a certain register has the data of the open aperture value, a certain register has the data of the maximum aperture value, and so on. The determined types of data are set in the respective registers. That is, the contents of the determined register in the microcomputer (MC1) are data of the determined type of the attached interchangeable lens. In the lens data, in the case of data that changes according to a change in the focal length of the zoom lens or data that changes in accordance with the shooting distance (lens extension amount), data corresponding to the set position of the zoom ring and the distance ring is used. An output code plate may be provided, and an address may be specified by a combination of the code plate and data obtained by counting clock pulses from the camera body.

In step # 17, the terminal (O3) is set to "Low" to stop taking in data from the lens circuit (LEC), and then it is determined whether or not the flag JF1 is "1". The flag JF1 is "1" when the calculation of the data for exposure control is completed, and is "0" when the calculation is not completed. And
If JF1 is "0", the calculation is not completed, and the flow shifts to step # 25. On the other hand, if the calculation is completed, it is next determined whether the release switch (S2) is closed and the input terminal (i2) is at "Low". And the terminal (i
If 2) does not become "Low", the flow proceeds to step # 25. On the other hand, if the terminal (i2) is "Low", the release switch (S2) is closed, and then in step # 20, the reset switch (S4) is closed and the input terminal (i3) is closed. Is determined to be "Low". At this time, the charging of the exposure control mechanism is not completed, the switch (S4) is opened, and if the terminal (i3) is "High", the flow proceeds to step # 25. On the other hand, the charging of the exposure control mechanism is completed, the switch (S4) is closed, and the terminal (i3) is set to “Lo”.
If "w", the exposure control operation from step # 80 is performed.

In step # 25, it is determined whether or not check data has been input among the data taken in from the lens. The check data includes data common to all interchangeable lenses (for example, “101010”) in the determined ROM address.
10 ") is stored to indicate this data. If this data is not input, the lens is not mounted, and if input, the lens is mounted. If this is the case, the data relating to the automatic focusing among the data captured from the lens in step # 26 is sent to the automatic focusing circuit (AF) via the data bus (DB), and the operation of this circuit (AF) Let me do #
Move on to step 27. On the other hand, if there is no check data, the lens is not mounted, so that the automatic focus adjustment circuit (AF) remains inactive and the process proceeds to step # 27.

In step # 27, the terminal (O4) is set to "High" to enable data exchange with the flash device and the flash controller. Then, the terminal (O5) is connected for a predetermined period T1.
(High) for 90 μsec. This signal is line (l
It is transmitted to the flash device and flash controller via 3) and (13). Then, the flash device and the flash controller determine that the mode is one in which data from the flash device and the flash controller is transmitted to the camera body (hereinafter, referred to as FC mode). When eight clock pulses are transmitted from the camera to the flash device via the lines (l3) and (13) by the operation according to the serial input / output command, the flash device synchronizes with the rising of the clock pulse. 6-bit data is output via lines (12) and (12), and this data is taken in by the flash controller in synchronization with the falling edge of the clock pulse. And
The flash controller determines the light emission mode according to the read data and the light emission mode (sequential light emission mode, simultaneous light emission mode) set by the flash controller at that time, and clocks the data according to the result in two bits. The line (l
Output via 2) and (12). At this time, the microcomputer (M
C1) takes in the data output to the line (l2) at this time in synchronization with the falling edge of the clock pulse by the input / output register IOR, but the microcomputer (MC1) does not use this signal. Next, in step # 30, eight clock pulses are output to the lines (13) and (13) by the serial input / output command again. At this time, if the flash device is mounted via the flash controller and the hot shoe is also mounted with the flash device, the flash device does not output data to the lines (l2) and (12), and the line (l2) , (12) in an open state so as not to affect the signal transmission, and the flash controller reads the data previously determined from the two flash devices and the data determined by the set light emission mode in response to the clock pulse. Output from the flash controller in synchronization with the rising edge. If the flash device is mounted via the flash controller and the hot shoe is not mounted on the hot shoe, the flash controller outputs data read from the flash device to the line (l2). At this time, the flash device also outputs data to line (12), but this data is shut off by the flash controller. When the flash device is mounted only on the hot shoe, data is output in synchronization with the clock pulse in step # 29, and then the same data is output again in synchronization with the clock pulse in step # 30. . In addition,
Even if the flash controller is mounted on the camera body, when the flash device is not mounted on the connector (CN5) of this flash controller, the flash controller opens the line (l2) and does not affect signal transmission. To do.

Next, data transmitted and received based on 16 clock pulses will be described. The first data of the clock pulse is b0 bit, the second data is b1 bit,
b2, b3, ..., b14, and b15 bits. First, Table 1 shows the data contents of each bit and the states of the camera body, the flash device, and the flash controller.

The flash device outputs the data shown in Table 1 based on the clock pulse from the camera for the 6 bits b0 to b5, and the controller sequentially reads this data. As for the bit b0, a "High" signal is output if the power switch of the flash device is closed. The bit of b1 is the upper light emitting part of the parent-child strobe described above (the one with the largest maximum light emission amount)
Is in a bounce state and is in "Low" when in the parent-child light emission mode, otherwise it is in "High". The bit b2 outputs a signal of "High" if the main capacitor of the flash device is in the full state, and outputs a signal of "Low" if the main capacitor of the flash apparatus is not in the full state. The bit b3 outputs a signal of "Low" if dimming display can be performed by the flash device, and outputs a "High" signal if dimming display is not performed. b4 bits are reserved,
In response to future system developments, for example, when a light emitting unit for auxiliary light for automatic focus adjustment is provided, it is conceivable to output a "High" signal when the light emitting unit is ready to emit light. Can be The bit b5 is data for judging that the system is the system of the present embodiment, and a "Low" signal is always output if the flash device is compatible with the system of the present embodiment. This means that in flash devices currently on the market, "Hig" is always
The flash controller and the camera body all read the "High" signal when such a flash device is attached. This is a signal for distinguishing the flash device from the system.

In the bits b6 and b7, data corresponding to the above-described light emission mode determined according to the data read from the flash device by the flash controller (IV) and the data set by the flash controller (IV) is stored in the flash device line (l2 ), Output to (12). The mounting signal read by the flash controller (IV) and the signal of the actual flash mode determined from the set flash mode are the line (l2),
Output to (12). Table 2 shows signals of this light emission mode.

When the flash device reads the light emission mode signal shown in Table 2, the flash device performs an operation corresponding to the light emission mode signal thereafter.

The flash device outputs data up to bits b0 to b5, and reads data with bits b6 and b7. By the way, a cable may be connected between the connector (CN5) of the flash controller and the flash device and between the connector (CN9) at the position of the hot shoe of the camera body and the flash device, and the signal line (l2), There is a parasitic capacitance and an impedance component between (l3) and the ground. If a “High” signal is output at the timing of the bit (b5) and the flash controller is not mounted, there is no discharge circuit, so that the charge remains stored in the parasitic capacitance, and the bit b6, b7
The flash device reads the "High" signal. In other words, when the flash device is connected to the hot shoe of the camera body via a cable and emits only one light, when a signal of "High" is output at bit b5, this signal remains stored in the parasitic capacitance. So a bit b
In steps 6 and 7, for example, a signal indicating the simultaneous light emission mode or the sequential light emission mode is read by the flash device, and a malfunction occurs. Therefore, in this system, at the bit b5, the discrimination signal "Low" is output so that the parasitic capacitance is discharged due to the short circuit so that the malfunction does not occur.

In the bits b8 to b15, if the flash device is merely connected to the hot shoe of the camera body, the flash device outputs the data shown in Table 1 and the camera body reads the data. If the flash unit is connected to the camera body via the flash controller sends to the camera body through the intact flash controller signals b ₈ ~b ₁₅ from the flash device, that this signal is the camera body reads However, in this case, there are the following problems. That is, if a cable is provided between the flash controller and the flash device, a signal is delayed by the cable and a circuit in the flash controller. Therefore, first, a clock pulse sent from the camera body to the flash device is delayed, and there is a time difference between when the clock pulse rises in the camera body and when it rises in the flash device. And
The flash device detects that the clock has risen and outputs data. This data is sent to the camera body via the cable and the flash controller, but is delayed as in the case of the clock. Then, it is read at the falling edge of the clock in the camera body. However, if the total delay time of the clock delay time and the data delay time is longer than the time from the rising edge to the falling edge of the clock in the camera body, the camera body will read erroneous data. Therefore, in this system, data from the flash device is once read by the flash controller, and then data is sent from the flash controller to the camera body.

If a flash controller is connected to the camera body and no flash device is attached to the connector (CN5) of this controller, the flash controller will be b8 to b1
During the 5 bits, no signal is output to the line (l2), and a high impedance state is set, so that data transmitted from the flash device connected to the hot shoe to the camera body is not adversely affected. If a flash device is mounted on the hot shoe and the flash controller, data “11”, “10”, “b6” and “b7” indicating that the flash is emitted by the flash controller indicate multi-light emission.
Any one of "01" is input to the flash device, and the flash device is on line (l2), (12) between bits b8 and b15.
And outputs a high impedance state without outputting data.
Then, the flash controller reads the data read from both flash devices and the data based on the set flash mode.
The data is output using bits b8 to b15, and the camera body (V) reads this data.

Next, data of bits b8 to b15 will be described. The bit b8 is a mounting signal, and outputs a "High" signal when the power switch is closed when the flash device outputs the signal. If the flash controller outputs, a “High” signal is output if a “High” signal is input from at least one of the flash devices with the b0 bit. The bit b9 is a signal for distinguishing the system of the present embodiment. If the flash device outputs a signal of "Low", the flash controller outputs "Low" signal from at least one of the flash devices by the bit b5. "
If the signal is read, a "Low" signal is output. b1
The bit of 0 is a signal indicating whether the flash device is in the sequential light emission mode. When the flash device outputs data, the signal is “Low” when the flash device is in the parent and child light emission mode, and otherwise outputs the “High” signal. I do. On the other hand, if the flash controller outputs data, it is “Low” in the sequential light emission mode and “Hi” in the other light emission modes.
gh "signal. The bit b11 outputs a full signal. If the flash device outputs, it outputs a" High "signal if it is full. If the flash controller outputs two flashes, If a mounting signal is input from the device and a “High” signal indicating a full state is input at both bits b2 from the two flash devices, a “High” signal is output at bit b11. When a “High” signal is input from only one of the flash units, a “Low” signal is output.The b12 bit is used to obtain an appropriate exposure in photography (flash photography) with the flash unit emitting light. This is a so-called FDC signal indicating that dimming has been performed, and outputs a "Low" FDC signal while the flash device performs dimming completion display when the flash device outputs. If the controller output if FDC signal "Low" from at least one of the flash device is entered in the bit b3 "L
The FDC signal of "ow" is output. The bits b13, b14, and b15 are spare data, and the signal of "Low" is output both when the flash device outputs and when the flash controller outputs. When the data transfer is completed, the flash device and the flash controller enter a mode (hereinafter referred to as a standby mode) in which a pulse is input from the next line (l3) or (13). In this case, the line (l2) is flashed. If the battery is fully charged, it becomes “High”, and if it is not charged, it becomes “Low”.

On the other hand, in the camera body, the data of bits b8 to b15 read into the register IOR from the flash device or the flash controller in step # 31 of FIG. 2 is set in a predetermined register, and the terminal (O4) is set to “Low”. I do. next,
In step # 33, various setting data (exposure control mode, apex value of set exposure time) to input terminal (IP1)
Tvs, Apex value Avs of the set aperture value, Apex value Sv on the film container or of the set film sensitivity, etc.) are taken into the registers corresponding to the respective data. Next, in step # 34, the output Bv-Avo (Bv is the object brightness, Avo is the open aperture apex value) of the photometric circuit (LM) is A / D converted and this data is set in a predetermined register. Then, in the steps # 35 to # 37, it is determined whether or not to shift to the exposure control operation as in the steps # 18 to # 20. If the shift to the exposure control operation is to be performed, the process proceeds to step # 80. If not, proceed to step # 38.

A specific example of the step # 38 is shown in the flowchart of FIG. First, if it is determined in step # 210 that an FDC signal is being input, the state of the FDC display is set, and the charge completion display is reset, and the process proceeds to step # 40. Meanwhile, FD
If the C signal has not been input, the FDC display is reset and it is determined whether or not the completion signal has been input. If the charge completion signal has been input, the charge completion display is set, and if not, the charge completion display is reset, and the process proceeds to step # 40.

In step # 40, it is determined whether check data "10101010" has been input from the interchangeable lens. If the check data has been input, the operations of steps # 41 and # 42 are performed, and if not, the operations of steps # 43 and # 44 are performed. In the stationary light calculation I of # 41, the calculation is performed according to the flowchart shown in FIG. First # 10
In step 1, (Bv−Avo) + Avo + Sv = Ev (1) is calculated. However, Rv is the apex value of the exposure value, so-called Ex
Posure Value. Next, the exposure control mode is determined in step # 102, and the P mode (program exposure mode)
If so, the process proceeds to steps # 103 and 104, and the calculation of p · Ev = Av (2) Ev−Av = TV (3) (0 <p <1) is performed. Here, Av is the value of the aperture opening to be controlled, Tv is the apex value of the exposure time to be controlled, and p is a program constant. This is for determining the ratio, whereby the program diagram is determined. The value of p can be determined at the time of setting, or can be manually set to a desired value. If it is determined that Av <Avo in step # 105, Ava = Avo is set in step # 106, and # 107
In the step, Ev−Ava = Tv (5) is used. And if TvoTv, Tv of formula (5) is Tva
And no warning is given. On the other hand, if Tvo> Tv, T
vo is set to Tva so that an underexposure warning is issued.
Here, Tvo corresponds to the longest exposure time that can be controlled by the camera body. If Av calculated by equation (2) is AvAvo, then Av> A
v Determine if it is _M. If Av> Av _M , the process proceeds to step # 114, Ava = Av _M is set, and in # 115, the operation of the equation (5) is performed. And if TvTv _M , Tv calculated by equation (5)
Is set to Tva so that a warning is issued. Meanwhile, # 116
If Tv> Tv _{M in} the step, Tv _{M is set} to Tva and an overexposure warning is performed. Here, Tv _M is equivalent to the shortest exposure time that can be realized by the camera body.

If it is determined in step # 113 that the current value is AvAv _M , no warning is given, and the Av calculated by equation (2) is used as the aperture value for constant light imaging Ava, and Tv in equation (3) is used as constant light imaging. Ava−Avo = d Ava... (4) is calculated in step # 163, and the calculated d Ava is used as the number of steps for narrowing down the constant light photography, and the data of Ava, d Ava, and Tva are respectively used. Set in a predetermined register.

If it is determined in step # 102 that the mode is not the P mode, then in step # 115 it is determined whether the mode is the S mode. When the exposure control mode is the S mode (exposure time priority / aperture automatic control mode), in step # 126, the set exposure time Tvs is set to Tva, and the calculation of Ev-Tva = Av (6) is performed. Then, in step # 128, if Av <Avo, Avo is set to Ava and an under warning is issued, and if Av> Av _{M in} step # 131, Av _{M is set} to Ava and an over warning is issued. . Also, Av <
If neither Avo nor Av> Av _M , then in step # 134 (6)
The Av calculated by the formula is set to Ava, and a state where no warning is performed is set, and the process proceeds to step # 163.

If it is determined in step # 125 that the mode is not the S mode, it is determined in the next step # 140 whether or not the mode is the A mode.
When the exposure control mode is A mode (automatic aperture priority exposure time control mode), the aperture value A is set in step # 141.
The equation (5) is calculated by setting vs as the aperture value Ava for normal light photography. Then the If step in Tvo> Tv of # 143 Tvo a state where underexposure warning is performed as Tva, a state in which overexposure warning is performed as Tva the Tv _M <Tv if Tv _M in step # 146. If neither Tvo> Tv nor Tv _M <Tv, Tv calculated by equation (5) is set as the exposure time Tva for normal light photography and no warning is given, and the routine goes to step # 163. If the mode is not the P, S, or A mode, the mode is the M mode (manually set exposure control mode). In this case, the process proceeds to step # 155, where Avs and Tvs are set to Ava and Tva, respectively. Further, an operation of Ev− (Tva + Ava) = dv is performed, and for a constant value k (allowable exposure error of the film), if dv <−k, an under warning, if dv> k, an over warning, and −
In the case of kdvk, the state where no warning is given
Move on to step 3. In step # 163, the number of aperture steps d Ava = Ava-Avo for steady light photography is calculated from the aperture value Ava for steady light photography and the open aperture value Avo, and the flow proceeds to the step I of flash photography calculation I in step # 42.

A specific example of the step # 42 is shown in the flowchart of FIG. 5, and the description will be made based on this flowchart. First, in the P mode, when Avo <3 (corresponding to FNO.2.8), Avc1 = 3, when Avo3, Avc1 = Avo, and in step # 174, Avc2 = 6 + (Sv-5) The calculation of (7) is performed. Here 6 is equivalent to FNO.8 and 5 is ISO 1
Corresponds to 00. And Avc2> the Av _M if Av _M and Avc2,
If Avc2Av _M, Avc2 is kept at the value obtained by equation (7) and the process proceeds to step # 177.

Next, the calculation of Ev + 1-6 = Av (8) is performed. Then, the Av calculated by equation (8) is #
If the result of the determination in 178 is Av> Avc2, Avf = Avc2. When Avf + 6Ev, Tvf = 6, and Avf +
If 6 <Ev, Tvf = 7 unless the data from the flash device is in the sequential light emission mode (or the parent-child light emission mode). On the other hand, if the signal of the sequential flash mode is input, Avf
Even if +6 <Ev, Tvf = 6. And
If Av calculated by equation (8) is Avc1AvAvc2,
Av is set to the aperture value Avf for flash photography, the exposure time Tvf for flash photography is set to 6, and the process proceeds to step # 204.

If it is determined in step # 170 that the mode is not the P mode, it is determined in step # 187 whether or not a signal of a light emission mode (or a parent-child light emission mode) is sequentially input from a flash device (or a flash controller). If the mode is the light emission mode, the tuning limit exposure time Tvl is set to 6 (1/60 sec), and if the mode is not the light emission mode, Tvl is set to 7 (1/125 sec), and the process proceeds to step # 190.

If it is determined in step # 190 that the mode is the A mode, the set aperture value Avs is set to Avf and Tvl is set to Tvf, and the process proceeds to step # 204. If it is determined in step # 190 that the mode is not the A mode, the set exposure time Tvs is Tvs> Tv
If l, Tvf = Tvl, if TvsTvl, then Tvf = Tvs. Then, in step # 197, it is determined whether or not the mode is the S mode. If the mode is the S mode, the operation of Ev + 1−Tvf = AV (9) is performed.
Is Avf. If AvoAvAv _M , Av calculated by equation (9) is Avf.
To step # 204. If the mode determined in step # 196 is the M mode, Avs is set to Avf,
The process proceeds to step # 204, where d Avf = Avf-Avo.

Specific examples of the steady light calculation II in step # 43 and the flash light calculation II in # 44 when the lens is not attached are described in the sixth section.
This is shown in the flow chart of the figure. Hereinafter, description will be made based on the flowchart of FIG. First, in step # 220, the calculation of Bv−Avn + Sv = Tv (10) is performed. Where Bv−Avn is the photometric output and Av
The vn is not controlled by the system of the present embodiment, but is manually set by itself, or the iris of an interchangeable lens, an intermediate ring, a bellows, a pinhole photographic adapter or the like in which a specific iris aperture is fixed in advance. Equivalent to the value.

Next, in step # 221, it is determined whether the mode is the M mode or another mode. Then, in the M mode, the set exposure time Tvs is set as the control exposure time Tva, and the calculation of Tva−Tv (Tv in equation (10)) = dv is performed. When dv <−k, an over warning is performed, when dv> k, an under warning is performed, and when −dvkdv, no warning is performed, and the process proceeds to step # 238.

If it is determined in step # 221 that the mode is not the M mode, the automatic exposure control mode is set in this case.
In this case, if the Tv calculated by the equation (10) is TvoTvTv _M , the Tv calculated by the equation (10) is set to Tva and no warning is performed, and if Tv <Tvo, the underwarning is performed by setting Tv to Tva. If Tv> Tv _M, Tv _{M is set} to Tva and an over warning is performed. Then, in step # 238, d Ava is set to 0, warning data is set as Ava so that a warning that the lens is not attached is issued, and the process proceeds to step # 240.

If it is determined in step # 240 that the mode is the P mode, Tvf = 6 if Tv calculated by equation (10) is Tv6 (1/60 sec), and if Tv> 6, then If not in mode, Tvf = 7 (1/125 sec),
In the case of the sequential mode, Tvf = 6 and the process proceeds to step # 253.

If it is determined in step # 240 that the mode is not the P mode, it is determined in step # 245 whether the mode is the sequential mode.
In the case of the sequential mode, the tuning limit exposure time Tvl =
6. If the mode is not the sequential mode, Tvl = 7 and the process proceeds to step # 248. In step # 248, it is determined whether the mode is the A mode. If the mode is the A mode, Tvf = Tvl and the process proceeds to step # 253. On the other hand, if it is not the A mode, it is determined whether the set exposure time Tvs is TvsTvl, and if TvsTvl, Tvs is set.
If it is Tvf, Tvs.Tvl, Tvl is set to Tvf and the process proceeds to step # 253. In step # 253, d Avf is set to 0, and Av
As f, warning data is set so that a warning that a lens is not mounted is issued, and the process proceeds to step # 45. In the sequential flash mode, since the maximum of three flash units emit light, the shortest limit of the exposure time is after the time required for the X contact (Sx) to close and the three lamps to sequentially emit light after the shutter. Tv = 6 (1/60 sec) when the curtain comes out, and if not in sequential emission mode, the minimum exposure time is X contact (Sx)
Tv = 7 (1/125 sec) at which the rear curtain of the shutter appears after a time required for one lamp to emit light after the shutter is closed.

Upon completion of the above operation, the flow shifts to step # 45 to determine whether or not a charge completion signal has been input from the flash device. If the fill signal is input, flash photography can be performed.
A signal indicating the Avf, the exposure time Tvf, and the state of the flash device (fully charged, dimming display) is sent to the display unit (DP).
On the other hand, when the filling signal is not input, the stationary light imaging is performed, so that the aperture value Ava, the exposure time Tva, and the warning data for the constant light imaging are sent to the display unit (D). And # 48 ~
In step # 50, it is determined whether or not to shift to the exposure control operation as in steps # 18 to # 20. If the shift to the exposure control mode is to be performed, the process shifts to step # 80. Move to step.

In step # 55, the microcomputer (MC1) terminal (O
4), (O6) is set to “High”. As a result, the NAND circuit (NA1) and AND circuit (AN11) shown in FIG. 7 become active, and the data from the camera body is transferred to the lines (l2) and (1).
The state is transmitted to the flash device via 2). The terminal (O5) is connected to the terminal (O5) for a predetermined time T2 (for example, 150
μsec) “High” signal is output, and this signal
It is determined that the mode is a mode in which data is transmitted to the flash device and the flash controller via 3) and (13) and data is transmitted from the camera to the flash device (hereinafter, referred to as CF mode). Then, the microcomputer (MC1) sets the aperture value Avf for flash photography in the serial input / output register IOR, and outputs this data in series. Then register IOR
The data of the film sensitivity Sv and the mode are set, and the data is output in series. Next, the focal length fv of the interchangeable lens is set and output in series. Then, in the step # 63, the terminals (O4) and (O6) are set to "Low", and the process proceeds to the next step # 64.

Next, transmission and reception of data between the flash device and the camera body will be described with reference to FIG. First, in the FC mode, the terminal (O6) becomes “Low”, the output of the NAND circuit (NA1) becomes “High”, the output of the AND circuit (AN11) becomes “Low”, and the transistors (BT15) and (BT17) It is non-conductive. Therefore, the terminal (l2) is open. When a clock pulse is output from the terminal (SCK), the clock pulse is output via an AND circuit (AN5) and an OR circuit (OR3), and the clock pulse is set to “High”.
In the case of, the transistor (B
T11) conducts, a “High” signal is output to line (l3), and when the clock pulse goes “Low”, the transistor (BT13) conducts by the inverter (IN5) and “ A "Low" signal is output. In this FC mode, serial data is input from the flash device. At this time, since the transistors (BT15) and (BT17) are non-conductive, when the line (l2) becomes “High”, the transistor (BT19) is turned off. The output of the inverter (IN7) becomes “Hig”
h ”, when the line (l2) goes“ Low ”, the transistor (BT
19) becomes non-conductive, and the output of the inverter (IN7) becomes “Lo”.
w ". The output of this inverter (IN7) is an OR circuit (O
R1) is read into the microcomputer (MC1) from the serial input terminal (SIN) of the microcomputer (MC1).

In the CF mode, the terminal (O6) becomes "High", and the NAND circuit (NA1) and the AND circuit (AN11) are in an active state. Then, the data from the serial output terminal (SOU) is output via the AND circuit (AN9), and when the “High” signal is output, the output of the NAND circuit (NA1) becomes “Low”, and the transistor ( BT15) conducts and the line (l
2) becomes “High”. On the other hand, when the output of the AND circuit (AN9) becomes “Low”, the output of the AND circuit (AN11) becomes “High”.
And the transistor (BT17) becomes conductive, and the line (l2) becomes "Low".

Returning to the flowchart of FIG. 2 again, the microcomputer (MC
In step # 64 where the operation of 1) is continuously described, since the preparation for the exposure control is completed, the content of the determination flag JF1 is set to "1".
Then, similarly to the steps # 19 and # 20, it is determined whether or not to shift to the exposure control operation. If the operation shifts to the exposure control operation, the operation proceeds to step # 80. If the operation does not shift to the exposure control operation, the operation proceeds to step # 70. #
In step 70, it is determined whether the photometric switch (S1) is closed and the input terminal (i1) is "Low". If "Low", the process returns to step # 11 and repeats the above-described operation. On the other hand, in step # 70, the input terminal (i1)
gh "for automatic focus adjustment circuit (AF) in step # 71
Stop the operation of, turn off the display of the display unit (DP), flag
JF1 is set to “0”, the interrupt signal from terminal (it) is accepted, terminal (O1) is set to “Low”, and transistor (BT
By turning off 1), power supply from the power supply line (+ V) is stopped, and the microcomputer (MC1) stops operating.

When performing the exposure control operation, the operation from step # 80 is performed. Automatic focus adjustment circuit (AF) in # 80 steps
Stop the operation of. Next, the terminal (O4) is set to “High”, and the terminal (O5) is kept at the terminal (O5) for a predetermined time T3 (for example, 210 μsec).
Outputs a “High” signal and sets the terminal (O4) to “Low”.
The flash device and the flash controller read this signal to determine that the exposure control operation is being performed (hereinafter referred to as the ES mode), and the closing signal of the X contact (Sx) of the camera body is transmitted from the line (1). Wait for typing. Next, in step # 84, it is determined whether or not a charge completion signal has been input from the flash device. If the signal has been input, the exposure control values Tvf and d Avf for flash photography are controlled via the output terminal (OP1). Exposure control value Tv for steady light photography if sent to circuit (ECC)
a, d Ava is connected to the exposure control circuit (EC
Send to C). At the time of flash photography, it is determined in step # 86 whether or not a signal of a sequential light emission mode is input.
An analog signal corresponding to Sv-0.5 is output from the terminal (ANO) from the terminal (ANO) unless the light emission mode. The meaning of the analog signal from this terminal (ANO) will be described later with reference to FIG.

In step # 90, the display on the display unit (DP) is turned off, and then the terminal (O2) is set to "High". by this,
The release circuit (RL) operates and the exposure control operation starts. Then, the aperture is controlled, the reflecting mirror is raised, and when the raising is completed, the front curtain of the shutter starts running. When the traveling of the shutter first curtain is completed, X
When the contact (Sx) is closed and flash photography is performed, flash emission is performed. The control of the flash emission amount will be described later with reference to FIG. Then, after the traveling of the front curtain starts, when the exposure time determined as described above elapses, the traveling of the rear curtain of the shutter starts, and when the traveling of the rear curtain of the shutter is completed, the reflecting mirror lowers, and the diaphragm stops. Is open. Since the switch (S4) is opened when the above exposure control operation is completed, the microcomputer (MC1) determines in step # 92 that the switch (S4) is opened and the input terminal (i3) becomes "High" in step # 92. wait. When the input terminal (i3) becomes "High", the terminal (O2) is set to "Low" in step # 93.
And the photometric switch (S1) is closed and the input terminal (i1)
Is determined to be "Low". And
If “Low”, go to step # 11 and “Hig
If "h" has been reached, the process proceeds to step # 95 and the flag JF1
Is set to “0”, the interrupt signal to the terminal (it) can be accepted, the terminal (O1) is set to “Low”, the power supply via the power supply line (+ V) is stopped, and the microcomputer (MC1) stops operating. .

Next, the light emission amount control operation of the flash device will be described based on a specific example of the light emission amount control circuit (FST) shown in FIG. In FIG. 8, (PD) is a light receiving element arranged at a position for receiving the light reflected by the film surface after passing through the taking lens and the aperture of the camera. The output current of this light receiving element (PD) is a diode (PD). D11) is logarithmically compressed. Since the analog output terminal (ANO) outputs a signal of Sv in the sequential light emission mode, and a signal of Sv-0.5 if not in the sequential light emission mode, the output of the operational amplifier (OA) is based on the flash light emission in the flash light emission. It has information on the intensity of the light reflected from the subject, the control aperture value, and the film sensitivity.
Sv−Avf or Qv + (Sv−0.5) −Avf. Here, Qv is a value obtained by logarithmically compressing the reflected light intensity from the subject under flash illumination. The output of this operational amplifier (OA) is logarithmically expanded as its collector current by a transistor (BT29), and this collector current is integrated by a capacitor (C11). Therefore, the integrated voltage of the capacitor is 2 ^Sv · ∫2 ^Qv dt / 2 ^Avf or 2 ^Sv−0.5 · ∫2 ^Qv dt / 2 ^Avf .

Terminal (O2) is “High” when exposure control operation starts
When this terminal (O2) becomes “High”, the AND circuit (AN13) becomes active and the output becomes “High”.
Becomes Also, the “High” signal from the terminal (O2) is delayed by the delay circuit (DL1), and then the T flip-flop (T
F1) and the reset terminal of the D flip-flop (DF1), and the reset state of these flip-flops (TF1) and (DF1) is released to make them operable. Therefore, at this point, both the flip-flops (TF1) and (DF1) have Q
The output is “Low” and the output is “High”. The terminal (INT) is the output of the inverter (IN7) in FIG. 7, and is a signal from the flash device via the line (12).
Then, this line (l2) becomes “High” in the ES mode until the flash is started if the flash is fully charged, and
When the X contact (Sx) is closed, it becomes "Low" for 2.5msec, then "High" for 1msec, and then "Low" for 5.5msec
And then “High”. Therefore, when the output of the delay circuit (DL1) in FIG. 8 becomes "High", the output of the AND circuit (AN15) is "Low", the output of the inverter (IN9) is "High", and the NAND circuit (NA3) ) Is “High”, the output of the NAND circuit (NA4) is “Low”, and the transistor (BT2
1) and the transistor (BT27) are conducting. Therefore,
The non-inverting input terminal of the comparator (AC1) is a resistor (R2 / 3)
And the level of the constant current source (CI1). The resistance value of these resistors (R2 / 3) and the value of the constant current are 70
% Level of potential.

Next, the light emission amount control operation will be described from the case of not sequentially in the light emission mode. When flash emission starts, an AND circuit (AN
The output of 13) becomes “Low”, the output of the NAND circuit (NA4) becomes “High”, the transistor (BT27) becomes non-conductive, and the collector current of the transistor (BT29) is integrated by the capacitor (C11). In this case, the analog output terminal (AN
Since O) outputs a signal of Sv−0.5, 2 ^Sv · ∫2 ^Qv dt / 2 ^Avf −2 ^0.5 ≒ 0.7 · 2 ^Sv · ∫2 ^Qv dt / 2 ^Avf = R _2/3 = 0.7K… (11) When (K: constant corresponding to proper exposure), the output of the comparator (AC1) is inverted to “High” and a “High” pulse is output from the one-shot circuit (OS1). This pulse is output to the line (13) via the circuit shown in FIG. 7, and the flash emission stops. (11)
ceremony Therefore, the flash light is emitted until the proper exposure is obtained. Thereafter, the circuit shown in FIG. 8 performs the operation described later based on the signal from the terminal (INT), but does not affect the flash light emission because it is not in the sequential light emission mode.

In the sequential light emission mode, the operation at the time of the first light emission is performed in the same manner as described above. However, since the Sv signal is being output from the analog output terminal (ANO) at this time, 発 光 2 ^Qv dt is 70% of the proper exposure.
When the terminal (INT) rises from “Low” to “High”, the T flip-flop (TF1) inverts the output and the Q output becomes “Hig”.
h ", the output becomes" Low ". On the other hand, the D flip-flop (DF1) takes in the output of the comparator (AC1) at this time, and if the light emission amount of the first lamp has reached 70% of the appropriate exposure, Q The output becomes “High” and the Q output becomes “Low.” If the light emission amount of the first lamp does not reach 70% of the appropriate exposure, the output of the comparator (AC1) remains “Low” and the D flip-flop (DF1 ) Q output is “Low” and the output remains “High.” When the first light emission reaches 70% of the proper exposure, the output of the NAND circuit (NA3) becomes “High”. Since the output of the NAND circuit (NA4) remains at “Lo” after a certain period of time set by the delay circuit (DL3) since the terminal (INT) becomes “High”
w ", the transistor (BT27) conducts and the integrated charge of the capacitor (C11) is discharged. On the other hand, if the first light emission does not reach 70% of the appropriate exposure, the NAND circuit (NA
The output of 3) is inverted to “Low”. Therefore, the delay circuit (DL
Even if the output of 3) is inverted to “High”, the output of the NAND circuit (NA4) remains “High”, the transistor (BT27) does not conduct, and the integrated charge of the first lamp by the capacitor (C11) is retained. Will remain.

When the light emission amount of the first lamp reaches 70% of the proper exposure, the output of the AND circuit (AN15) becomes “High”, the output of the inverter (IN9) becomes “Low”, and the transistor (BT23) conducts.
The level of the non-inverting input terminal of the comparator (AC1) is a level that can be determined by the resistance (R1 / 3) and the constant current source (CI1). The resistance value of this resistor (R1 / 3) generates a potential of 30% of the proper exposure with the constant current of the constant current source (CI1). On the other hand, if the exposure does not reach 70% of the appropriate exposure, the NAND circuit (NA
The output of 3) becomes “Low” and the transistor (BT25) is turned on. As a result, the level of the non-inverting input terminal of the comparator (AC1) becomes a level that can be obtained by the resistor (R1) and the constant current source (CI1). A potential of a level corresponding to proper exposure is generated. Therefore, the comparator (AC
A voltage corresponding to an appropriate exposure level is applied to the non-inverting input terminal of 1). When the light emission of the second lamp starts, the terminal (INT) falls to “Low”, and when the first lamp reaches 70%, the transistor (BT27) becomes nonconductive again and the transistor (BT29) Is integrated again by the capacitor (C11). On the other hand, when the exposure amount by the first light emission does not reach 70% of the appropriate exposure, the transistor (BT27) remains non-conductive, so that the capacitor (C11) is integrated by the first light emission. The charge is integrated so that the integrated charge of the second lamp is added to the charge. And when the exposure by the first light emission reaches 70% of the appropriate exposure When the condition is satisfied, the light emission stop signal is output, and the light emission amount of the second lamp is 30% of the appropriate exposure. In this case, the ratio of the light emission amounts of the first and second lamps is 7: 3, and the total of both light emission amounts Is the appropriate exposure, while if the first light emission does not reach 70% of the appropriate exposure, , A second light emission stop signal is output. Therefore, in this case, the ratio of the light emission amounts of the two lamps cannot be controlled to 7: 3, but the proper exposure is compensated by the two flash light emission.

When three lamps emit light continuously, after the time required for the second lamp to start emitting light and for the second lamp to emit all light (2.5 mse
c) The third lamp emits light. At this time, the terminal (INT) is “Low”
In this case, the integration by the capacitor (C11) is continued, and for example, if the light emission of the two lamps does not reach the proper exposure, the light emission stop signal may be output to the line (l3) by the light emission of the third lamp. However, this emission stop signal is not transmitted to the third flash device as shown in FIG. 1, and the third flash device emits light by the amount that can be obtained by the flash device. In addition, the first and second flash units receive a flash stop signal only for 2.5 msec after the second flash starts for outputting the FDC signal, and emit a flash for controlling the flash amount. Start flashing,
Since the light emission stop signal is received only for 2.5 msec, the light emission stop signal due to the light emission of the third light is output for the first light or the second light.
It does not act on the flash device of the lamp and cause a malfunction.

Next, a specific example of the flash device (I) shown in FIG.
Description will be made based on FIG. 10, FIG. 11, FIG. 11, FIG. 12, FIG. 13, and FIG. FIG. 9 shows a specific example of the control circuit (FLC1). From the terminal (l3), pulses with widths indicating FC mode, CF mode, and ES mode, data transfer clock pulses,
A pulse for stopping light emission is input, and the terminal (l3) is set to “High”.
, The transistor (BT31) becomes conductive, and the output (p3) of the inverter (IN11) becomes “High”. The mode determination circuit (TIC) detects the "High" width of this terminal (p3) and controls the operation of the flash device.

Next, the determination operation will be described based on a specific example of the mode determination circuit (TIC) shown in FIG. When the X contact (Sx) is closed and the line (1) is at the ground potential, the terminal (p1) becomes "High" by conducting the transistor (BT39) shown in the lower left of FIG. This pin is low when a pulse of width indicating FC mode, CF mode, ES mode and a clock pulse for data transfer are input, and the output of the inverter (IN19) becomes high. I have. When the terminal (p3) becomes “High”, the AND circuit (AN4
The output of 3) rises to “High”, a “High” pulse is output from the one-shot circuit (OS3), and the counter (CO
1) After reset by it, microcomputer (MC2)
The reference clock pulse (φ2) from the terminal (CKO) is counted. In addition, flip-flops (FF1) to (FF7) are set by a pulse from the one-shot circuit (OS3). The terminals (τ1), (τ2), (τ3) of the decoder (DE0) for inputting the signal from the counter (CO1),
From (τ4), 60μsec and 120μ from the start of counting, respectively
A pulse is output after sec, 180 sec, and 240 sec. Therefore, the flip-flop (FF1) is 60
Set state for μsec, (FF3) for 120μsec, (FF5)
Is set for 180 μsec and (FF7) is set for 240 μsec. Therefore, the AND circuit (AN45) is 60 μsec to 120 μ
(AN47) is active for 120 μsec to 180 μsec, and (AN49) is active for 180 μsec to 240 μsec. And the one shot circuit (OS5) is the terminal (p3)
When the potential of the terminal (p3) falls in 90 μsec, the pulse from the one-shot circuit (OS5) is output by the AND circuit (AN4
5), the flip-flop (FF9) is set, and the terminal (FC) becomes “High”. On the other hand, terminal (p3)
Falls in 150μsec, one-shot circuit (OS5)
Is output from the AND circuit (AN47), the flip-flop (FF11) is set, and the terminal (CF) is set to “Hi”.
gh ". If the terminal (p3) falls in 210 μsec, the signal from the one-shot circuit (OS5) is output from the AND circuit (AN49), the flip-flop (FF13) is set, and the terminal (ES) Becomes “High.” A clock pulse is output from the AND circuit (AN43) and pulses are output from the one-shot circuits (OS3) and (OS5). Is 60μsec
Flip-flops (FF9), (FF1
1) and (FF13) are not affected.

When the terminal (FC) becomes “High”, the reset state of the counter (CO3) is released, and the decoder (DE1) is ready to output. The counter (CO3) counts the falling of a signal obtained by inverting the clock pulse for data transfer from the terminal (p3) by the inverter (IN21), that is, the rising of the clock pulse. Then, every time the content of the counter increases by "1", the decoder (DE1) switches the terminals (f0) to (f15).
To output a “High” signal. That is, the counter (CO
If the output of 3) is "0001", (f0) is "High"; if it is "0010", (f1) is "High"; if it is "1000", (f7) is "High", "100".
If "1", (f8) is "High"; if "1111", (f14) is "Hig"
If "h" or "0000", (f15) becomes "High". This signal is used for gate control for data transfer.When the terminal (f15) becomes "High", the AND circuit (AN44) becomes active. , The signal from the inverter (IN21) is output, and the rising of the output of the inverter (IN21)
That is, at the falling edge of the 16th clock pulse in FC mode, a pulse is output from the one-shot circuit (OS4), and at the falling edge of this pulse, the one-shot circuit (OS6) is triggered to output a pulse, and the flip-flop (FF
9) is reset, the pin (FC) goes “Low”, and the standby mode is entered. Also, when the terminal (CF) becomes “High” to enter the CF mode, the reset state of the counter (CO4) is released, and the decoder (DE2) is ready for output. Then, the counter (CO4) counts the clock pulse from the inverter (IN21), and when 24 clocks (for 3 bytes) are counted, the output becomes “11000”,
The terminal (g23) of the decoder (DE2) becomes “High”. Then, the AND circuit (AN46) becomes active and the signal from the inverter (IN21) is output, and the falling of the 24th clock pulse, that is, the falling of the AND circuit (AN46), causes the one-shot circuit (OS8) to output the signal. A pulse is output, and a pulse is output from the one-shot circuit (OS10) at the fall of this pulse. And this one-shot circuit (OS
With the pulse from 10), the flip-flop (FF11) is reset, the terminal (CF) goes low, and the mode changes from the CF mode to the waiting mode. In the ES mode in which (terminal ES) is set to “High”, when the shutter rear curtain of the camera body completes running and the X contact (Sx) is opened, the transistor (BT39) in FIG. 9 is turned off. The terminal (p1) becomes “Low”, the output of the inverter (IN19) becomes “High”, and a pulse is output from the one-shot circuit (OS7). As a result, the flip-flop (FF13) is reset, the terminal (ES) becomes "Low", and the operation mode becomes the standby mode.

Returning to FIG. 9, (FTC1) shown at the lower right is a light emission amount control circuit, and a specific example of this circuit (FTC1) will be described later with reference to FIG. (MC2) is a microcomputer. The operation of this microcomputer (M2) is shown in Figs.
It will be described later based on the flowchart of FIG. In the standby mode, the terminals (FC) and (C) of the mode determination circuit (TIC)
F) and (ES) are all “Low” and the terminal (f0)
Since (f15) is also "Low", the outputs of the NOR circuits (NO3) and (NO5) are "High". As described later, the output (INS) of the light emission amount control circuit (FTC1) is
When the X contact (Sx) is closed in the full state, it stays "Low" until 2.5 msec elapses, then goes "High" for 1 msec, and then "Low" for 5.5 msec Becomes "High" for another 2 msec, and remains at "Low" thereafter. The signal from this terminal (INS) is the X contact (S
X) is closed and the output of the AND circuit (AN24) is forcibly set to "Low" even if the output is full, then the OR circuit (OR2)
The signal is output through an AND circuit (AN21) and an OR circuit (OR5), and is output from the AND circuit (NA18) and the AND circuit (AN19). ) Is output. In the waiting state, the AND circuit (AN24) outputs a “High” signal if the output of the AND circuit (AN33) is “High” in a full state, and outputs a “Low” signal if the output is not charged. Is output. And if it is in the full state, the transistor (BT83),
(BT35) conducts, and a "High" signal is output to the line (l2). If the battery is not charged, the transistors (BT81) and (BT37) conduct to output a "Low" signal.

In the FC mode, the mode determination circuit (TIC) terminal (F
C) becomes “High”, and the output of the NOR circuit (NO5) and the output of the AND circuit (AN21) become “Low”. When the terminal (f0) of the mode discrimination circuit (TIC) becomes “High”, this signal sets the output of the OR circuits (OR7) and (OR5) to “High” and outputs a “High” signal to the terminal (l2). . This signal is the signal of bit b0 in Table 1 above, that is, the attachment signal. When the terminal (f1) of the mode discrimination circuit (TIC) becomes "High", the AND circuit (AN29) is activated, and the light emitting unit (FLO2) of the flash unit (I) in FIG. 1 is in the bounce state. For example, if the switch (SB1) is closed and the "Low" signal does not bounce, the switch (SB1) is opened and a "High" signal is output from the AND circuit (AN29). Therefore,
When a “High” signal is output from the AND circuit (AN29), the output of the AND circuit (AN18) becomes “Low” and the output of the AND circuit (AN19) becomes “Low”, and the transistor (BT8
3) and (BT35) are conducted, and a “High” signal is output to the line (l2). On the other hand, when a “Low” signal is output from the AND circuit (AN29), the output of the AND circuit (AN18) becomes “Low”, the output of the AND circuit (AN19) becomes “High”, and the transistor (BT81) (BT37) becomes conductive, and a “Low” signal is output to the line (l2). This signal is shown in Table 1.
Is the parent-child signal of bit b1. Mode discrimination circuit (TIC)
When the terminal (f2) becomes “High”, the AND circuit (AN31) is activated. As a result, a signal from the AND circuit (A33) is output. The AND circuit (AN33) includes two main capacitors (C) of the flash device (I) shown in FIG.
When the charging voltages of 1) and (C2) reach a predetermined value and the outputs of the charging completion detection circuits (CHD1) and (CHD2) both become "High", a "High" signal is output. The output of the AND circuit (AN33) is output as bit b2 of Table 1, that is, a line (l) as a completion signal.
Output to 2). Mode discrimination circuit (TIC) pin (f3)
Becomes "High", the AND circuit (AN35) becomes active, and the FDC signal from the dimming completion display circuit (INF) (the details of which will be described later with reference to FIG. 12) is output to the line (l2). Is output as a signal of the bit b3. When the terminals (f4) and (f5) of the mode discriminating circuit (TIC) become “High”, the terminals (f4) and (f5) are not connected anywhere, so that the output of the OR circuit (OR5) is output. “Low”, AND circuit (AN1
The output of 9) is “High” and the AND circuit (AN18) is “Low”, the transistors (BT81) and (BT37) are turned on, and a “Low” signal is output to the line (l2). As shown in Table 1, bit b4 is a spare timing, and bit b5 is a discrimination signal indicating that this system is used.

The terminals (f6) and (f7) of the mode determination circuit (TIC) are “Hig
During "h", the output of the NOR circuit (NO3) becomes "Low", and the outputs of the AND circuit (AN18) and the AND circuit (AN19) both become "Low". Therefore, the transistors (BT35) and ( BT37) is turned off, and the transistor (BT33) is turned on / off in response to a signal input from the line (l2).
As described above, the signal of the light emission mode determined by the flash controller is input. Line (l2) is “Hi
When it becomes “gh”, the transistor (BT33) conducts, the output of the inverter (IN13) becomes “High”, and the line (l2) becomes “Low”.
Then, the transistor (BT33) becomes non-conductive, and the output of the inverter (IN13) becomes "Low". Mode discrimination circuit (TI
While the terminal (f6) of C) is “High”, the AND circuit (AN25) is in the active state, and the clock pulse (7) from the terminal (p3) is
The D flip-flop (DF3) outputs the bit b from the terminal (p2) at the falling edge of this pulse.
6 Latch the signal. When the terminal (f7) of the mode discrimination circuit (TIC) is "High", the AND circuit (AN27) becomes active, the eighth pulse is output from the terminal (p3), and the D flip-flop (DF5) Latch the signal of bit b7 from the terminal (p2). Flip-flop (DF
The data latched in 3) and (DF5) is
The light-emission state according to the light-emission mode is sent to the input terminals (i11) and (i12) of (2). Also, if a flash device is mounted in addition to the flash device (I),
As described in Table 1, since at least one of the bits b6 and b7 is "High", the output of the OR circuit (OR8) becomes "High" and the output of the AND circuit (AN23) becomes the mode discrimination circuit. The output of the (TIC) terminals (f8) to (f15)
gh ”, the output is“ High ”and the output of the NOR circuit (NO3) is“ L ”.
ow "causes no signal to be output to the line (l2). In this case, as described above, the flash mode is the simultaneous light emission mode or the sequential light emission mode, and the signals of bits b8 to b15 are transmitted from the flash controller to the line (l2). The transistor (BT35) and (BT7) remain non-conductive during this time, and do not interfere with data transfer between the flash controller and the camera body.

If the signals latched by the flip-flops (DF3) and (DF5) are both "Low", only one flash device is connected to the camera body. In this case, the output of the OR circuit (OR8) and the AND circuit (AN23) is "Low", the output of the NOR circuit (NO3) is "High", and the AND circuit (AN3)
18) and AND circuit (AN19) are active and line (l2)
Data can be output to When the terminal (f8) of the mode determination circuit (TIC) becomes “High”, this “High” signal is output via the OR circuit (OR9), and “High” is output to the line (l2) in the same manner as described above. Is output. This is the mounting signal of bit b8 shown in Table 1. When the terminal (f9) becomes “High”, the OR circuit (O
Since the output of R9) is "Low", the line (l2) becomes "Low". This is the distinction signal of bit b9 shown in Table 1. When the terminal (f10) of the mode determination circuit (TIC) becomes “High”, a signal indicating the open / closed state of the switch (SB1) is output to the AND circuit (A
N37), output from the OR circuit (OR9) and output to line (l2). This is the sequential light emission signal of bit b10 in Table 1. If the light emitting section (FLO2) is in a bounce state, the light emitting section (FLO2) is sequentially in the light emitting mode (or parent-child light emitting mode), and the line (l2) becomes "Low". It is determined that the camera body is sequentially in the light emission mode (or the parent and child light emission mode). When the terminal (f11) of the mode determination circuit (TIC) becomes “High”, a charge completion signal from the AND circuit (AN33) is output from the AND circuit (AN3).
9), and output to the line (l2) via the OR circuit (OR9).

By the way, the flip-flop (FF2) is reset by a pulse output from the one-shot circuit (OS2) when the terminal (FC) of the mode determination circuit (TIC) becomes "High". In the single light emission mode, bit b11
When the transistor (BT35) is turned on as the charge completion signal, the transistor (BT33) is turned on and the terminal (p2) is set to “High”.
become. In this case, the AND circuit (AN20) remains at "Low" and the flip-flop (FF2) remains in the reset state. Therefore, the output of the AND circuit is "High", the AND circuit (AN22) is activated, and the light emission start signal from the terminal (p1) is transmitted to the light emission control circuit (FTC1). On the other hand, when charging is not completed, the transistor (BT37) becomes conductive and the line (l2) becomes "Low", but this turns off the transistor (BT33) and the terminal (p2) becomes "Low". As a result, the flip-flop (FF2) is set, the output of the NAND circuit (NA5) becomes "Low" when the terminal (ES) becomes "High", and the AND circuit (AN22) is disabled.
Flash emission is not performed even if emission start is output from the terminal (p1). Therefore, it is determined whether or not the flash device itself emits light based on the completion signal sent to the camera body at bit b11, and the camera body performs flash light photography based on the completion signal sent at bit b11. The system does not malfunction.

In the multi-light mode, the flash device is set to bits b8 to b1.
Although the signal of 5 is not output, as will be described later, the flash controller is “High” if both flash devices are in the full state, and “Low” if at least one of the flash units is in the full state.
Is output to the line (l2). Then, this signal is read as a complete signal by the camera body, but also in the flash device, it is read by the flip-flop (FF2) to determine whether or not to emit light.

The output to the line (l2) of the flash unit is
The output current when outputting a “High” signal is smaller than the input current when outputting a “Low” signal.
That is, a difference is provided in the impedance. This has such a configuration in order to perform the following operation. That is, a connector for connecting the terminals of two or more flash devices to the camera body in parallel, and a connector for increasing the number of lights for simultaneously emitting light from each flash device can be considered. Terminal (f11) when such a connection is made
Becomes "High" and outputs a completion signal, when at least one flash device is not in a full state, the transistor (BT37) of at least one flash device is turned on and the transistor (BT37) in another flash device is turned on. Even if the transistor (BT35) is conducting, the current from the transistor (BT35) is limited to an integrated current by the constant current circuit (CI10) and the transistor (BT83). Flows into the transistor (BT37) of another uncharged flash device. Therefore, the transistor (BT33) cannot conduct in any flash device, the flip-flop (FF2) is set,
The flash device connected to the multi-flash connector cannot emit light.

When the terminal (f12) of the mode determination circuit (TIC) becomes “High”, the signal from the dimming completion display circuit (INF) is output to the line (l2) via the AND circuit (AN41) and the OR circuit (OR9). You. These are the FDC signals indicated by bit b12 in Table 1, and are read by the camera body and used to display the status of the flash device. Mode discrimination circuit terminal (f1
3) While (f14) and (f15) are “High”, OR circuit (OR
The output of 9) is "Low" and the line (l2) remains "Low", which is a spare bit as shown by bits b13, b14 and b15 in Table 1.

Next, the light emission control operation in the ES mode will be described with reference to FIGS. 9 and 11. FIG. When the X contact (Sx) of the camera body V in FIG. 1 is closed and the terminal (p1) is set to "High", if the flip-flop (FF2) is in a reset state at this time, the NAND circuit (NA5) is set to "High". And the output (FSA) of the AND circuit (AN22) becomes "High" when the battery is in a full state. This allows the one-shot circuit (OS9) in Fig. 11
Outputs a “High” pulse.
The flip-flop (FF15) is reset via the OR circuit (OR13), the flip-flops (FF17) and (FF14) are set, and the Q of the flip-flop (FF14) is set.
When the output becomes “High”, the reset state of the counter (CO5) is released, and the decoder (DE3) is ready to output. Decoder (DE3) has terminal (p1) set to “Hig
After 2.5 msec elapses from "h", a "High" pulse is output. When 3.5 msec elapses, a "High" pulse is output from the terminal (τ6). When 6 msec elapses, a "Hig" is output from the terminal (τ7).
The pulse "h" is output, a "High" pulse is output from the terminal (.tau.8) after 9 msec, and a "High" pulse is output from the terminal (.tau.9) after 11 msec. Q output terminal (p1) is “Hig
h ”and remain“ Low ”for 2.5 msec (p
1) becomes “High” and “High” for 2.5msec to 3.5msec
Then, it becomes "Low" again for 3.5 msec to 9 msec, becomes "High" again after 9 msec elapses, and becomes "Low" again after 11 msec elapses. This Q output is input to the OR circuit (OR2) of FIG. 9 via the terminal (INS). At this time, since the terminal (p1) becomes “High”, the output of the AND circuit (AN24) becomes “Low” and the signal from the terminal (INS) is output from the OR circuit (OR2) even in the full state. Is output. In the ES mode, the output of the NOR circuit (NO5) is “H”
igh ", the signal is output as it is from the AND circuit (AN21) and output to the line (l2) in the same manner as the above-mentioned signal. This signal is used in the camera body for controlling the light emission amount described above with reference to FIG. The line (l
3) To the camera body that does not output the pulse indicating the mode,
When this flash device is mounted, the terminal (ES) is “Low”, so if it is fully charged, “Hig” from the terminal (p1)
h "is output to the terminal (FSA) to emit light.

The terminal (O13) of the microcomputer (MC2) in FIG. 9 is a terminal which becomes "High" in the sequential light emission mode and the first light emission mode as described later. The terminal (O11) is a terminal that becomes “High” in the parent-child light emission mode. The terminal (O12) is a terminal which becomes “High” in the sequential light emission mode and the post light emission mode. (O10) is a terminal which becomes “High” in the simultaneous light emission mode or the single light emission mode. The terminal (O14) is a terminal that is “High” in the automatic light control mode and “Low” in the manual setting mode. In FIG. 9, (FLD) is a circuit for outputting a signal of the light emission amount in the automatic light control mode and the manual setting mode, and an output terminal (e) of this circuit (FLD).
Table 3 shows the relationship between 1) and (e2), the output terminals (d1), (d2), and (d3) of the decoder (DE5) in FIG. 11, the light emission mode, and the light emission amount.

As is clear from this table, when light is emitted by half of the total light emission, the terminal (d2) of the decoder (DE5) becomes "High" and the transistor (BT43) is turned on. The light emitted from the light emitting unit (FLO2) is directly received by the phototransistor (PT1), and the output current of the phototransistor (PT1) is used to make the light emitting unit (FLO2) emit light.
When the output of 1) becomes “High”, the output of the OR circuit (OR20) becomes “Low”, so that the transistor (BT45) becomes non-conductive and integrated by the capacitor (C15). When the integrated voltage of the capacitor (C15) exceeds the potential determined by the resistors (R5) and (R7), the output of the comparator (AC3) becomes “Hig
h ", and a" High "pulse is output from the one-shot circuit (OS11). This pulse stops the light emission. When only 1/4 of the total light emission is performed, the terminal (d3) is set to" High ". As a result, the transistor (BT41) conducts, and the output current of the phototransistor (PT1) is integrated by the capacitor (C13) having a capacitance half that of the capacitor (C15). Is half of the amount of light emission when “High”. In the case of full emission and automatic light control, the terminal (d1) is “High” and the OR circuit (OR20) remains “High”. The transistor (BT45) remains conductive, and no light emission stop pulse is output from the one-shot circuit (OS11).

First, the operation in the parent-child light emission mode will be described. in this case,
The terminal (O11) of the microcomputer (MC2) is "High", and the outputs of the OR circuits (OR15), (OR17), and (OR19) are "High". Therefore, at this time, the X contact (Sx) is closed and the output of the AND circuit (AN51) becomes "High" for 2.5 msec, and the output (ST2) of the OR circuit (OR21) becomes "High". The light emitting unit (FLO2) emits light. During this light emission, if in the automatic light control mode, the AND circuit (AN65) is in the active state,
When the flash stop signal from the camera body is input via the terminal (p3), the signal is output to the terminal (SP2) via the AND circuit (AN65) and the OR circuit (OR25), and the light emitting unit (FLO
2) Stop the light emission. In the manual setting mode, the AND circuit (AN63) is in the active state, and the emission stop signal from the one-shot circuit (OS11) is output to the terminal (SP2) via the AND circuit (AN63) and the OR circuit (OR25). Then, the light emission of the light emitting unit (FLO2) is stopped. Next, the output (ST1) of the AND circuit (AN55) becomes "High" from the time 3.5 msec elapses to the time 6 msec elapses after the X contact (Sx) is closed, and the light emitting section (FLO1) Emits light. If the terminal (O14) of the microcomputer (MC2) is “High” in the automatic light control mode, the light emission stop signal from the terminal (p3) is output to the AND circuit (AN6).
7) is output to the terminal (SP1), and the light emission of the light emitting unit (FLO1) is stopped. On the other hand, in the manual setting mode, since the terminal (O14) of the microcomputer (MC2) is “Low”, the light emission stop signal is not output from the AND circuit (AN67), and the light emitting unit (FL)
O1) emits all light. In this case, in the automatic light control mode, the second light emission stop signal from the terminal (p3) is output via the AND circuit (AN61), the OR circuit (OR23), and the AND circuit (AN69). The signal is input to the dimming completion display circuit (INF) via the terminal (FDS).

In the simultaneous light emission mode or the single light emission mode, the terminal (O10) of the microcomputer (MC2) becomes “High” and the output of the OR circuit (OR17) becomes “High”. Therefore, the X contact (S
The AND circuit (AN51) for 2.5 msec after x) closes
Output becomes “High” and the output of the OR circuit (OR21) (ST
2) becomes “High”. As a result, the light emitting section (FLO2) emits light, and in the automatic light control mode, the terminal (p3)
From the AND circuit (AN65) via the OR circuit (OR25) to the terminal (SP2),
The light emission of the light emitting unit (FLO2) is stopped. On the other hand, in the manual setting mode, the pulse from the one-shot circuit (OS11) is output to the terminal (ST2) via the AND circuit (AN63) and the OR circuit (OR25), and the light emission of the light emitting unit (FLO2) is stopped. . In this case, no “High” signal is output to the terminal (ST1), and the light emitting unit (FLO1) does not emit light. Also, after the X contact (Sx) is closed in the dimming completion display circuit (INF),
The light emission stop signal input from the terminal (p3) during msec is input via the AND circuit (AN59), the OR circuit (OR23), and the AND circuit (AN69).

In the sequential flash mode and the pre-flash mode, the terminal (O1
3) becomes “High” and OR circuit (OR15), (OR17),
The output of (OR19) becomes "High", and the terminal (ST2) becomes "High" for 2.5 msec after the X contact (Sx) is closed. As a result, the light emitting unit (FLO2) emits light. During this light emission, the terminal (p3) or the one-shot circuit (OS11)
The light emission is stopped by the light emission stop signal from. In addition, the dimming completion display circuit (INF) is closed after the X contact (Sx) is closed.
The emission stop signal input from the terminal (p3) from the time when 3.5 msec elapses to the time when 6 msec elapses after the X contact (Sx) is closed is output from the AND circuit (AN61) and the OR circuit (OR).
23), input via AND circuit (AN69). Therefore,
Even if the first light emission does not reach 2/3 of the proper exposure, the FDC display is performed if the sum of the first light emission and the second light emission becomes appropriate.

In the post-emission mode, the AND circuit (AN53) becomes active and 3.5 msec elapses after the X contact (Sx) is closed, and 6 msec elapses after the X contact (Sx) is closed. Until the output of the AND circuit (AN53) is “High”
And the light emitting unit (FLO2) emits light. During this light emission, a light emission stop signal from the terminal (p3) or the one-shot circuit (OS11) is output to the terminal (SP2), and the light emitting unit (FLO2) stops emitting light. I do. Similarly, the signal is input to the dimming completion display circuit (INF) from the time when 3.5 msec elapses after the closing of the X contact (Sx) to the time when 6 msec elapses after the closing of the X contact (Sx). The flash stop signal from the terminal (p3) is input. The light emitting section (FLO1) does not emit light even in the first light emission mode and the second light emission mode.

Next, the dimming completion display circuit (INF) will be described with reference to FIG. The flip-flop (FF21) is set when a light emission stop signal for dimming completion display is input from the output terminal (FDS) of the light emission amount control circuit (FTC1). At this time, in the ES mode, since the terminal (ES) of the mode discrimination circuit (TIC) in FIG. 9 is "High", the output of the AND circuit (AN71) becomes "Low" and the counter (CO7) is reset. Has become. When the terminal (ES) goes to “Low” in the standby mode, the output of the AND circuit (AN71) goes to “High”, the output of the inverter (IN20) goes to “Low”, and the FDC
The signal is output to the AND circuit (AN35). When the output of the AND circuit (AN71) becomes “High”, the counter (CO
The reset state of 7) is released, and the counter (CO7) starts counting clock pulses (φ2) from the microcomputer (MC2). A clock pulse of 8 Hz is output from the terminal (t0) of the counter (CO7), and the light emitting diode (LD1) blinks at 8 Hz by the transistor (BT47). And
After 3 seconds, the terminal (t1) becomes “High”, the flip-flop (FF21) is reset via the OR circuit (OR27), the counter (CO7) is reset, and the output of the inverter (IN20) becomes “ High ", and the light emitting diode (LD1) turns off. When the photographing interval is short, the mode is the ES mode while the light emitting diode (LD1) is being displayed. When the terminal (ES) of the mode discrimination circuit (TIC) in FIG. Is “Low”
And the output of the inverter (IN20) becomes “High”.
Further, the counter (CO7) is reset and the light emitting diode (LD1) is turned off. When the terminal (ES) becomes “High”, a pulse is output from the one-shot circuit (OS13) and the flip-flop (FF21) is reset.

Next, the operation of the microcomputer (MC2) in FIG. 9 will be described based on the flowcharts in FIGS. In the CF mode, the terminal (CF) of the mode discrimination circuit (TIC) is "High"
Becomes “High” at the interrupt terminal (it) of the microcomputer (MC2)
And the operation from step S3 is started.
In step S3, the microcomputer (MC2) can be interrupted to the terminal (it), and data to the terminal (SIN) is read based on the clock pulse from the terminal (p3) to the terminal (SCK). And the flash aperture data (Av
f) is set in a predetermined register in the microcomputer (MC2). Next, similarly, the serial data (the film sensitivity value Sv and the exposure control mode) is read and set in a predetermined register of the microcomputer (MC2). Further, another one byte of the focal length data (fv) of the lens is read and set in a predetermined register in the microcomputer (MC2). Thus, the data from the camera body is read. Next, data for counting a fixed value (for example, 10 seconds) is set in the internal counter, and when the counter reaches the set predetermined value, an interrupt is made. Next, terminals (i13) and (i14) are “High”
Is determined, and if both are "High", the automatic light control mode has been set, so the flow proceeds to step S15. On the other hand, if at least one of the terminals (i13) and (i14) is "Low", in step S14, it is determined whether the exposure control mode read from the camera body is the M mode. If the mode is the M mode, the mode is the manual setting mode, and the process proceeds to step S18. On the other hand, if the mode is not the M mode, the flash device enters the automatic light control mode even if the manual setting mode is set, and shifts to step S15. In step S15, the mode is set to the automatic light control mode, and the process proceeds to step S15. In step S15, an automatic display indicating that the automatic light control mode is set is performed, the terminal (O14) is set to "High", the flag AMF is set to "1", and the process proceeds to step S21. On the other hand, S1
In step 8, a manual display indicating that the mode is the manual setting mode is performed, the terminal (O14) is set to "Low", the flag AMF is set to "0", and the process proceeds to step S21.

From step S21, terminals (i10), (i11), (i1
The light emission mode is determined according to the input signal to 2). If the terminals (i12) and (i11) are "High", the simultaneous light emission mode is set. In step S23, the simultaneous light emission mode is displayed, the terminal (O10) is set to "High", and the terminals (O11) and (O1) are set.
2), (O13) is set to "Low", and the routine goes to Step S34.
Then, in the step S34, it is determined whether or not the terminal (i10) is "High". If the terminal (i10) is "High", the light emitting unit (FLO2) is in the front light state, and the process shifts to the step S36. On the other hand, the terminal (i
If 10) is "Low", it means that the bounce state has been reached, bounce display is performed, and the routine proceeds to step (S60). If the terminal (i12) is “High” and the terminal (i11) is “Low”, pre-emission is performed. In this case, the terminal (O13) is set to “High” in step S24.
To indicate that it is in the pre-emission mode, and the terminal (O1
0), (O11), and (O12) are set to “Low”, and the flow shifts to the step S55. Terminal (i12) is “Low” and terminal (i11) is “Hi”
gh "indicates the post-emission mode, and the terminal (O1
2) Set “High” to indicate that it is in post-emission mode,
The terminals (O10), (O11), and (O13) are set to "Low", and the process proceeds to step S34. When the terminals (i12) and (i11) are "Low", it means that only the flash device (I) is mounted on the camera body directly or via the controller, and the process shifts to step S29. In step S29, it is determined whether the terminal (i10) is “High” and the terminal (i10) is set to “H”.
If “igh”, the light emitting unit (FLO1) is in the front light state, is in the single light emission mode, displays that the single light emission display state is displayed in step S30, and shifts to step S31. ) Is "Low", the light-emitting portion (FLO2) of the flash device (I) is in a bounce state and is in the parent-child light emission mode. In this case, the fact that the parent-child light emission mode is set is displayed in step S48, and the terminal (O11) To “High” and the terminal (O1
0), (O12), and (O13) are set to “Low”. Then, based on the maximum light emission amount and the minimum light emission amount of the light emitting unit (FLO1), the maximum value and the minimum value Iv, Ivm of the light emission amount are set, and the process proceeds to step S41.

In step S36, the irradiation angle data (this is the light emitting unit (FLO
(2) The irradiation angle is variable, and (ZD) outputs data corresponding to the irradiation angle) from the irradiation angle data output circuit (ZD) and displays the irradiation angle. Next, it is determined whether or not the flag AMF is "1". If the flag AMF is "1", the level of the input terminals (i13) and (i14) is determined if the flag AMF is "1" and if "0". In the automatic light control mode or the full light emission mode, the maximum light emission amount of the light emitting unit (FLO2) is set to Iv and the minimum light emission amount Ivm. On the other hand, if the mode is not the full light emission mode, the maximum light emission amount set at that time is set to Iv, and the minimum light emission amount is set to Ivm, and the process proceeds to step S41. In the step S41, it is determined whether or not an interchangeable lens is mounted on the camera body. If no lens is mounted, a message indicating that there is no lens is displayed, and the process proceeds to the step S59. Here, if the interchangeable lens is not attached to the camera body, specific data is input to the flash device as aperture value data Avf, and when it is determined that the flash has input this data, the interchangeable lens is activated. Determine that it is not mounted. If it is determined in step S41 that the lens is attached, the process proceeds to step S43, and the calculation of Iv _M + Sv−Avf = Dv Ivm + Sv−Avf = Dvm (15) is performed, and the longest shooting for proper exposure is performed. The distance Dv _M and the shortest shooting distance Dvm are calculated. Next, to determine whether the short-range than the limit shooting distance Dv _L shortest shooting distance DVM is determined by the rose Lux like, employs a critical object distance Dv as the shortest photographing distance DVM When the DVM <Dv _L, S52 Go to step.

In step S52, it is determined whether or not the flag AMF is "1". If the flag is "1" and the automatic light control mode is set, the interlocking range is displayed from the re-flash amount Iv and the minimum issue amount Ivm, and if the flag AMF is "0". In the case of the manual setting mode, the photographing distance at which proper exposure is performed based on the maximum light emission amount Iv is displayed. Then, after displaying the aperture value based on the flash photography value aperture value data Avf, the focal length based on the interchangeable lens focal length data fv, and the film sensitivity based on the film sensitivity data Sv, step
Returning to S12, the setting data acquisition, calculation, and display operation are repeated, and the terminal (CF) of the mode determination circuit (TIC) is set to “Hig”.
When "h" is set and the interrupt terminal (it) is set to "High", the operation from step S3 is performed again.
It is determined whether or not an interchangeable lens is attached in the same manner as described above, and if so, the process proceeds to step S57, and if not, a message indicating that the lens is not attached is displayed, and the process proceeds to step S59.

The mode in which the shooting range at which the interlocking range or the appropriate exposure is obtained is displayed when the bounce state is not set in the simultaneous flash, single flash, and post-flash modes, and when the parent-child flash mode is used.
In the parent-child light emission mode, an interlocking range or a shooting distance based on the light emitting unit (FLO1) is displayed. When the light emitting unit (FLO2) is in the bounce state in the first light emission mode and in the simultaneous light emission and the second light emission, the interlocking range or the photographing distance is not displayed. If the bounce state has been set for simultaneous light emission, post-light emission, and single-light emission, the bounce display is performed in step S35, and then S
Move on to step 60. Then, a warning is issued because the probability of properness is low if the bounce has occurred during the post-emission, and the process proceeds to step S55.

In FIG. 14, when power is supplied to the microcomputer (MC2), the operation from step S70 is performed. First, in step S70, the terminal (O10) is set to “High” in order to turn off the display of the display unit (FDP1), enable interruption to the terminal (it), and perform the simultaneous mode or the single light emission mode, and set the terminal ( O11), (O1
2), (O13) is set to “Low” and the process proceeds to step S74.

In step S74, signals from the input terminals (i13) and (i14) are determined to determine whether the mode is the automatic light control mode. If the mode is the automatic light control mode, the automatic display is performed, the terminal (O14) is set to "High", the flag AMF is set to "1", and the process shifts to the step S81. If it is determined in step S74 that the mode is not the automatic light control mode, a manual display is performed, the terminal (O14) is set to "Low", the flag AMF is set to "0", and the process shifts to step S81. In step S81, Sv = 5 corresponding to ISO 100 is set, and in step S82, the input terminal (i10)
And determines whether or not the light emitting unit (FLO2) is in a bounce state. If it is in the bounce state, bounce display is performed in step S94, and then the process proceeds to step S95. If it is determined in step S82 that the light emitting unit (FLO2) is in the front light state, the process proceeds to step S83 and the irradiation angle data output circuit (Z
Import the irradiation angle data from D). Then, the irradiation angle is displayed based on the data. Next, the flag AMF is set to “1”.
Is used to determine whether the mode is the automatic light control mode. Then, setting the maximum light emission amount Iv _M and the maximum light emission amount Ivm based on irradiation angle of the light emitting portion if the automatic light control mode (FLO). Then, the calculation of Iv _M + Sv = Gv Ivm + Sv = Gvm is performed, and the maximum guide number G in the SIO 100 is calculated.
v Display _M and the minimum guide number Gvm, and proceed to step S95. On the other hand, if it is determined in step S85 that the AMF is "0" and the automatic light control mode is not set, the terminals (i13) and (i14)
Set the light emission amount Iv _M signal and the set value based on the irradiation angle from, the process proceeds to Gv _M = Iv _M + Sv view and S95 of steps emission guide number Gv based on the set value subjected to operation.

In step S95, a display indicating that there is no lens is performed to indicate that data regarding the lens is not sent from the camera body, SIO 100 is displayed, and the process proceeds to step S97. In steps S97, 98, and 99, it is repeatedly determined whether or not the setting state of the external setting means has changed. If the setting state has changed, the process returns to step S70 to perform the above-described operation again to switch the display state.

An interrupt signal is input from the terminal (CF) to the interrupt terminal (it) from the terminal (CF) for a certain period of time (for example, 10 seconds) after the counter interrupt is enabled. If not, an interrupt is generated by a counter inside the microcomputer (MC2), and the operation from step S70 is performed. Therefore, the display based on the data from the camera body is performed for 10 seconds after the data from the camera body is no longer input, and after 10 seconds, only the data that can be displayed with only the value set in the flash device is displayed. Become.

Next, the flash device (II) based on FIGS.
And (III) will be described. FIG. 15 shows a specific example of the control circuits (FLC2) and (FLC3) in FIG. 1, in which only parts different from those in FIG. 9 are shown, and the corresponding terminals are denoted by the same reference numerals as in FIG. (See FIG. 9 for the same parts.) In the case of this flash device, the light emitting part is (FLO3)
Or, the presence of only one (FLO4) does not result in the parent-child light emission mode. So, in FC mode, bits b1 and b10
Since it is not necessary to output a signal indicating that the mode is the parent-child mode, the terminals (f1) and (f1) of the mode determination circuit (TIC)
The output of (0) is directly input to the OR circuits (OR7) and (OR9), and a "High" signal is output as the bits b1 and b10. Further, the microcomputer (M3) is not provided with a terminal (O11) for outputting a "High" signal indicating the parent-child light emission mode. In addition, the emission control circuit (FTC2) and microcomputer (MC
The operation of 3) is different from that of the flash device (I), but the different parts will be described with reference to FIG.

FIG. 16 shows only parts different from FIG. 11 (see FIG. 11 for the same parts). First, in the simultaneous or single light emission mode, the terminal (O10) of the microcomputer (MC3) in FIG.
gh ", and the output of the OR circuit (OR31) becomes" High ".
Therefore, from the terminal (ST4), the X contact (S
“Hig” from the point when x) is closed until 2.5 msec elapses
h "of the flip-flop (FF17) (see Fig. 11)
The output is output from the terminal (ST4) via the AND circuit (AN75) and the OR circuit (OR35), and the light emitting unit (FLO) shown in FIG.
3) or (FLO4) emits light. During the light emission, in the automatic light control mode, the light emission stop signal from the terminal (p3) is sent to the terminal (SP) via the AND circuit (AN83) and the OR circuit (OR39).
4), and also sent to the dimming completion display circuit (INF) via the AND circuit (AN87) to stop the light emission of the light emitting unit (FLO3) or (FLO4) shown in FIG. The dimming completion is displayed. In the manual setting mode, a pulse from the one-shot circuit (OS11) (see FIG. 11) is output via the AND circuit (AN85) and the OR circuit (OR39), and light emission is stopped. In the pre-flash mode, the microcomputer (MC
3) terminal (O13) becomes “High” and OR circuit (OR3
1), (OR33) output becomes “High”. Then, the Q output of the flip-flop (FF17) is output via the AND circuit (AN75) and the OR circuit (OR35), and the light emitting section (FLO3) or (FLO4) emits light as soon as the X contact is closed. Also in this case, the light emission is stopped by a light emission stop signal input during light emission. On the other hand, the dimming completion display circuit (IN
F) In the case of the automatic light control mode, “Hig” is set for 2.5 msec after 3.5 msec has passed since the X contact (Sx) was closed.
The Q output of the flip-flop (FF19) that becomes "h" is output from the AND circuit (AN81) and the OR circuit (OR37), and during this time, the light emission stop signal input from the terminal (p3) is input. For example, the terminal (O12) becomes “High”, the output of the OR circuit (OR33) becomes “High”, and becomes “High” for 2.5 msec after 3.5 msec elapse from the time when the X contact is closed. The Q output of the flip-flop (FF19) is output via an AND circuit (AN79) and an OR circuit (OR35) to start light emission, and from a terminal (p3) input during this light emission or a one-shot circuit (OS11). In this case, in the automatic light control mode, the stop signal input during light emission from the terminal (p3) via the AND circuit (AN87) causes the light control display (INF) to stop. Sent to

FIG. 17 shows only a part of the flowchart of the operation of the microcomputer (MC3) shown in FIG. 15 which is different from the flowchart of FIG. 13, and FIG.
This will be described with reference to the drawings. From S21, the light emission mode is determined by observing the output states of the terminals (i11) and (i12) as in FIG. If the terminals (i12) and (i11) are both "High", the simultaneous emission mode is set. The simultaneous emission mode is displayed in step S101, and the terminal (O10) is set to "High" in step S105.
And the terminals (O12) and (O13) are set to “Low”, and step S3
Go to step 4 and determine if it is in a bounce state. Terminal (i1
If 2) is “High” and the terminal (i11) is “Low”, it is the pre-emission mode. In step S102, the pre-emission mode is displayed, and the terminal (O13) is set to the “High” terminals (O10) and (O12). ) To “Lo
The process moves to step S55 in FIG. 13 as “w”. Terminal (i12)
Is "Low" and (i11) is "High", the post-emission mode is displayed, terminal (O12) is set to "High", terminals (O10) and (O13)
Is set to “Low”, and the process proceeds to step S34. Terminal (i12),
If both (i11) are “Low”, the single-light emission mode is displayed in step S104, and the process proceeds to step S105.

FIG. 18 is a diagram showing a specific example of the internal circuit (CNC) of the flash controller (IV).

(TIC) is a mode discriminating circuit, which is the same as the mode discriminating circuit of FIG. 9 whose specific example is shown in FIG. 10, and is denoted by the same reference numerals. First, the operation in the FC mode will be described. First, the terminals (f0) to (f5) of the mode determination circuit (TIC)
Are high, the outputs of the NOR circuits (NO11) and (NO15) are "Low", and the AND circuits (AG2), (AG64), and (AG
1) and (AG65) are disabled, and lines (l2) and (1
The data from 2) is read. Then, the signal from the line (l2) is output to (r21) via the transistor (BT53) and the inverter (IN27), and is output to the line (1
2) The signal from the transistor (BT69) and the inverter (I
N31) and output to terminal (r22). The signals of the bits b0, b2, b3, and b5 from the terminal (r21) are latched by the D flip-flops (DF11), (DF13), (DF15), and (DF17). On the other hand, bits b0, b1, b2,
The signals of b3 and b5 are D flip-flops (DF19), (DF2
1), (DF23), (DF25), and (DF27) are latched.
When the light emitting mode is sequentially selected by the switch (SS), the switch is opened, and when the light emitting mode is the simultaneous light emitting mode, the switch is closed. If the Q output of each of the D flip-flops (DF11) and (DF19) is "High", it means that two flash units are mounted, and the AND circuit (AG
The output of 47) becomes “High”. On the other hand, if the Q output of at least one of the D flip-flops (DF11) or (DF19) is "Low", the two flash devices are not mounted, and the output of the AND circuit (AG47) is "Low". The output of the AND circuit (AG45) is (α0) and the AND circuit (AG
The outputs of 59) are both "Low". D flip-flops (DF17) and (DF27) are flip-flops that latch the discrimination signal at bit b5, and both flash devices are compatible with this system when both input a "Low" signal. At this time, the AND circuit (AG63) outputs a "High" signal. On the other hand, if at least one of the two flash devices outputs only a "High" signal to the terminal (12), the output of the AND circuit (AG63) becomes "Low". The AND circuit (AG61) is a flash device compatible with this system, and the output of the AND circuit (AG61) becomes "High" when the sequential mode is selected. On the other hand, if at least one of the flash devices is not compatible with this system, the sequential mode is selected, and the output of the AND circuit (AG61) is "Low" even when the switch (SS) is open. Then, if two flash devices are mounted and the AND circuit (AG47) is "High" and the output of the AND circuit (AG61) is "High", the light emitting mode is sequentially set, and the output (α0) of the AND circuit (AG45) is changed. It becomes “High”. On the other hand, even if the output of the AND circuit (AG47) becomes "High", if the output of the AND circuit (AG61) becomes "Low", the output of the AND circuit (AG59) becomes "High" and the simultaneous mode is set.

In the sequential mode, when the terminal (f) of the mode determination circuit (TIC) is “High”, “L” from the AND circuit (AG59) is output.
ow "signal is the AND circuit (AG41), OR circuit (OR4
7), (OR43), (OR41), AND circuit (AG1), and output to line (12) via transistor (BT57). When the terminal (f7) of the mode determination circuit (TIC) becomes "High", a "High" signal from the AND circuit (AG47) is output from the AND circuit (AG43), the OR circuit (OR47), (OR43), (OR4
1), output to line (l2) via AND circuit (AG2) transistor (BT55). Therefore, the flash device directly connected to the hot shoe of the camera body is “01”,
That is, a signal indicating the post-light emission mode is sent. On the other hand, when the terminal (f6) is “High”, “H” from the AND circuit (AG47) is output.
igh "signal is an AND circuit (AG55), OR circuit (OR5
1) Output to line (l2) via AND circuit (AG64) and transistor (BT65). When the terminal (f7) of the mode determination circuit (TIC) becomes “High”, a “Low” signal from the AND circuit (AG59) is output from the AND circuit (AG57), the OR circuit (OR51), the AND circuit (AG65), Output to the line (12) via the transistor (BT67). Therefore, "10", that is, the signal of the pre-emission mode is input to the flash device directly connected to the flash controller.

In the simultaneous emission mode, the AND circuit (AG47), (AG
59) are both "High". Therefore, the AND circuits (AG41), (AG43), (AG55) and (AG57) output "High" when the terminals (f6) and (f7) are "High". A "High" signal is output, and this signal is sent to both flash units. That is, a simultaneous emission mode signal of "11" is sent to both flash devices. When neither the sequential mode nor the simultaneous mode, the sand flash device is installed,
When only one is mounted, the output of the AND circuit (AG47) becomes “Low” and the output of the AND circuit (AG59) also becomes “Lo”.
Therefore, the signal of "00" is output to the lines (l2) and (12) as the bits b6 and b7, and only the flash device that has read this signal is mounted on the camera. And determine that it is not.

Next, terminals (f8) to (f15) of the mode determination circuit (TIC)
Will be described with reference to FIG. First,
When the output of the D flip-flop (DF19) is "High", that is, when the mounting signal is not inputted from the line (12), the terminal (α3) becomes "High", and during this time, the OR circuit (OR46) Since the output is "High", the output of the AND circuit (AG13) becomes "High". Therefore, the NOR circuit (N
O11) output becomes “Low” and the AND circuits (AG2) and (AG
1) is disabled and the line (l2) is in a high impedance state. The output of the AND circuit (AG47) is “High” when the mounting signal is input to both lines (l2) and (12).
And the AND circuit (AG21) is activated. First, the “High” signal of the terminal (f8) is sent from the OR circuit (OR49) to the line (l) via the AND circuit (AG21), the OR circuit (OR43), (OR41), the AND circuit (AG2), and the transistor (BT55).
Output to 2). This is the mounting signal of bit b8 shown in Table 1. The terminal (f9) of the mode determination circuit (TIC) is set to “H”.
igh ", D flip-flop (DF27), (DF17)
Input of the output of OR circuit (OR55) output (α6)
Is output from the AND circuit (AG33) and output to the line (l2). Output of OR circuit (OR55) (α
6) becomes "High" if at least one of the flash devices compatible with this system is mounted, and this is inverted and output, so that at least one of the flash devices suitable for this system is mounted. And “Lo
The signal "w" is output from the line (l2). This is the distinction signal indicated by the bit b9 in Table 1. When the terminal (f10) of the mode determination circuit (TIC) becomes "High" A signal obtained by inverting the output (α0) of the AND circuit (AG45) is output from the AND circuit (AG35).
Become "High" in the sequential light emission mode. Therefore, this signal is a sequential signal indicated by bit b10 in Table 1. When the terminal (f11) of the mode determination circuit (TIC) becomes “High”, the output (α2) of the AND circuit (AG49) is output from the AND circuit (AG37) and output to the line (l2). The AND circuit (AG49) is a D flip-flop (DF1
3) and (DF23) Q outputs are input, and each flip-flop latches the filling signal sent from the flash device at bit b2. Therefore, the AND circuit (AG49) becomes "High" when both flash devices are in the full state, and this signal is the full signal shown by bit b11 in Table 1. When the terminal (f12) of the mode determination circuit (TIC) becomes “High”, the AND circuit (AG39) becomes active, and a signal obtained by inverting the output (α5) of the OR circuit (OR53) is output to the line (l2). You. The OR circuit (OR53) receives the outputs of the D flip-flops (DF15) and (DF25) as inputs, and the flip-flops (DF15) and (DF25) latch the FDC signal at bit b3 from the respective flash devices. Therefore, when the FDC signal is output at bit b3 from at least one of the flash devices, the output of the OR circuit (OR53) becomes “High”, which is inverted to “Low” and output to the line (l2). This signal is the F of bit b12 in Table 1.
It becomes a DC signal. Mode determination circuit (TIC) terminal (f13),
Line (l2) when (f14) and (f15) become “High”
Remains "Low", which is a spare bit as shown by bits b13, b14 and b15 in Table 1.

The mounting signal is input from the line (12), the Q output (α1) of the D flip-flop (DF19) becomes “High”, the mounting signal is not input from the line (l2), and the D flip-flop (DF11) If the Q output of is “Low”,
The output of the AND circuit (AG51) becomes “High”, and the AND circuit (AG19) is activated. First, the mode discrimination circuit (TI
When the terminal (f8) of C) is “High”, this signal is directly output to the OR circuit (OR45), AND circuit (AG19), and OR circuit (O4
3), output from (OR41) and output to line (l2). This becomes the mounting signal of bit b8. When the terminal (f9) becomes “High”, the Q output (α8) of the D flip-flop (DF27) is output from the AND circuit (AG27). This signal is a discrimination signal of bit b5, and this signal is output to the line (l2) and becomes a discrimination signal of bit b9. When the terminal (f10) becomes “High”, the D flip-flop (DF2
The Q output (α4) of 1) is output from the AND circuit (AG27). This signal indicates “Lo” if the flash device attached to the line (12) is in the parent-child flash mode.
w "is" High "when the single-light emission mode is set. This signal is output to the terminal (f10) of the mode determination circuit (TIC).
Is output to the line (l2) at the timing of “High”.
This is the sequential light emission mode signal indicated by the bit b10. When the terminal (f11) of the mode determination circuit (TIC) becomes “High”, the Q output (α3) of the D flip-flop (DF23) is output from the AND circuit (AG29). This signal is the complete signal bit b2 from the line (12) and the terminal (f1
When 1) is output to the line (l2) at the timing of "High", the signal becomes the completion signal of the bit b1 shown in Table 1. When the terminal (f12) of the mode determination circuit (TIC) becomes “High”, the Q output (α7) of the D flip-flop (DF25) is output from the AND circuit (AG31). This flip-flop (DF2
5) is bit b12, FDC input from line (12)
This signal is a line (l2) at the timing when the terminal (f12) of the mode determination circuit (TIC) becomes “High”.
Is output as the FDC signal of bit b12. While the terminals (f13), (f14) and (f15) of the mode discrimination circuit (TIC) are "High", the line (l2) is "Low" and is a spare bit.

In the CF mode, the terminal (C
F) becomes “High”, the NOR circuit (NO11) outputs a signal of “Low”, the AND circuits (AG2) and (AG1) are disabled, and the transistor is operated according to the signal from the line (l2). (BT53) becomes conductive or non-conductive, and a signal from the line (l2) is output from the output (r21) of the inverter (IN27). When the terminal (CF) becomes “High”, the AND circuit (AG33) becomes active, and the terminal (r2
The signal from 1) is an AND circuit (AG53) and an OR circuit (OR5
1), AND circuit (AG64), (AG65), transistor (B
Output to the line (12) via (T65) and (BT67). Therefore, data from the camera body is output from the line (l2) to the line (12) via the flash controller, and is read into the flash device.

In the ES mode, if the mounting signal is not latched in the D flip-flop (DF19), the output (α3) becomes “Hi”.
gh ", the terminal (ES) becomes“ High ”.
13) The output is “High” and the output of the NOR circuit (NO11) is “Lo”
w ", the transistors (BT55) and (BT57) are in a non-conductive state. If the Q output (α1) of the D flip-flop (DF19) latches the mounting signal, the terminal (ES) becomes“ When the signal goes to "High", the AND circuit (AG23) is in an active state.
31) and output from terminal (r22),
This signal is output from the AND circuit (AG23) and output to the line (l2). Accordingly, the integration control signal synchronized with the light emission output from the flash device to the line (12) is transmitted via the flash controller to the line (l2).
Is output to

In the sequential light emission mode, when the output (α0) of the AND circuit (AG45) becomes “High”, the AND circuit (AG11) is activated. Then, when the X contact (Sx) of the camera body is closed and the line (1) becomes "Low", the transistor (BT59) becomes conductive and the terminal (r1) becomes "High". At this time, since the flip-flop (FF23) is in the reset state, the output of the AND circuit (AG11) is connected to the terminal (r
When 1) becomes “High”, it becomes “High” and the counter (CO11)
Is reset, and the counter (CO11) counts the clock pulse (φ3) from the oscillator (PG).
Then, 6 ms after the X contact (Sx) is closed, the terminal (re) becomes “High” and the flip-flop (FF23)
Is set. And if both flash units are fully charged and the terminal (α2) is “High”, the output of the AND circuit (AG88) becomes “High” and the transistor (BT71) conducts,
The line (l21) becomes "Low". As a result, the flash device (III) shown in FIG. 1 emits light. That is, after the flash device (I) emits light and then (II) emits light for proper exposure, the flash device (III) emits light. When the flip-flop (FF23) is set, the output of the AND circuit (AG11) becomes "Low" and the counter (CO11) is reset. When the X contact (Sx) is closed and the transistor (BT59) becomes non-conductive and the terminal (r1) falls to "Low", the one-shot circuit (OS
17) A pulse is output from the flip-flop (FF23)
Is reset and returns to the initial state.

In the multi-light mode, the flash device is set to bits b8 to b1.
Although the signal of 5 is not output, as described above, the flash controller is “High” if both flash devices are in the full state, and “Low” if at least one of the flash units is in the full state.
Is output as bit (b11) to line (l2). Then, this signal is read as a complete signal by the camera body, but also in the flash device, it is read by the flip-flop (FF2) to determine whether or not to emit light.
In addition, in the flash device directly connected to the flash controller, when it is determined that both are in the full state in the multi-light mode, the output of the AND circuit (AG86) is “Hig”.
h ", and when the terminal (f11) becomes" High ", the outputs of the AND circuit (AG92) and the OR circuit (OR72) become" High ".
This signal is output on line (12) and sends a signal that can emit light to the flash device. On the other hand, if at least one of the flash units is not in the full state, the AND circuit (AG86)
Is "Low", a "Low" signal is output to the line (12), and a signal indicating that light emission is prohibited is sent to the flash device. When the mode is not the multiple light mode, the output of the inverter (IN50) becomes “High”, and when the flash device connected to the controller is in a full state and the terminal (α9) is “High”, the terminal (f11) becomes “High”. When it becomes "", when the output of the AND circuit (Ag90) becomes "High", the output of the AND circuit (AG90) becomes "High". Therefore, this "High" signal is output to the line (12) via the OR circuits (OR72) and (OR51), read by the flash device, and the flash device is enabled to emit light. On the other hand, when the flash device is not in the full state and the D flip-flop (DF23) latches a signal of "Low" and the terminal (α9) is "Low", when the terminal (f11) becomes "High", the line ( At 12), a "Low" signal is output, and the flash device reads this signal and becomes unable to emit light.

The output of the NOR circuit (NO13) is connected to terminals (FC), (CF), (E
When S) is "Low", that is, in the standby mode, it becomes "High". If the flash device is not mounted on the line (12) and the terminal (α13) is “High”,
The output of the AND circuit (AG15) becomes “High” and the NOR circuit (N
The output of O11) becomes “Low” and the transistor (BT5
5) and (BT57) are both non-conductive. On the other hand, if the flash device is mounted on the line (12) side, the terminal (α1) becomes “High” and the AND circuit (AG17) is activated. Then, the completion signal input as bit b2 from the line (12) is latched by the D flip-flop (DF23), and if the terminal (α9) is “High”, the AND circuit (AG17)
Becomes “High” during the standby state. Therefore, the line (1
2) When the flash unit on the side outputs the completion signal, the controller outputs a "High" signal to the line (l2) during the standby state.

Fig. 19 shows the flash control unit (FTC1) of the parent-child strobe (Fig. 11
FIG. The terminal (O1
3) becomes “High” and OR circuit (OR14), (OR16),
(OR12) output becomes “High” and the AND circuit (AN5
2), (AN54) and (AN62) are activated. Therefore,
The signal of the flip-flop (FF17) that has been “High” for 2.5 msec after the X contact (Sx) is closed is output from the AND circuits (AN52) and (AN54) and the OR circuit (OR22)
(OR24) is sent to the light emitting units (FLO1) and (FLO2),
Both light emitting units emit light at the same time. In the automatic light control mode, the light emission stop signal from the terminal (p3) is output by an AND circuit (AN
66) and (AN68), the two light emitting units stop emitting light simultaneously. The light emission stop signal to the FDC display circuit (INF) is a signal of the flip-flop (FF17) which is “High” for 2.5 msec after 3.5 msec elapses from the time when the X contact (Sx) is closed. Is output from the AND circuit (AN62) and OR circuit (OR26). During this time, the emission stop signal input from the terminal (p3) is output to the FDC via the AND circuit (AN70).
It is sent to the display circuit (INF). If the automatic light control mode is not set, the one-shot circuit (OS1
The light emission stop signal from 1) is sent through the AND circuit (AN64) and the OR circuit (OR28), and the light is emitted up to the set light emission amount, but is not transmitted to the light emitting unit (FLO1), and is fully emitted.

In the post-emission mode, the terminal (O12) becomes "High", the OR circuits (OR18) and (OR12) become "High", and the AND circuits (AN58), (AN60) and (AN62) are activated. Therefore, when the flip-flop (FF19) is set, the two light emitting units emit light simultaneously, and during this light emission, both light emission is stopped by the light emission stop signal input to the terminal (p3), and this light emission stop signal is displayed by the FDC display. Sent to the circuit. In the simultaneous light emission mode and the single light emission mode, the terminal (O10) becomes “High”, the OR circuits (OR14) and (OR16) become “High”, and the AND circuits (AN52), (AN54) and (AN56) Becomes active. Therefore, when the flip-flop (FF17) is set, the two light emitting units emit light simultaneously, and the light emission of both light emitting units is stopped based on the light emission stop signal input to the terminal (p3) during light emission, and the FDC display is performed. This light emission stop signal is also input to the circuit (INF).

In the parent-child light emission mode, the terminal (O11) becomes “High”, the outputs of the OR circuits (OR16), (OR18), and (OR12) become “High”, and the AND circuits (AN52), (AN60), (A
N62) becomes active. First, when the flip-flop (FF17) is set, light emission of the light emitting unit (FLO2) starts. During this time, light emission of the light emitting unit (FLO2) is stopped by a light emission stop signal input from the terminal (p3). Next, when the flip-flop (FF19) is set, light emission of the light emitting unit (FLO1) starts, and light emission of the light emitting unit (FLO1) is stopped by a light emission stop signal input during this time. Is FD
Sent to the C display circuit (INF).

In the case of this modification, both light-emitting units emit light simultaneously in modes other than the parent-child light-emitting mode, so that the interlocking range needs to be displayed based on the sum of the light emission amounts of both light-emitting units.

The flash photography system to which the present invention is applied has been described above. Next, a modified example of this system will be described. In multi-flash shooting, when one flash device is in the automatic light control mode and the other is in the manual setting mode, the flash device in the automatic light control mode and the camera body show the FDC display, but the manual setting mode The FDC display is not performed in the flash device. To stop this, the following modified examples are conceivable.

1. When the signals of the sequential light emission mode (“01”, “10”) and the simultaneous light emission mode (“11”) are read with bits b6 and b7,
Set the automatic light control mode even when the manual setting mode is set.
In other words, the manual setting mode is prohibited for multi-light emission.

2. Using bits b4 and b5 that are reserved,
In step 4, the flash device outputs a signal indicating the automatic light control mode or the manual setting mode, and the flash controller reads the signal. The flash controller determines that multiple flashes are being emitted, and determines that only one of the flash units is in the manual setting mode. send. Then, the flash device that has read the prohibition signal enters the automatic light control mode. That is, in the case of multiple light emission, only one of them is prohibited from being in the manual setting mode, and both are permitted to be in the automatic light control mode or the manual setting mode.

3. The flash controller outputs the FDC signal as the bit b15 when the FDC signal is input from both flash devices in the multi-light emission.

Further, it is determined that the camera body (V) has all the "High" signals as the data from the flash, that is, that the conventional flash device having no function compatible with the system of the present embodiment is mounted. Then, the display and exposure control for natural light photography are not performed in the camera body, and the display and exposure control for natural light photography are performed, so that a flash device that is not compatible with this system may not be used.

Or, when the flash unit reads all "High" signals, the camera body fixes the exposure time to 1/60 sec and the aperture value to F5.6, regardless of the mode, and guarantees only the lowest flash photography You may make it.

In addition to this, when the flash unit emits light when it is fully charged, the camera body shifts to the release state, and the terminal (ES) of the mode discrimination circuit (TIC) becomes “Hig”.
At the time of "h", a timing signal for outputting a completion signal and a timing signal for reading are produced by each flash device and controller, and whether or not to emit light based on the completion signal read based on the timing signal is determined. A decision may be made.

In the above embodiment, the power-on reset operation at power-on is omitted for the sake of simplicity of description and drawings, but those skilled in the art can easily add the power-on reset operation.

In the above embodiment, the signal indicating the state of charge of the main capacitor of the flash device is output in a pulsed manner.
If not completed, the present invention can be applied to a flash device that continuously outputs a “Low” signal.

Effects According to the present invention as described above, when all the flash devices connected for multi-flash flash photography are in the charging completed state, each of the flash devices is in a state capable of emitting light, so that other flash devices can emit light. When the device is not fully charged,
It does not happen that a flash device accidentally emits light. Also, in the case of multi-flash photography, if the second terminals of the respective flash units are directly connected to each other, the second terminals of the uncharged flash units have low impedance.
As a whole, the impedance becomes low, that is, “Low”, and each flash device can read the state of charge to determine the charge state of another flash device. Therefore, a special device or circuit for determining the charge state of all flash devices. Is not required.

Also, as in the embodiment, if the charge completion signal is sent in synchronization with the clock pulse from the camera body, only a part of the clock pulse may be used as the charge completion signal, and the remaining clock pulse is It can be used to exchange various data other than the completion signal, and the data exchange can be performed in series.

Also, as in another embodiment, the charge state of the main capacitor is output during a first predetermined time from a release signal input from the camera body, and a light emission control signal is read after a second predetermined time has elapsed. By doing so, control according to the state of charge immediately before the exposure control of the camera is started is performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a flash photographing system to which the present invention is applied, FIG. 2 is a flowchart for explaining the operation of the microcomputer (MC1) in FIG.
FIG. 4 is a flowchart showing a specific example of the flash state display set in step # 38 in FIG. 2, FIG. 4 is a flowchart showing the operation for the steady light calculation I in step # 41 in FIG. 2, and FIG. Step # in Figure 2
FIG. 6 is a flow chart showing the operation for the flash light calculation of 42, FIG. 6 is a flow chart showing the operation of the steady light calculation II and the flash light calculation II in steps # 43 and # 44 in FIG. 2, and FIG. Input / output controller (IOC)
FIG. 8 is a circuit diagram showing a specific example of the light emission amount control circuit (FST) in FIG. 1, and FIG. 9 is a control circuit (FST) in the flash device (I) in FIG. FL
C1) is a circuit diagram showing a specific example, FIG. 10 is a circuit diagram showing a specific example of the mode discrimination circuit (TIC) in FIG. 9, and FIG. 11 is a specific example of the light emission control circuit (FTC) in FIG. 12, FIG. 12 is a circuit diagram showing a specific example of the dimming completion display circuit (INF) in FIG. 9, and FIGS. 13 and 14 explain the operation of the microcomputer (MC2) in FIG. Flowchart for the fifteenth
The figure is a circuit diagram showing a specific example of a main part of the control circuits (FLC2) and (FLC3) in the flash units (II) and (III) in FIG. 1, and FIG. 16 is a light emission control circuit (FTC2) in FIG. FIG. 17 is a circuit diagram showing a specific example of a main part of the microcomputer (MC) of FIG.
FIG. 18 is a flowchart showing a main part of the operation of 3), and FIG.
FIG. 19 is a circuit diagram showing a specific example of an internal circuit (CNC) of the flash controller shown in FIG. 19, and FIG. 19 is a circuit diagram showing a modification of the light emission control unit (FTC1) of the parent-child strobe (I). V: Camera body, I, II, III: Flash device, IV: Flash controller, LM: Photometry circuit, FST: Flash emission control circuit, IOC: I / O control circuit, FLC1, FLC2, FLC3: Control circuit, FLO1, FLO2 , FLO3, FLO4: Light emitting unit, C1, C2, C3,
C4: Main capacitor, CHD1, CHD2, CHD3, CHD4: Charge completion detection circuit, MC1, MC2, MC3: Microcomputer, 1: Synchro switch closing signal transmission line, l2: Data transfer line, l3: Clock pulse transmission line, l4: ground line, TIC: mode discrimination circuit,

Continuing on the front page (72) Inventor Takanobu Ohmaki 2-30 Azuchicho, Higashi-ku, Osaka City International Building Minolta Camera Co., Ltd. JP-A-56-168643 (JP, A) JP-A-58-105139 (JP, A) JP-A-55-124123 (JP, A) JP-A-56-149800 (JP, A) JP, U)

Claims (6)

(57) [Claims] A flash device used in a flash photographing system in which a plurality of flash devices can be connected to a camera. The flash device is charged by an output of a booster circuit and stores light emission energy of a flash light emitting unit. A capacitor; a light emission start signal input means for inputting a light emission start signal from the camera; and determining whether the main capacitor has been charged to a predetermined level at which the flash light emission unit can emit light with a predetermined light amount or more, based on the result. A discriminating means for outputting a discriminating signal, and an input from a camera based on the discriminating signal from the connected flash device to indicate whether the main capacitors of all the flash devices have been charged or have not been completely charged. Reading means for reading a light emission control signal to be read, and the reading means If the flash device has read a light emission control signal indicating that charging has been completed, it issues a light emission instruction to the flash light emitting unit based on the light emission start signal, and reads a light emission control signal indicating that there is an incomplete one. A flash control unit that does not issue a flash instruction even when a flash start signal is input. 2. A first method for inputting a light emission start signal from a camera.
A second terminal for inputting a clock pulse from the camera; and the determination means outputs the determination signal to the camera during a period from a rise of a predetermined clock pulse to a rise of the next clock. 3. The flash device according to claim 1, further comprising: a third terminal for reading the light emission control signal from the camera at a falling timing of a predetermined clock pulse. 3. A first method for inputting a light emission start signal from a camera.
A second terminal for inputting a release signal from the camera indicating that the exposure control operation is to be started; And a third terminal for reading the light emission control signal after a lapse of a second predetermined time shorter than the first predetermined time since the input of the release signal. The flash device according to claim 1, wherein: 4. A flash device system capable of using a plurality of flash devices connected to a camera, wherein the flash device is charged by an output of a booster circuit and stores a main capacitor for storing light emission energy of a flash light emitting unit. A light emission start signal input means for inputting a light emission start signal from the camera; and determining whether the main capacitor has been charged to a predetermined level at which the flash light emitting unit can emit light with a predetermined light amount or more, and determining based on the result. Based on the discriminating means for outputting a signal and the discriminating signal from the connected flash device, a signal is inputted from the camera to indicate whether the main capacitors of all the flash devices have been charged or not. Reading means for reading the light emission control signal, and the reading means When a flash control signal indicating that charging has been completed is read, a flash command is issued to the flash light emitting unit based on the flash start signal, and when a flash control signal indicating that there is an uncompleted flash is read, the flash starts. A light emission control unit that does not issue a light emission instruction even when a signal is input; a camera; a second reading unit that reads a discrimination signal output from the discrimination unit of the flash device; Based on the discrimination signal, it is determined whether all of the connected flash devices are fully charged or uncompleted, and a flash control signal is sent to the flash device to indicate the determination result. A second determining means for outputting, and a flash shooting mode when the second determining means determines that all the flash devices have been charged. ,
And a mode selecting means for selecting a camera mode to a natural light photographing mode when it is determined that there is an unfinished one. 5. A flash device comprising: a first terminal for inputting a light emission start signal from a camera; a second terminal for inputting a clock pulse from the camera; A third terminal that outputs the determination signal to the camera during the rising of the next clock, and further reads the light emission control signal from the camera at the falling timing of a predetermined clock pulse; 5. The flash photographing system according to claim 4, further comprising: 6. A flash device comprising: a first terminal for inputting a light emission start signal from a camera; a second terminal for inputting a release signal from the camera indicating that an exposure control operation is started; When the release means receives the release signal, the determination means outputs the determination signal to the camera for a first predetermined time, and further, the reading means outputs a second predetermined time shorter than the first predetermined time after the release signal is input. The flash photographing system according to claim 4, further comprising: a third terminal for reading a light emission control signal after a lapse of time.