JPS60192930A - Indicator for electronic flashgun - Google Patents

Abstract

PURPOSE:To prevent confusion of indication when two flashes are used and to visually recognize the order of emission of light by detecting the mode selection of consecutive light emission and earlier light emission, and prohibiting the operation of an interlocking range indicating means. CONSTITUTION:Time series input signals from a line l2 are latched in D-type FFDF3, DF5 by a mode discriminating circuit TIC, and latched data are sent to input terminals i11, i12 of a microcomputer MC2. Consequently, one of light emission modes; simultaneous, ealier light emission, later light emission, one light, is selected. When earlier light emission mode is selected, indication FDP1 of the range of interlocking and the range of photographing is not executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Application The present invention relates to an electronic flash light emitting device used in a flash photography system that performs flash photography by sequentially emitting light from two electronic flash light emitting devices (hereinafter referred to as flash devices). In particular, there is provided an automatic light emission amount control means that stops the light emission when the integral value of the reflected light from the subject reaches a predetermined value, an aperture value for photographing,
Displays the subject distance range (hereinafter referred to as the interlocking range) that is determined based on data on film sensitivity and flash device maximum flash output or set flash output, and that allows the subject to be illuminated with an amount of light that provides an appropriate exposure. The present invention relates to a flash device that automatically controls light emission amount and is equipped with a display means.

I'm confused! 1 (Change the light emitting directions of the two light emitting parts so that the subject is illuminated from different directions, emit light from both the light emitting parts simultaneously or sequentially, and set both light emitting parts so that the sum of the amounts of light irradiated by both light emitting parts becomes the appropriate exposure. 2. Description of the Related Art Flash photography systems that control the amount of light emitted from each light emitting section are known.

In particular, when both light emitting parts are emitted sequentially at different timings, the amount of light irradiated to the subject by each light emitting part (i.e., the sum of the light emitting amounts of both light emitting parts gives the appropriate exposure) is greater than when the light emitting parts are emitted at the same time. As a result, each light emitting unit can independently control the light emission (light emission control), and the desired lighting effect can be obtained. A display device capable of displaying the interlocking range in such a sequential flash photography system has not been proposed in the past.

Now, many flash devices have been known that automatically control the light emission amount of a single light emitting part and also display the interlocking range. However, in this case, the following disadvantages may occur.

First, depending on the maximum light emission m of the light emitting section of each device, the set light emission amount, and the above-mentioned irradiation light amount ratio, the amount of light emitted is substantially increased (i.e., each light emitting section is set to 1/3 or 2 of the amount of light that provides proper exposure.
/3, so the amount of light emitted by each light emitting part is apparently 3 times or 3/2 times that when used alone), and the calculated interlocking range is displayed independently. So the maximum of each light emitting part.

When the setting and apparent flash output are different from each other, two types of interlocking ranges are displayed, and the photographer is informed that if the interlocking display is based on the substantially increased flash output, the flash output will match the flash output ratio. If control cannot be performed, the displayed value cannot be said to be correct.

In other words, if the light emitting part that emits the first light does not emit the full amount of light but cannot obtain the amount of irradiation light according to the light amount ratio, if the light emitting part that emits the second light emits an extra amount of light to compensate for the shortage, the desired illumination can be achieved. The effect is not compromised, but proper exposure is guaranteed. However, in this case, the actual farthest distance in the interlocking range is shorter than the farthest distance in the interlocking range displayed by the device that emits light afterward by a value corresponding to the insufficient amount of irradiation light. Furthermore, even if the subject is outside the interlocking range displayed by the device that flashes first, the light emitting section of the second flasher will provide proper exposure, so there is little need to display the interlocking range with the device that flashes first. do not have.

In addition, if the photographer forgets the order in which the flash device fires first, for example, the photographer will not know the order until he or she actually takes the picture, and the film and flash energy will be wasted. become.

The present invention provides a convenient and error-free combination when sequentially controlling the light emission of two flash devices! The aim is to provide a display device that can display the surrounding area.

To solve the problem, the present invention provides means for detecting whether or not a sequential light emitting mode in which light is emitted one after another in cooperation with other electronic flash devices is selected in an electronic flash light emitting device equipped with a light emission amount control means. and a means for detecting whether or not a preflash state is selected in which the electronic flash device emits light before the light emission of the other electronic flash device, and a display means for displaying an interlocking range based on the maximum light emission period of the electronic flash device itself or a set light emission amount; It is characterized by comprising a display control means that prohibits the display operation of the display means when the sequential light emission mode and the first light state are selected, and permits the display operation at other times, based on the detection outputs of both the detection means. shall be.

艷1 According to the present invention, the display control means prohibits the display operation of the display means only when the sequential light emission mode and the first light state are selected, and the display control means prohibits the display operation of the display means only when the sequential light emission mode and the first light state are selected. When the simultaneous flash mode in which the flash devices of the present invention emit light at the same time or the single light flash mode in which the flash device of the present invention emits light independently is selected, the display operation of the display means is permitted, so the sequential flash mode is selected. In this case, only the flash device in the post-emission state displays the continuous range.

Embodiment FIG. 1 is a block diagram showing the overall configuration of a flash photography system to which the present invention is applied. In this figure and the following circuit diagrams and block diagrams, thick lines indicate multiple signal lines, and thin lines indicate one signal line.

(V) is a lens interchange model-eye reflex camera body, and this camera body has a connector (CN9) for electrically connecting to a flash device.

(CN3) is provided. Connector (CN9)
is provided on a hot shoe (not shown) on the top of the camera, and when an electronic flash device (hereinafter referred to as a flash device) is attached to the camera via the hot shoe, it is directly electrically connected to the circuit of the flash device. . Connector (CN3
') is provided at the bottom of the camera and is electrically connected to the flash device via the flash controller (ff) described later; the flash device is not directly electrically connected to the camera via the connector (CN3). . Furthermore, the camera body (V) is provided with a connector (CNI>), and this connector (CN1) is provided at a position, such as the seat plate of the lens mount 1~, to which the interchangeable lens is attached. (When l is attached to the camera, it is connected to the connector (CN2) of the interchangeable lens (Vl), and various data from the lens circuit (LEG) is transmitted to the camera body (
V).

(ff) is a flash controller that controls a flash device connected to it, and is electrically connected to a connector (CN3) at the bottom of the camera body via a connector (CN4). The flash controller (ff) also has a connector (CN5).

(CN7') is provided, and a connector (CN5') is provided.
) has four electrical terminals, and the connector (CN7) has two electrical terminals. And the connector (CN5
) The flash device connected to the connector (CN7) exchanges signals for data and light emission control between the flash controller 1 and the roller (■), and the flash device connected to the connector (CN7) Only a light emission start signal is transmitted from the controller (ff).

(1”) is a two-lamp type flash device, and in the example shown in Figure 1, the connector (CN5) is connected to the flash controller (N).
), (CN6). (1) is a one-lamp type flash device, which is electrically connected via a connector (CN9) provided on the hot shoe of the camera body (V) and a connector (CN10). (
I) is a single flash device with the same configuration as flash device @(■), and in this example, the flash controller (
ff) via connectors (CN7) and (CN8).

Figure 1 shows the camera body (V), flash controller (IV), and flash devices (1), (I[), (■)
This figure shows an example of how to connect the flash units (1) and (1), by switching the connection positions of the flash units (1) and (1),
If you do not install the flash device (1) or install the flash device only at the hot shoe position, i! (1) or (1)
), or attach the flash controller (■) to the camera body (V), and connect the connector (C
Flash device 1) or (l[
), or install either flash [1 (1) or (1)] at the hot shoe position,
A flash device may not be attached to the flash comma roller (ff) attached to the camera body (V). Furthermore, the flash control D′-ra (ff
) and attach the flash unit N (1) or (1) to the connector (CNI) position.Furthermore, it is also possible to attach only the flash controller (IV) to the camera body (V) and attach the flash unit to the connector (CNI). You can also operate the camera without installing it anywhere. Please note that only the flash controller (NV) is connected to the camera body (V).
When attached to the camera, flash photography is not performed, but constant light photography is performed. In addition, the hot shoe of the camera body (V) and the connector of the flash controller (■) (
If a general-purpose flash device or a non-dedicated flash device that does not have the 4161 necessary for the system of this invention is installed in the position of CN5), flash photography according to this invention will not be performed at all, and the installed general-purpose flash device Or a non-dedicated flash device will only emit light. Also, the connector (C:N7) of the flash controller (ff)
The flash photography according to the present invention can be performed using a flash device mounted at the position of , whether it is a dedicated flash device, a general-purpose flash device, or a non-special flash device.

Next, the inside of the camera body (V) will be explained.

(BAl) is a power supply battery, and (MSI) is a main switch. (Sl) is a photometry switch that is opened when the release button (not shown) is pressed in the first step, and (Sl) is a release switch that is opened in the second step when the release button (not shown) is pressed. The closing signal of (Sl) is transmitted by a microcomputer (hereinafter referred to as microcomputer) (MCI).
) is input to the interrupt terminal (it) and input terminal (11), and the close signal of the release switch (Sl) is input to the same microcomputer (MC).
1) Input to input terminal (12). ($4) is opened when the exposure control operation is completed, and the shutter mechanism and aperture III
This is a reset switch that is opened when the charging of the exposure control device III (not shown) such as
> input terminal (i3). (Do) is a circuit that outputs data corresponding to setting values such as exposure control mode film sensitivity, exposure time, aperture value, etc., and outputs such setting data to the input terminal (IPl) of the microcomputer (MCI). A signal is being input. The film sensitivity value is set by automatically reading the film sensitivity data marked on the film container (not shown) instead of manually setting it.
This may be done in the form of setting data. (LM) is a photometric circuit, and the output of the photometric circuit (LM) is output from the microcontroller (
Analog input terminal (AN
The output of the reference voltage II (not shown) provided in the photometric circuit (LM) is input to A- of the microcomputer (MC1).
There is a shortage of input to the D conversion reference voltage input terminal (VRI).

(AF) is an automatic focus adjustment circuit that detects the focus adjustment state of the photographic lens and drives the photographic lens to the in-focus position. This automatic focus adjustment circuit (AF) is operated by a microcomputer (MC).
It operates in response to commands transmitted from I) through the data bus (DB), and detects the direction and amount of deviation of the subject image formed by the photographic lens from the intended focal plane.

Then, the detected deviation amount data and the interchangeable lens (Vl)
Based on the data from Displays the focal point mvx state of the photographic lens. (RL) is a release circuit for starting the operation of the exposure control m mechanism, and is a terminal of the microcomputer (MCI) (
It operates with the 'High' signal from 02).(DP
) is a display circuit that displays exposure control values (scheduled aperture value, exposure time value, etc. to be controlled), exposure control mode, film sensitivity, flash device status, etc. This display circuit (D P ) is connected to the output terminal (
The display is performed based on the data from OF2'').

(FCC) is a circuit for exposure control, and the output terminal (OP
The shutter and aperture aperture are controlled based on the data on the exposure time and the number of aperture steps from I).

The transistor (BTI) is a power supply transistor, and when the terminal (01) of the microcomputer CMG1) becomes High, the transistor (BTI) is connected via the inverter (INI).
BTl) is brought into conduction, and power is supplied via the power supply line (+■).

From this line (+V), the circuit (LM), (AI=) (
FCC), (RL), (FST) and lens circuit (LE
C) is supplied with power.

The switch (Sx) is a synchro switch that closes when the shutter front curtain completes running, and the signal from this synchro switch (Sx) is transmitted via the line (Fuki 1) to the flash device [(1), flash controller (■ ), transmitted to the flash unit @ (summer). (FST) is a light emitting device that controls the amount of light emitted by the flash device! This is a sub-m circuit, and a specific example thereof is shown in FIG. (10G> is an input/output controller that controls the transmission and reception of signals between the camera body (V), the interchangeable lens (■), the flash device f (1), and the flash controller (mV). It is shown in the figure.

The terminal (CKO) of the microcomputer (MCI) outputs a clock pulse from inside the microcomputer, and this pulse (φ1
) is an automatic focus adjustment circuit (AF), a setting data output circuit (Do), an exposure control circuit (FCC), and a display circuit (D
P) and the release circuit (RL) as their reference clock. Microcomputer (MCI) terminal (ANO)
> outputs a signal obtained by D-A converting the film sensitivity for controlling the amount of light emitted by the flash device. Terminal (SCK).

(SOLI) and (SIN) are terminals for serial input/output of data, and when there is a command for serial input/output, eight clock pulses are output from the terminal (SCK), and the rising edge of this clock pulse The microcomputer (MCI >
Data is transferred one bit at a time from the input/output register in the terminal (S
The data sent to the terminal (SIN) is sequentially fetched into the input/output register in synchronization with the falling edge of the clock pulse from the terminal (SCK). (03)
is used when exchanging data with the interchangeable lens (Vl).
(04) is a terminal that becomes “@igh” when exchanging data with either or both of the flash device and flash controller, (05)
is a terminal that transmits a signal indicating the operating status of the camera to the flash V41F and the flash controller, and when data from either or both of the flash device and flash controller is taken into the camera body, it is necessary to wait for a predetermined period T1 (for example, 90μsea). (duration) “')light”
pulse for a predetermined period T2 (for example, 150 μs) when outputting data from the camera body to the flash device and/or flash controller
When the camera body starts the exposure control operation, it outputs a "High" pulse for a predetermined period T3 (for example, 210 μsec). Further, the terminal (06) is a terminal that becomes 1-1i9hn when either or both of data is transferred from the camera body to the flash device and flash controller.

(LEG) is a circuit provided in the interchangeable lens (Vl), and is supplied with power from the ii source Klein +■) of the camera body. And the terminal (03) of the microcomputer (MCI) is “d”
When Hl a i +t, the line (Ll) becomes l-
1-1i'' and the lens internal circuit becomes operational.Then, based on the O-clock pulse sent from line (L2), the data fixedly stored in the lens internal circuit (LEC) is sequentially transferred to line (L3) in series. The fixedly stored data includes open aperture value, maximum aperture value, focal length, shooting distance, various data for automatic focus adjustment, and for checking (if an interchangeable lens compatible with the system of this embodiment is available). There is data for confirming whether or not the interchangeable lens is attached, and whether or not such an interchangeable lens is reliably attached.

(No. 1) is a signal line to which the closing signal of the synchro switch (SX) is transmitted as described above. i2) When exchanging data between the camera body and either or both of the flash controller and flash device, serial data from either or both of the flash device and flash controller and serial data from the camera body are transmitted. It functions as a bidirectional data bus.

When the flash device emits light, the flash device outputs a “LOW” signal for a certain period of time II (for example, 2.5 ssec, which is longer than the time required for the flash device to fully emit light), and then outputs a “LOW” signal for a certain period of time (for example, 2.5 ssec). 11SflO)
The signal ") light" is output, and then a certain period of time (for example, 5.5-
sec) A signal of "L 01" is output.

When the flash device is in a fully charged state, a signal of "High" is output, and a signal of "Low" is output if the flash device is not in a fully charged state, except when transmitting/receiving data or emitting light.

In addition, “LOW”, “Higl+”, “1ow” when emitting light
As will be described later, the signal `` is a signal for controlling the amount of light emitted.The line (α3) is a synchronization signal from the terminal (SCK) for exchanging data between the camera body, flash device, and flash controller. A clock pulse for the camera body is output from the camera body.A signal indicating the operating state of the camera body from the terminal (05) is also output from the line (α3).Furthermore, while the flash device is emitting light, the light emission amount control circuit (F A light emission stop signal is output from S, T).

Next, the inside of the flash device (1) will be explained.

(BA3) is a power supply battery, and (MS3) is a main switch. (FLCl) is a control circuit,
It has functions such as data exchange, display calculations, and light emission control, and the specific internal configuration is shown in Figures 9, 10, and 11.
This will be explained later based on FIGS. 12, 13, and 14. (FDPl) refers to the light emission mode (parent-child light emission, sequential light emission) described later (first light emission or second light emission, simultaneous light emission,
Displays whether the flash is in bounce mode or not, Displays the data sent from the camera body (displays the aperture, film sensitivity, and focal length, and sets the flash coverage angle when the flash coverage angle is variable) display, as well as aperture value and film sensitivity data sent from the camera body, and light emission m.
Based on the data, the interlocking range (
Auto-adjustable shooting distance range) can be manually set.
Mode in which the light is emitted for 1 minute (manual setting mode shown below)
In this case, the shooting distance that provides the appropriate exposure is displayed. (CH
Cl) is the charging completion detection circuit (CHol), (CHD2
) is a boost control circuit that controls the operation of the 1-transistor (ST2) and the boost circuit (CDI) according to signals from the 1-transistor (ST2) and the boost circuit (CDI).

The booster circuit (DDl) operates when the transistor (ST2) becomes conductive and changes the voltage of the power supply (BA3) to the required voltage (
For example, the voltage is boosted to 300V), and this output is passed through a diode (Dl) to a capacitor (C1).
The capacitor (C2) is charged through the capacitor (C2). Then, the charging completion detection circuit (C1-IDI>, (CHD
2), when the capacitors (C1) and (C2) are charged to a voltage that can compensate for the maximum amount of light emitted by the flash device, a signal of 'l-1iQh'' (hereinafter this signal will be referred to as the full charge signal) is generated. Output. Boost control circuit (CHCI)
) are both detection circuits (CHDI), (CHD2
), the transistor (ST2
) is deactivated to stop the operation of the booster circuit (CDI), and if a fullness signal is not output from at least one of the detection circuits, the transistor (ST2) is made conductive to operate the booster circuit (DDl>).

CF-LOI) and (PuO2) are each light emitting parts,
Signal (ST1) from control circuit (FICl)
), (SPI), (ST2), and (SF3') control the light emission. The light emitting part (PuO2) has a variable irradiation direction. When only this flash device fil (1) is connected to the camera body (V) directly or via a flash controller (ff), if the light emitting part (PuO2) faces the front, (hereinafter referred to as front light state), this light emitting part (PuO2
) only emits light, and if the winding part (PuO2) is facing in a direction other than the front (hereinafter referred to as bounce state), the light emitting part (PuO2) will first emit light for about 2/3 of the proper exposure, and then The light emitting section (FLO1) emits light by approximately 1/3 of the proper exposure (hereinafter, such a light emitting mode will be referred to as parent-child light emitting mode). On the other hand, as shown in Figure 1, the camera body (V)
If two or more flash devices are electrically connected, including this flash support I (1), the light emitting part (
Whether PuO2) is in the front light state or in the bounce state, only the light emitting part (PuO2) emits light, and (FLOl'
) does not emit light. Light emitting part (FLOI).

(PuO2) has terminals (ST1) and (ST2).
The light starts to emit light when it reaches ``H+gh''.Also,
Since the capacitance of the capacitor (C1) is very small compared to the capacitance of the capacitor (C2), the light emitting part (F
The maximum light emission amount of the light emitting section (PuO2") is very small compared to the maximum light emission amount of the light emitting section (PuO2"). Therefore, while the maximum light emission amount of the light emitting section (PuO2) is, for example, 40 as a guide number, The maximum light emission amount of (FLOl) is, for example, 8 in terms of guide number.Furthermore, the illumination angle of the light emitting part (PuO2) is variable, whereas the illumination angle of the light emitting part (FLOI) is fixed. The terminals (SPI) and (SF3) are terminals for stopping light emission, and when the signal ")lilJh" is output from the terminal (SPI), the light emission of the light-emitting part (FLOl) stops and the terminal ( When a "Hi (Jh") signal is output from SF3), the light emitting section (PuO2) stops emitting light.

Next, the flash device [(I) will be explained.

(BA5) is a power supply battery, and (MS5) is a main switch. (PuO3) is a control circuit that has the same function as the control circuit (FLCl) of the flash device M(1), and it transfers display data to the display unit (FDP3).
), and the light emitting part (PuO4) is sent to the terminal (ST
4) A light emission start signal is output from the terminal (SF3), and a light emission stop signal is output from the terminal (SF3). A specific example of this control circuit (PuO3) will be explained later based on FIGS. 15, 16, and 17.

The boost control circuit (CHC3) is the detection circuit (CHD4)
Transistor (BT4) according to the fullness signal from
Controls activation and inactivation of the booster circuit (DD3). The light emitting unit (PuO4) can be switched between a front light state and a bounce state, and the irradiation angle is also variable. The flash device (it) has the same configuration as the flash device (I).

Next, the flash controller (IV) will be explained. (BA2) is a power supply battery, and (MS2) is a main switch. (CNC) is a processing circuit, which controls whether the flash is installed or not based on the clock pulse from the camera body (V). Read the data from (1) and (1) to determine the attachment state of the flash device and the internal state of the flash device, determine the flash mode, and send the flash mode signal to the flash based on the clock pulse from the camera. Send to device. Then, based on the clock pulse from the camera body, a signal indicating the light emission mode and the status of the flash device is sent to the camera. Furthermore, it is determined whether or not to cause the flash device l1 to emit light according to the result of discrimination of the light emission mode, and when the flash device l1 is to be caused to emit light (sequential light emission mode), a light emission start signal is output to the terminal (921) after the two flash devices have emitted light. .

A specific example of this processing circuit (CNC) is shown in FIG.

Next, various combinations of light emission modes will be explained. If only the flash device (I) is connected to the camera body directly via the hot shoe or via the flash controller (■), and the light emitting unit (PuO2) is in the front light state, only the light emitting unit 1FLO2) emits light 1
The lamp light emission mode is entered, and the interlocking range is displayed based on the maximum light emission amount of the light emitting unit (PuO2). In addition, the light emitting part (Pu
If O2> is in a bounce state, the light emitting part (PuO2) emits light for 2/3 of the proper exposure, and then the light emitting part (FLOl)
is a parent-child light emission mode in which light is emitted by 1/3 of the proper exposure, and the interlocking range is displayed based on the maximum light emission m of the light emitting unit (FLOl).

When only the flash unit [(II) is electrically connected to the camera body (V) via the hot shoe or flash controller, the light emitting unit (PuO4) will not operate until the proper exposure is reached in both front light and bounce conditions. (PuO4
) becomes the single-lamp emission mode. In this case, if the light emitting unit (PuO4) is in the bounce state, the interlocking range is not displayed, and if the light emitting unit (PuO4) is in the front light state, the interlocking range is displayed based on the maximum light emission amount of the light emitting unit (PuO4).

Next, we will explain the case where a flash device is attached to the hot shoe and the flash controller.In this case, if one or both flash devices are of type (1), the light emitting part (PuO2) is in a bounce state. Even so,
Even in the front light condition, the light emitting part (FLOI) does not emit light, and only the (PuO2) emits light.When the flash controller (ff) selects the simultaneous mode, the two flash devices emit light at the same time. The light emission stops as soon as the combined light output of both reaches the appropriate exposure.In this case, the interlocking range is displayed based on the maximum light output of each light emitting part, and if the light emitting part is in a bounce state, the flash will stop. When the flash controller (N) selects the sequential flash mode, the flash device mounted on the flash controller (ff) first emits 2/3 of the proper exposure, then the camera body The flash device that is placed on the hot shoe (V) emits only 1/3 of the proper light.The interlocking range at this time is not displayed for the flash device that fires first, but for the flash device that fires later. The interlocking range based on the maximum light emission amount of the flash device is displayed.

Further, as shown in the figure, when a flash device is attached to each of the hot shoe and the flash controller, and a flash device is attached to the connector <CN7) of the flash controller, the following light emission mode occurs. When the flash controller (mV) selects the simultaneous mode, the light emission start signal is not output from the terminal (A21) and the flash Ii@(II) does not emit light. When the flash controller (IV) sequential flash mode is selected, two flash devices 1 (I[), (1
) sequentially emit light, a light emission start signal is outputted from the terminal (21), and the flash device (II) emits light. Since the flash device 1 (1) only connects the ground line (α4) and transmits the flash start signal, the signal from the flash control circuit (FST) on the camera side is not transmitted, and manual settings are required. The light is emitted at the specified light amount, or in the automatic light control mode, the entire light is emitted. Note that since this flash device only inputs a light emission start signal, it does not need to be a dedicated flash device, and may be a general-purpose flash device. In addition, this 31st flash device (Il[) can be set to illuminate only the background, for example, and even if two flashes are fired in succession to illuminate the main subject, the main subject can be photographed in the background. Unnatural shadows can be removed. This third flash device (M) is connected to the first and second flash devices (1), (■
) The light is emitted after the proper exposure is achieved by the light emission of the two lights, and the amount of light emitted is not controlled by the camera, so it is not desirable to illuminate the main subject, and it is not desirable to illuminate the main subject. Just do it.

Next, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7
8, the operation of the camera body (V) and the operation of the entire system shown in FIG. 1 will be explained. FIG. 2 is a flowchart for explaining the operation of the microcomputer (MC1) shown in FIG. The following explanation will focus on this flowchart. The main switch (MSl) of the camera body (V)
) is opened, power supply to the microcomputer (MCI) starts, and the microcomputer (MCI) starts the operation at the start of power supply. First, in step #1, connect the output terminals (01) to (06)
is set to "LOW" and then outputs data to erase the display on the display unit (DP). Then, in step #3, data for operating the automatic focus adjustment circuit (AF) is not sent from the data bus (DB), and in step #4, an interrupt signal to the interrupt terminal (it) is accepted. In this state, the microcomputer (MCI) stops operating.

When the photometry switch (Sl) is closed, the interrupt terminal (it)
A 'Low' interrupt signal is input to the microcomputer (MC).
I) starts the operation and performs the operation from step #10. In step #10, set the terminal (ol) to “High”
The transistor (BTl) is made conductive via the inverter (INI) as ll'', and power is supplied from the power supply line (+■) to supply power to circuits other than the microcomputer (MCI) and to the lens circuit (LEC). Let's do it. #11
In step , the terminal (03) is set to "high" and reading of data from the lens circuit (LEC) is started.

First, the contents of the register BR in the microcomputer (MCI) (hereinafter, registers, flags, etc. indicated by symbols without parentheses are set in the microcomputer by the program) are set as O", and # In step 13, an operation is performed using the serial input/output command.This causes the data from the lens (LEG) to be read into the serial input/output register IOR.The contents of this register IOR are taken into the specified register, and 1°' to the contents of BR
is added, and it is determined whether the contents of register BR have become "N". If it has not become "N", then #1
Returning to step #3, the next lens data is read, and if it is "N", the process moves to step #11.

Here, reading of lens data will be explained based on FIGS. 1 and 7. Note that Figure 7 shows the input/output l of Figure 1.
This is a specific example of a control circuit (10G).

The terminal (03) of the microcomputer (MCI) is “High”
When this happens, the AND circuits (ANl >, (AN3) become active, and the lens circuit (LEC) is also given the ')high' signal through the line (Ll), making it possible to operate. When eight clock pulses are output from the terminal (SCK) of (MCI), these clock pulses are sent to the lens circuit (L, EC) via the AND circuit (AN3) and line (L2). The lens circuit (LEC) sequentially outputs the first data to the line (L3) in synchronization with the rise of this clock pulse.This data is sent to the microcomputer via the AND circuit (ANl) and the OR circuit (OR1). (M
CI) is input to the terminal (SIN).

This data is sequentially read into the register 10Rk in synchronization with the falling edge of the clock pulse output from the terminal (SCK).

The lens circuit (LEG) is equipped with a ROM that fixedly stores a plurality of pieces of data in a determined order, an addressing means for sequentially specifying the address of this ROM, and a data output means for sequentially outputting data from the ROM in series. ing. The address designating means sequentially updates the address data every time 8 a-to-a pulses are input from the line (L2), and outputs the data in the order of the determined data type. Then, the microcomputer (MCI) sets data in the registers determined in the order of the input data, so one register contains data for the open aperture value, another register contains data for the maximum aperture value, etc. A determined type of data is set in each register. That is, the contents of a fixed register in the microcomputer (MCI) are fixed types of data for the attached interchangeable lens. Among the lens data, in the case of data that changes according to changes in the focal length of the zoom lens, or data that changes according to the shooting distance of 111 ft (lens feeder), data that changes according to the setting position of the zoom ring and distance ring. A code board is provided to output the
The address can be specified by a combination of this code plate and data obtained by counting clock pulses from the camera body.

In step #17, the terminal (03) is set to '1 ow' to stop data input from the lens circuit (LEC), and then it is determined whether the flag JFI is set to '1'. This flag J1:1 is ``1'' if the calculation of exposure control data has been completed, and 0'' if it has not been completed.If JFl is 0'', the calculation has been completed. Since there is not, move on to step #25. On the other hand, if the calculation has been completed, the release switch (S
2) is closed and the input terminal (12) is "LOW". And the terminal (12) is '
If the terminal (12) is not set to LOWWII, then the release switch (S2) is open.
Next, in step #20, it is determined whether the reset switch (S4) is opened and the input terminal (i3) is set to '(ow').At this time, charging of the exposure control mechanism is not completed and the switch ( S4) is opened and the terminal (i
If 3) is "old Qh", proceed to step #25. On the other hand, the charging of the exposure control m mechanism is completed and the switch (
s4) is opened and the terminal (i3) is "Low", the exposure tIIJ control operation from step #8o is performed.

In step #25, it is determined whether check data is input among the data taken in from the lens. This check data is stored in the specified ROM address as data common to all interchangeable lenses (for example, '101
01010") is stored and indicates this data. If this data is not input, it means that the lens is not attached, and if it is input, it means that it is attached. The lens is attached. If so, among the data captured from the lens in step #26, data related to automatic focus adjustment is sent to the automatic focus adjustment circuit (AF') via the data bus (DB), and this circuit (AF)
The operation proceeds to step #27. On the other hand, if there is no check data, the lens is not attached and the automatic focus adjustment circuit (AF) remains inactive.#
Proceed to step 27.

#27 (Connect @ terminal (04) to D Stella raft °' I-1
The flash is set to a state in which data can be exchanged with the flash [i and the flash controller.
This signal is the line (A3).

(α13) to the flash device and flash controller I roller. Then, the flash device and flash controller determine that the mode is for transmitting data from the flash Hffi and flash controller to the camera body (hereinafter referred to as FC mode). Then, in the operation based on the serial input/output command, eight clock pulses are first sent from the camera to the lines (QJ3), (
13) to the flash device, the flash device outputs 6-bit data via lines (92) and (α12) in synchronization with the rise of this clock pulse, and this data is The data is captured by the flash controller I-roller in synchronization with the falling edge of the clock pulse. Then, the flash controller determines the flash mode according to the read data and the flash mode set in the flash controller at that time (sequential flash mode, simultaneous flash mode), and outputs 2-bit data according to this result. The signals are output via lines (92) and (912) in synchronization with the rising edge of the clock pulse.

At this time, the microcomputer (MCI > is the input/output register IO
H, the data currently being output to the line (α2) is taken in in synchronization with the falling edge of the clock pulse, but the microcomputer (MCI) does not use this signal.

Next, in step #30, the serial input/output command is executed again to line (A3).

Eight clock pulses are output to (α13).

At this time, if a flash device is attached via the flash controller and a flash device is also attached to the hot shoe, the flash device will be connected to the line (A2).
, do not output data to (α12), line 12)
, (12) in an open state so as not to affect signal transmission, and the flash controller sends data determined by the data previously read from the two flash devices and the set emission mode to the clock pulse. Output from the flash controller in synchronization with the rising edge. Also, if a flash device is attached via a flash controller and a flash IA@ is not attached to the hot shoe, the flash controller will transfer the data read from the flash device to the line (α
2) Output. At this time, the flash device similarly outputs data to the line (fL12), but this data is blocked by the flash coat roller. When the flash device is attached only to the hot shoe,
After outputting data in synchronization with the clock pulse in step #29, the same data is output again in synchronization with the clock pulse in step #30.

Note that even if the flash controller is attached to the camera body, the flash controller's connector (C
When no flash device is installed in position N5), the flash controller opens the line (A2) and sets it to 1 so as not to affect signal transmission.

Next, 16 pieces of data exchanged based on 16 clock pulses in steps #29 and #30 will be explained. Note that the first data of the clock pulse is bθ bibit, the 2111th data is b1 bit,
Below b2. b3.・・・・・・, b14, b1
It is assumed to be 5 bits. First, Table 1 shows the data contents of each pit and the states of the camera body, flash device, and flash controller.

Table 1 6 bits bO to b5 indicate that the flash device outputs the data shown in Table 1 based on the clock pulse from the camera.
The controller reads this data sequentially. bO
If the power switch of the flash device is closed, the bit outputs a "Higb" signal. The bit bl is "low" if the upper light emitting part (the one with the larger maximum light emission amount) of the above-mentioned parent/child strobe is in a bounce state and the parent/child flash mode is set, and is "high" otherwise.

The bit b2 outputs a 'Hioh' signal if the main capacitor of the flash device is fully charged, and a 'LOW' signal if it is not fully charged. Bit b3 is °'L if the dimming display is performed with a flash device.
"", if H light display is not performed "')light
” signal is output. Bit b4 is reserved and corresponds to future system development. For example, when a light emitting part is provided for an auxiliary light for automatic focus adjustment, that light emitting part can emit light. It is conceivable to output a "High" signal when the state is reached.

The bit b5 is data for identifying the system of this embodiment, and if the flash device is compatible with the system of this embodiment, it will always output a "low" signal. In the flash devices currently on the market, when the flash device is fully charged, the line (n2) is always "High".
When such a flash device is installed, the flash controller and the camera body will all read the signal l-1-1i+, which makes it difficult for conventional flash devices like this to output This is a signal for distinguishing the system from the flash device of the embodiment.

The bits be and b7 are the flash controller (f
f) is an actual light emission mode signal determined from the mounting signal read from the flash device and the set light emission mode set by the flash controller NV), and is output to line i2>, (912). Table 2 shows the signals of this light emission mode.

Table 2 Snake/〒/Shishiku-1 When the flash device reads the light emission mode signal shown in Table 2, the flash device will thereafter perform an operation according to this light emission mode signal.

Note that the flash device outputs data from bits b0 to b5, and reads data from bits be and b7. By the way, there are cases where cables are used to connect the connector (CN5) of the flash controller and the flash device, and the connector (CN9) at the hot shoe position of the camera body and the flash device II.
There are parasitic capacitance and impedance components between the signal lines (α2), (α3) in this cable and the ground. Therefore, when the 'l-(high' signal is output at the timing of bit (b5)), if the flash controller is not installed, the charge will remain accumulated in the parasitic capacitance because there is no discharge circuit. “H” as bits b6 and b7
The flash am reads the “high” signal.

In other words, in the case of single-flash emission where the flash device is connected to the camera body's Hole Shoe via a cable, if a 'High' signal is output at pit b5, this signal remains accumulated in the parasitic capacitance. Therefore, bit b6.117 is read by the flash device as a signal indicating, for example, simultaneous flash mode or sequential flash mode, causing a malfunction.Therefore, in this system, bit b5.
In this case, the discrimination signal "LOW" is outputted to discharge the parasitic capacitance by short circuiting and prevent malfunction from occurring.

For bits b8 to b15, if the flash device is only connected to the hot shoe of the camera body, the flash device outputs the data shown in Table 1, and the camera body reads this data. If the flash device is connected to the camera body via a flash controller, consider sending the b8 to b15 signals from the flash device as they are to the camera body via the flash controller, and having the camera body read these signals. However, in this case there are the following problems. That is, if a cable is provided between the flash controller and the flash device,
The signal is delayed by this cable and circuitry within the flash controller. Therefore, first, the clock pulse sent from the camera body to the flash device is delayed, and there is a time difference between when this clock pulse rises in the camera body and when it rises inside the flash device. The flash device then detects that the clock has risen and outputs data. This data is sent to the camera body via the cable and flash controller, but is delayed in the same way as the clock. Then, it will be read at the falling edge of the clock on the camera body.

However, if the delay time between the clock delay time and the data delay time is longer than the time from the rise to the fall of the clock in the camera body, the camera body will read incorrect data. Therefore, in this system, data from the flash device is read into the -H flash controller, and then data is sent from the flash controller to the camera body.

If a flash controller is connected to the camera body and no flash device is attached to the connector (CN5) of this controller, the flash controller is B8.
During the bits from ~b15, no signal is output to the line (north 2) and the circuit is in a high impedance state, so as not to adversely affect the data sent from the flash device connected to the hot shoe to the camera body. Also, if a flash device is attached to the hot shoe and flash controller, be,
At bit b7, any of data "'11", "10", or "01" indicating multi-flash emission is input to the flash device, and the flash device reads line 1. between bits b8 to b15. 2>, it does not output data to (α12) and enters a high impedance state.

Then, the flash controller outputs the data read from both flash devices and data based on the set light emission mode at pins b8 to b15, and the camera body (V) reads this data.

Next, the data of bits b8 to b15 will be explained. The b8 bit is the installation @ signal, and if the flash device outputs it, it will be “Htgh” if the power switch is closed.
’ signal is output. If the flash controller outputs b
If the “)light” signal is input in the O bit,
Outputs a "High" signal. The bO bit is a signal that distinguishes the system of this embodiment, and if the flash device is outputting it, it outputs the 'L GW' signal, and the flash controller outputs the signal from at least one flash device with the b5 bit. If the low signal is read, a low signal is output. bl
o is a signal indicating whether it is in the sequential flash mode or not, and when the flash device outputs data, if the flash device is in the parent-child flash mode, °' low ”
In other cases, it outputs a signal of ``)l +gh''.
Ru.

On the other hand, if the flash controller outputs data, it outputs a signal of "LOW" in sequential light emission mode and "HIGH" in other light emission modes. bll
The bit outputs a fullness signal.

When the flash device outputs, if it is fully charged, then ゛)l
When the flash controller outputs a signal, the attachment signal is input from the two flash devices, and the bit b is output from the two flash devices.
If a "High" signal indicating a full state is input in both flashes 2 and 2, a @high" signal is output at bit b11. Therefore, only one flash II can output a ")li" signal.
When the ``gh'' signal is not input, a ``LOW'' signal is output. The b12 bit indicates that the light was adjusted to obtain the appropriate exposure when taking pictures using a flash device (flash photography).
It is an FDC signal, and when the flash device outputs it, it is “1” while the flash device is displaying the completion of dimming.
-ow" FDC signal is output. When the flash controller outputs, if a "low" FDC signal is input from at least one flash device at hit b3, a "LOW" FCC signal is output. Do.b13
, b14, and b15 are preliminary data, and output "Low" signals both when the flash device outputs them and when the flash controller outputs them. When the data exchange described above is completed, the flash device and flash controller transfer to the next line (fL3).
, (, Q13) enters a mode (hereinafter referred to as standby mode) in which pulses are input, and at this time, crawling (
2) is 'lligh' if the flash is fully charged and 'LOW' if it is uncharged.

On the other hand, in the camera body, the data of bits b8 to b15 read from the flash device or flash controller to the register IOR in step #31 of FIG. 2 is set in a predetermined register, and the terminal (04) is set to
OW”.Next, in step #33, various setting data (exposure 11J Il
1 mode, the apex value Tvs1 of the set exposure time, the apex value AVS1 of the set aperture value (on the film container or the apex value Sv1 of the set film sensitivity, etc.) are taken into registers corresponding to the respective data. Next, in step #34, the output of the photometry circuit (ShiM) is 3v -AVO(B
V is the a degree of the subject and AVO is the apex value of the open aperture value) is converted from analog to digital and this data is set in a predetermined register. Then, in steps #35 to #37, #18
It is determined whether or not to proceed to the exposure control operation in the same way as in steps ~#20, and if the process is to proceed to exposure Ill a 11, the process proceeds to step #80; otherwise, the process proceeds to step #38.

A specific example of step #38 is shown in flowchart 1 in Figure 3.
This is shown below. First, in step #210, when it is determined that the FCC signal is input, the FDC display is set, the fullness display is reset, and the process moves to step #40. On the other hand, if the FDC signal is not input, the FCC display is reset and it is determined whether the full charge signal is input. If the fullness signal is input, the fullness indication is set; if not, the fullness indication is reset and the process moves to step #40.

In step #40, it is determined whether check data "1o1oioio" has been input from the interchangeable lens.If check data has been input, step #41
．． Calculation in step #42, if not input, #4
3. Perform mW in step #44.

The constant light calculation (2) in #41 is performed according to the flowchart shown in FIG. First, in step #101, (By-Avo)+Avo+Sv-Ev=(1) is calculated. However, Ev is the apex value wI of the exposure value
There is an exposure value. Next, the exposure control mode is determined in step #102, and the P mode (
#103 for program exposure Morton. 104
Shift to step p-Ev=Av (2) EV -AV -TV -<3 (0<p<1
). where AV is the value of the aperture aperture to be controlled, Tv is the apex value of the exposure time to be controlled, p is the program constant, and exposure 1iiiE
This is used to determine the distribution ratio for distributing V to the aperture value and exposure time value, and thereby determines the program diagram. The value of p can be determined at the time of design or manually set to a desired value. Then, in step #105, A
If it is determined that V<AVO, 1. A, va-AVO, and the calculation Ev-Ava=Tv-(5) is performed in step #107. And if TVO≦TV, then T in equation (5)
Set V as Hva and set the state in which no warning is issued as 1". On the other hand, if TvO>TV, set TvO as Tva and set the state in which an underexposure warning is issued. Here, Tvo corresponds to the longest exposure time that can be controlled by the camera body. .

If Ay calculated by formula (2) is AV>AVO, then AV>
Determine whether it is an AVM. And if AV>AVM then #
Move to step 114, set Ava=AVM, and #
At step 115, the calculation of equation (5) is performed.

If TV<TVM, the TV calculated by equation (5) is set as Va and a warning is issued.

On the other hand, in step #116, if TV > TV gate, then TV
M is set as Tva, and an overexposure warning is issued. Here, TVM corresponds to the shortest exposure time that can be realized by the camera body.

If it is determined in step #113 that AV≦AVM, no warning will be issued, and the AV calculated by formula (2) is the aperture value for constant light photography, and the Tv of formula 61Va1 (3) is the constant light photography condition. The exposure time for photography was 7'va, and #
In step 163, AVa-Δvo=dAva-(4) is calculated, the calculated dAva is used as the number of aperture stages for steady light photography, and the data of Ava, dAVa, and -rva are set in predetermined registers, respectively.

If it is determined in step #102 that the mode is not P mode, then in step #125 it is determined whether the mode is S mode. When the exposure control mode is S mode (n output time priority/automatic aperture control mode), set exposure time Tvs to Tva in step #126 and set EV -1-va=Av-
(6) Perform the calculation. Then, in the step #128, if the AV is AVO, the AVO is set as Ava and an under warning is issued, while in the step #131, the AV
>AVM, AVM is set as Ava and an over warning is issued. Also, if neither AV<, AIVor nor AV>AVM, then in step #134 (6
) is set as Ava, a state in which no warning is issued, and the process moves to step #163.

If it is determined in step #125 that the mode is not S, then in step #14o it is determined whether the mode is A. When the exposure control mode is A mode (automatic immersion/exposure time control mode), in step #141, calculate the set aperture value, A, vs by equation (5) as the aperture value Ava for constant light photography. Do this. Then, in step #143, if TVO>TV, Tvo is set to Tva and an underexposure warning is issued, and in step #146, TV
If M<TV, TVM is set to Tva and an overexposure warning is issued. TVO>TV, TVOpen TV
If neither of the above is true, the Tv calculated by the equation (5) is set as the ambient light photography exposure rR11I1-Va, and no warning is issued, and the process moves to step #163. P.S.
If it is not the A mode, it is the M mode (manual setting exposure control mode), and in this case, the process moves to step #155 and the set AVS and TVS are set as Δva and Tva, respectively.

Roughly calculate Ev - (Tva+, A, va) = dv, and when dv<- for a constant value k (allowable exposure error of the film), an under warning is issued, and when dv>k, an over warning is issued. When -k<av≦, it is assumed that no warning is given and the process moves to step #163.

In step #163, the aperture for constant light photography @ A va
and the number of aperture steps d for constant light photography from the open aperture value AVO.
Ava-Ava-AVO is calculated and the process moves to step #42, calculation I for flash light photography.

A specific example of step #42 is shown in the flowchart of FIG. 5, and will be explained below based on this flowchart. First, in P mode, Avo<3 CFN
o, equivalent to 2.8) (7) Tokiha Δvc1=3, A
For VO23, set AVCI=AVO, and #17
In step 4, perform the calculation AVO2=6+(SV-5)''・(7).Here, 6 corresponds to FNo. 8, and 5 corresponds to 1801
Corresponds to 00. And if Ava2>Avr'+ then A
Let VM be A vc2, and if A vc2≦AVM, then A
VO2 is left at the value determined by equation (7) and the process moves to step #177.

Next, the calculation Ev+1-6=Av.<8) is performed. Then, when the AV calculated by equation (8) is AV>Ava2 as a result of the determination in #178, A vf=A v
Let it be c2. And when AV[+6≧EV, Tvf
-6, and if AVf+5<Ev, the data from the flash device is set to Tvf-7 unless the data is in sequential light emission mode (parent-child light emission mode). On the other hand, if the sequential light emission mode signal is input, even if Avf+6<EV, Tvf −
It remains at 6. Then, AV7 calculated by equation (8)
) (If AVO1≦AV<A vc2, this AV is set as the aperture value Avr for flash photography, the exposure time Tvr for flash photography is set to 6, and the process moves to step #204.

If it is determined in step #170 that it is not in P mode, the flash device (flash
Controller) to sequential flash mode (parent-child flash mode)
If the sequential light emission mode is selected, set the tuning limit exposure time lower VQ to 6(1,'6oSeC).
), if it is not sequential flash mode, set TVQJ to 7 (1/
125 sec>, the process moves to step #190.

When it is determined in step #190 that the mode is A, the set aperture value Avs is set to AV[, the TV magazine is set to Tvf, and the process moves to step #204. If it is determined in step #190 that the mode is not A mode, if the set exposure time TV3 is TVS>TVα, then TVf-TvQ, Tv
If s<TVQ, Tvf=7' vs. #
In step 19G, it is determined whether the mode is S mode or not. If it is S mode, the following calculation is performed. If AV<AVO, AVO is set to Avf.

If AV>AVM then AVM is AvflAvo<Av
<AVM, the AV calculated by equation (9) is set as Avf and the process moves to step #204. If the mode determined in step #196 is M mode, change AVS to Av
f, move to step #204, and set dAvf-A.
vf-AVO.

Specific examples of the steady light calculation (2) in step #43 and the flash light calculation H in #44 when the lens is not attached are shown in the flowchart of FIG.

The following explanation will be given based on the flowchart shown in FIG.

First, in step #220, the calculation Bv - AVn + SV - Tv - (10) is performed. Here, BV −Avn is the photometric output, and Avn
The aperture is not controlled by the system of this embodiment, and
It corresponds to the aperture value of an interchangeable lens intermediate ring, bellows, pinhole photographic adapter, etc., which is manually set by itself or has a specific aperture fixed in advance.

Next, in step #221, it is determined whether the mode is M1 need or other mode. In the M mode, the set exposure time Tvs is set as the control exposure time TVa, and Tva -
TV < Tv of equation (10) = dvc7) Perform the calculation. And when dv<-, over warning, d
When v>k, an under warning is issued, -d
When v:g, ≦dv, it is assumed that no warning is given and the process moves to step #238.

If it is determined in step #221 that the mode is not M mode, in this case, the TV calculated by equation (10) is T vo
If <TV≦TVM, the TV calculated by equation (10)
is set to 7va and no warning is issued, and Tv
If O, TvO is set to Tva and an under warning is issued, and if TV>TV bar, TVM is set to 7va and an over warning is issued.

Then, in step #238, dAva=Q is set, warning data is set as Ava so that a warning that a lens is not attached is issued, and the process moves to step #240.

When the P mode is determined in step #240, the TV calculated by equation (10) is 1-v≦6 (1
/60sec), set Tvf = 5, and when Tv > (3, if it is not sequential mode, l"'vf = 7(1/'
125sec), if in sequential mode, l”vr=
5 and moves to step #253.

If it is determined in step #240 that the mode is not P mode, then in step #245 it is determined whether the mode is sequential. In the sequential mode, the tuning limit exposure time TVα
= 6, if not sequential mode, set TvQ = 7 #24B
Move to the next step.

In step #248, it is determined whether it is A mode or not, and
If it is the mode, Tv4=Tvα and the process moves to step #253. On the other hand, if it is not A mode, it is determined whether the set exposure time TVS is TvS≦l”vλ, and Tvs≦
If TVfL, Tvs@Tvf1Tvs>TvQ, then TvQ is set as TVf and the process moves to step #253.

In step #253, set it to dAvf@o, and set Av
As for f, a warning is given for lens not yet used.
The warning data is set and the process moves to step #45. In the sequential flash mode, a maximum of three flash units fire, so the shortest limit exposure time is the X contact (Sx
) opens and the shutter rear curtain reveals its face after the time required for the three lights to emit light in sequence Tv = 6 (1/60
sec), and if it is not sequential flash mode, the exposure time of the R short limit is a TV in which the rear shutter curtain will expose the face after the time required for the X contact (SX) to close and one light to emit light.
-7 (1/125seO).

When the above calculation operation is completed, the process moves to step #45, and it is determined whether or not a fullness signal is input from the flash device. If the charge completion signal is input, flash photography will be performed, and therefore signals indicating the aperture value Avf for flash photography, exposure time Tvf, and the status of the flash device (charge complete, flash control display) will be displayed on the display (DP). On the other hand, if the fullness signal is not input, ambient light photography is performed, so the aperture value Ava, exposure time Tva, and warning data for ambient light photography are sent to the display section (DP).Then, # In steps 48 to #50, #18 to #
In the same manner as in step 20, it is determined whether or not to shift to the exposure control operation, and if the mode is to shift to the exposure control mode, the process moves to step #80, and if not, the process moves to step #55.

In step #55, the microcomputer (MCI) terminal (
04) , (06) wo “Hiol+” ,! :t le. CtL activates the NAND circuit (NAI) and AND circuit (ANll) in Figure 7, and data from the camera body is transmitted to the flash device via lines (1>, (A12)). .And the terminal (0
5) for a predetermined period T2 (for example, 150 μsec)
Outputs a “Higb” signal, and this signal is connected to the line (
A3), the data is transmitted to the flash device and the flash controller via (913), and it is determined that the mode is in which data is transmitted from the camera to the flash device (hereinafter referred to as CF mode). And a microcomputer (MC)
I) sets the aperture value Avf for flash photography in the serial input/output register IOH, and outputs this data in series. Next, the film feel 11Sv and mode data are set in the register IOR, and the data is output in series.Next, the focal length fv of the interchangeable lens is set, and the data is output in series. Then, in step #63, terminals (04>, (06
) is set to "low" and the process moves to the next step #64.

Next, data exchange between the flash device and the camera body will be explained based on FIG. First, in the FC mode, the terminal (06) becomes "OFF" and the NAND circuit (NA
The output of I) is 'High' AND circuit (ANll)
The output of becomes “LOW” and the transistor (BT15)
, (BT17) are non-conductive. Therefore, the terminal (
Including 2) is open. Then, the terminal (SGK
), this clock pulse is output via the AND circuit (AN5) and the OR circuit (OR3), and when the clock pulse is "High11", the inverter (IN3) outputs the clock pulse from the transistor (BT
ll) is conductive, and the line (magazine 3) is "Hi9h"
When the signal is output and the clock pulse becomes “LOIll”, the transistor (
B T 13) is conductive, and the line (O 3) is 'LOW'.
” signal is output. In this FC mode, serial data is input from the flash device, but at this time transistors 1 to (BTI5) and (B T 17) are non-conductive, so the line (α2 ) becomes 111g1'', the transistor (B T 19) becomes conductive and the inverter (IN
The output of 7) is “old gh”, and the line (α2) is “’LO”.
When the voltage becomes "W", the transistor (B T 19) becomes non-conductive, and the output of the inverter (IN7) becomes "'1ow".

The output of this inverter (IN7) is an OR circuit (ORI).
) to the series input terminal (SI) of the microcontroller (MCI).
N) to the microcomputer (MCI').

In CF mode, terminal (06) is 'Higl+
” becomes a NAND circuit (NA1) and an AND circuit (ANl).
l) is in the active state. Then, the data from the series output terminal (Sou) is outputted via the AND circuit (ANO), and when the "Ht9h" signal is output, the output of the NAND circuit (NAI) becomes "LOW" and the transistor ( BTI5) is conductive and the line (magazine 2) is '
l-111Jh".

On the other hand, when the output of the AND circuit (ANO) becomes "low", the output of the AND circuit (ANII) becomes "high", the transistor (B T 17) becomes conductive, and the line (2) becomes "1ow".

Returning to the flowchart in Figure 2 again, the microcontroller (MCI)
) operation will be explained next. In step #64, the preparation for exposure control is completed, so the content of the discrimination flag JFI is set to '1°' and step #19. Similar to step #20, it is determined whether to proceed to the exposure control operation. If the exposure control operation is to be performed, proceed to step #80, and if not to the exposure control operation, proceed to step #70.
Move to the next step.

In step #70, the photometric switch (Sl) is opened and it is determined whether the input terminal (11) is "1-ow". If the input terminal (11) is 1li (lh) in step #70, go back to step #11 and repeat the above operation.
In step , the operation of the automatic focus adjustment circuit (AF) is stopped, the display on the display unit (DP) is turned off, and the flag JFI is set to "0".
'', it is possible to accept an interrupt signal from the terminal < it), and the power supply line (+
(2)), and the microcomputer (MC1) stops operating.

When performing an exposure control operation, the operation is performed from step #80. In step #80, the automatic focus adjustment circuit (
AF) operation. Next, connect the terminal (04) to "'H"
"high", outputs "Hi, I, II" signals to the terminal (05) for a predetermined time T3 (for example, 210 μsec), and sets the terminal (04) to 'low'.

The flash device and flash controller read this signal and enter the mode (hereinafter referred to as ES) in which exposure control operation is performed.
mode), and the closing signal of the X contact (Sx) of the camera body is input from the line (north 1). Next is #84 Ste.

In the Tsubu, it is determined whether or not a fullness signal is inputted from the flash device, and if it is inputted, the exposure control mt values Tvf and dAvf for flash photography are sent to the exposure control circuit (FCC) via the output terminal (OPl). If the fullness signal is not input, the exposure control value for ambient light photography is set to 7.
'va, dAva is sent to the exposure control circuit (FCC) via the output terminal (OPI). When shooting with flash, it is determined in step #86 whether or not a sequential flash mode signal is being input, and if it is sequential flash mode, an analog signal corresponding to the film sensitivity Sv is sent from the terminal (ANO>). If it is not in the sequential light emission mode, an analog signal corresponding to 5v-0, 5 is output from the terminal (ANO).The meaning of the analog signal from this terminal (ANO) will be described later based on FIG.

In step #90, the display on the display unit (DP) is turned off, and then the terminal (02) is set to ""@igh"'.

As a result, the release circuit (RL>) operates and the exposure control operation starts.Then, the aperture aperture is controlled and the reflection mirror is raised, and when the raising is completed, the front curtain begins to move. .

Then, when the shutter lead register is completed, the X contact (Sx
) is opened, and if it is flash photography, the flash fires. Control of the amount of flash light emission will be described later with reference to FIG. After the front curtain starts running, when the exposure time determined as described above has elapsed, the shutter rear curtain starts running, and when the shutter rear curtain completes running, the anti-fouling mirror lowers and the aperture stops. becomes open.

The switch (S4) is opened when the above exposure control operation is completed, so the microcomputer (MCI') opens the switch (S4) and input terminal (i3) becomes "l-1-1".
i” in step #92. Then, when the input terminal (i3) becomes “l-1-1i”, the terminal (02) is set to “LOW” in step #93, and the photometry switch (S
1) is closed and the input terminal (11) is "LOW". Then, if it is "low", it moves to step #11, and if it is "high", it moves to step #95, and flag JF1 is set.
Set the terminal (01) to 'O'' to enable reception of interrupt signals to the terminal (IT), and set the terminal (01) to 'L ON' to connect the power line (+
(2) stops the power supply and the microcomputer (MCI) stops operating.

Next, the light emission amount control operation of the flash device will be explained based on a specific example of the light emission amount control circuit (FST) shown in FIG. In Fig. 8, (PD) is a light-receiving element placed at a position to receive the light that passes through the photographing lens and diaphragm of the camera and is reflected on the film surface, and the output current of this light-receiving element (PD) is transmitted through a diode ( Dll) is logarithmically compressed. Then, the output from the analog output terminal (ANO) is 3V when in sequential light emission mode, and 5V when not in sequential light emission mode.
Since signals of 0 and 5 are output, when the flash is fired, the output of the OA has information on the intensity of the reflected light from the subject due to the flash, the control aperture value, and the film sensitivity, Qv +3v -Avf or Qv + (S
v −0,5) −Avf. Here, Qv is a value obtained by logarithmically compressing the intensity of reflected light from a subject under flash illumination. The output of this trunk amplifier (OA) is logarithmically extended by a transistor (BT29) as its collector current, and this collector current is connected to a capacitor (C11).
It is integrated by Therefore, the integrated voltage of the capacitor is 2sl, J z &', 1t//2Avf or 2! ; v-o, 5. ! , z&va, / 2Avf
It turns out that.

The terminal (02) is set to "'l-" when the exposure control operation starts.
1-1i", and this terminal (02) is ""
)light”, the AND circuit (A N 13) becomes active and the output becomes “lligh”. Also, the signal “111g1l” from the terminal (02) is sent to the delay circuit (DL
After being delayed by ■ flip-flop (T
FI) and D flip-flop (DPI), and these 7-lip 70-tube (TFI)
, (DPI) are released from the reset state and made operational. Therefore, at this point, the flip-flop (TF
The Q output of both l ) and (DFl ) is 'low', and the 0 output is 'highb'.The terminal (INT
) is the output of the inverter (IN7) in FIG. 7, and is a signal from the flash device via the line (magazine 2).

In ES mode, if the flash is fully charged, this line (north 2) will be at °'High until it starts firing.
h” and 2.5 when the X contact (SX') is closed.
It becomes “L OW” for m5ec, then it becomes “High” for 1 m5ec, then 5. Fvsec “LOW”
Then, it becomes "H+gh". Therefore, the output of the delay circuit (DLI) in FIG. 8 is ')-1111h
”, the output of the AND circuit (AN15) is “LOW” and the output of the inverter (IN9) is “r
-++gh”, the output of the NAND circuit (NA3) is “Hi”
gh", the output of the NAND circuit (NA4) is °'1-ow
"Te, transistor (BT21) and transistor (BT
27) is conducting. Therefore, the comparator (ACI
)'s non-inverting input terminal is connected to a resistor (R2/3) and a constant current source (
C1l), and this resistance (R2/3
) resistance value and constant current value are 70% of the appropriate exposure level.
It is set to generate a potential at a level of .

Next, the light emission amount control operation will be explained sequentially starting from the case where the light emission mode is not set. When the flash starts firing, the AND circuit (A
The output of N13) becomes low, and the NAND circuit (NA
4) output becomes 'l-(igt+''), transistor (BT27) becomes non-conductive, and transistor (BT2
9) is integrated by the capacitor (011). In this case, from the analog output terminal <ANO), 3V-
Since signals of 0 and 5 are output, given θ, 7・z 5vJZ&-, y also /zA-f-R=
When ρf7K...(11) (K: constant corresponding to proper exposure), the output of the comparator (Act) is "'
) high” and a “Higb” pulse is output from the one-shot circuit (081), and this pulse is output to the line (α3) via the circuit shown in Fig. 7, and the flash emission stops. (11) The formula is as follows, and therefore, the flash will emit light until proper exposure is achieved.After this, the circuit in Figure 8 performs the operation described below based on the signal from the terminal (INT), but it sequentially switches to the light emission mode. Therefore, it does not affect the flash emission.

In the sequential light emission mode, the operation when the first light is emitted is performed in the same manner as described above. However, at this time, an SV signal is output from the analog output terminal (ANO). Terminal (INT)
When rises from 'Low' to 'High', the T flip-flop (TFl) inverts the output, and the Q output becomes 'High' and the Q output becomes 'LOW'.On the other hand, the D flip-flop (DPI) At this time, the output of the comparator (ACl
C", the Q output becomes "LOW". If the light emission amount of the first lamp does not reach 70% of the proper exposure, the comparator (
Since the output of ACI> remains 'LOW', the Q output of the D flip 70 tube (DFl) remains 'LOW' and the 0 output remains 'H+gh'. When the first light emission amount reaches 10% of the proper exposure, the NAND circuit (NA3
) remains the same as °'l-1-1i", so the output of the NAND circuit (NA4") has a terminal (TNT) of -HHg.
After reaching hrr, the delay circuit <[)13) becomes LOW” after a certain period of time, and the transistor (B T 27
) becomes conductive and the integrated charge of the capacitor (C11) is discharged. On the other hand, if the first light emission does not reach 70% of the proper exposure, the output of the NAND circuit (NA3) will be LOW.
”. Therefore, the output of the delay circuit (DL3>
Even if it is reversed to ``1-1-1i'', the output of the NAND circuit (NA4) remains ``H1 (Jll'') and the transistor (
BT27) is not conductive and 1 due to capacitor (011)
The integrated charge of the lamp remains retained.

When the light emission amount of the first lamp reaches 70% of the proper exposure, the output of the AND circuit (AN15) becomes 'High', the output of the inverter <lN9) becomes 'LOW', and the 1-transistor (BT23) conducts, and the comparator (ACl)
The level of the non-inverting input terminal of is determined by the resistor (R1/3) and the constant current source ((,11).
A resistance value of 1/3) is designed to generate a potential of 30% of the proper exposure with a constant current of 11t (CII). On the other hand, if the proper exposure has not reached 70%, the NAND circuit (
The output of NA3) becomes "LOW" and the transistor (BT25) becomes conductive. This allows the comparator (
The level of the non-inverting input terminal of ACl) is determined by the resistance (R1)
and the level determined by the constant current source (C11), and the resistance (R
The resistance value 1) is such that, together with the current of the constant current source (C1l), a potential at a level corresponding to proper exposure is generated.

Therefore, a voltage corresponding to the appropriate exposure level is applied to the non-inverting input terminal of the comparator (Act). Then, when the second lamp starts emitting light, the terminal (INT) is '
When the first light reaches 70%, the transistor (BT27) becomes non-conductive again and the collector current of the transistor (BT29) is integrated again by the capacitor (C11). If the amount of exposure due to the first light emission does not reach 70% of the proper exposure, the transistor (B T 27) remains non-conducting, so the capacitor (C: 11) is connected to the first light emission. Integrate so that the integrated charge of the second lamp is added to the integrated charge.

When the exposure from the first light reaches the proper exposure condition, a light emission stop signal is output, and the light emission amount from the second light becomes 30% of the proper exposure. In this case, the light emission amount from the first light and the second light is the ratio. is 7:3, and the sum of the amounts of light sold on both sides gives the appropriate exposure. On the other hand, 1
When the amount of light emitted from the first light reaches , a light emission stop signal for the second light is output. Therefore, in this case, the ratio of the amount of light emitted by the two lights is 7:
Although it cannot be controlled to 3, proper exposure can be compensated by two flashes.

In addition, when three lights emit light in succession, after the second light starts emitting light and the time required for the second light to fully emit light (2.5 m.
5ec later) The third light emits light. At this time, the terminal (INT)
Since it remains 'Low', the integration by the capacitor (C11) continues. For example, if the proper exposure is not reached with the emission of two lights, a light emission stop signal is output to the line (north 3) when the third light is emitted. However,
This light emission stop signal is not transmitted to the third flash device as shown in FIG. 1, and the third flash device emits only the amount of light that can be dimmed by that flash device. Also,
For FDC signal output, the first and second flash devices only accept a light emission stop signal for 2.5m5ec after the second light starts emitting light, and for "light emission" control, the flash device that emits light emits light. Since the flash stop signal is accepted only between 2.5+n5ec after starting the flash, there is no possibility that the flash stop signal caused by the third flash will act on the first or second flash device and cause a malfunction. It won't happen.

Next, a specific example of the flash device a(1) shown in FIG. 1 will be explained based on FIGS. 9, 10, 11, 12, 13, and 14. Figure 9 shows the control circuit (FL
Cl) is a specific example. From the terminal (α3), pulses with widths indicating FC mode, CF mode, and ES mode, clock pulses for data exchange, and pulses for stopping light emission are input.
When the terminal (DJ3) becomes "Hioh", the transistor (BT31) becomes conductive and the output (O3) of the inverter (INll) becomes "Higl+". The mode discrimination circuit (TiG) is rl of “Hi9h” of this terminal (O3).
J is detected to control the operation of the flash device.

Next, the discrimination operation will be explained based on a specific example of the mode discrimination circuit (T(C)) shown in FIG. When the transistor (
This is a terminal that becomes ``High'' when BT39) conducts, and becomes ``Low'' when pulses indicating f-C mode, CF mode, and ES mode and clock pulses for data exchange are input. Then, inverter (I
The output of N19) is 'l-1i9h'. When the terminal (O3) becomes 'High', the AND circuit (A
The output of N43) rises to "'Hi9h", a "High" pulse is output from the one-shot circuit (083), the counter (COI) is reset by this, and then from the terminal (CKO) of the microcontroller (MC2). The reference clock pulses (φ2) of are counted.

Further, the flips 70 (FF1) to (FF7) are set by a pulse from the one-shot circuit (083). Terminal (τ1) of the decoder (DEO) that inputs the signal from the counter (001).

From (τ2), (τ3), and (τ4), 60 μsec and 120 .mu.sec from the start of counting, respectively. czsec, 180
μsec.

A pulse is output after 240 μsec. Therefore, flip 70 (FF1) is 60μs from the start of counting.
Set state for ec, (FF3) for 120μsec,
(FF5) for 180μsec, (FF7) for 240μsec
It is in the set state for sec. Therefore, the AND circuit (AN45) is active for 60 μsec to 120 μsec, and (AN A7) is active for 120 μsec to 180 μsec.
active for sec, (A N 49) is 180μsec
It becomes active for 240 μsec.

The one-shot circuit (O85) outputs a "high" pulse when the potential of the terminal (O3) falls, so if the potential of the terminal (O3) falls in 90 μsec, the one-shot circuit (O85) The pulse is output from the AND circuit (AN45) and sent to the flip-flop (F
F9) is set, and the terminal (FC) goes High. On the other hand, if the terminal (p3) falls in 150 μsec, the pulse from the one-shot circuit (055) is output from the AND circuit (A N 47). The flip-flop (FF11) is set, and the terminal (CF) becomes 'High.
If the terminal (p3) falls in 210 μsec, the signal from the one-shot circuit (<085) is output from the AND circuit (AN49), the flip-flop (F F i3) is set, and the terminal ( ES) becomes "light". Note that the clock pulse is output from the AND circuit (A N 43), and the pulses are output from the one-shot circuits (083) and (055), but in this case, the interval between the two pulses is much larger than GOμsec. Because it is narrow, 7 lips and 70 tubes (FF9), (
It does not affect the states of FF11) and (FF13).

When the terminal (FC) becomes '1-High', the counter (
CO3') is released from the reset state, and the decoder (DE
l) becomes ready for output. and the counter (CO
3) counts the falling edge of a signal obtained by inverting the data exchange clock pulse from the terminal (p3) using the inverter (IN21), that is, the rising edge of the clock pulse. Then, the decoder (DEL) has a counter whose contents are ``1''.
“'High” is applied to the terminals (fO) to (fl5) each time the
” signal is output. In other words, if the output of the counter (CO3) is “oooi”, then (fO) is “ @ igt+
”, “ooio” means (fl) is “High”,
If it is “1000”, (fl) is “HiQh”, “1o”
oi” Now (fO) lfi “High”, “1
111", then (fl4) is '@igh", "o
ooo", then (fl5) becomes "l-1-1i". This signal is used for gate control for data exchange.Furthermore, when the terminal (fl5) becomes "'l-1-1i", the AND circuit (AN44 ) becomes active, and the inverter (IN
21) is output. And the inverter (
The rise of the output of IN21), i.e. 1 in FC mode.
At the falling edge of the 6th clock pulse, a pulse is output from the one-shot circuit (084), and at the falling edge of this pulse, the one-shot circuit (086) is triggered to output a pulse, and the flip 70 knob (FF9) is activated. It is reset, and the terminal (FC) becomes "'LOW" and enters the timing mode. Well, the IL S terminal (CF) is
” and enters CF mode, the counter (C
04) is released from the reset state, and the decoder (DE2
) becomes ready for output. and counter (CO4)
counts the clock pulses from the inverter (IN21) and reads 24 clocks (3 bytes)] -
Then, the output becomes 11000" and the decoder (DE
2") terminal (a23) becomes "High". Then, the AND circuit (ΔN46) becomes active and the signal from the inverter (IN21) is output, and the falling edge of the 24th clock pulse, that is, the AND Circuit (AN
46), a pulse is output from the one-shot circuit (088), and at the fall of this pulse, a pulse is output from the one-shot circuit (OS 10). Then, the 7 lip flop (FF11) is reset by the pulse from this one-shot circuit (OS 10), and the terminal (
CF) becomes “'Low”, and the CF mode changes to the period mode. In the ES mode when the terminal (ES) becomes 'Higl+''', the shutter 41! of the camera body is activated.
When the curtain completes its travel and the X contact (Sx) is opened,
The transistor (BT39) in Fig. 9 is non-conductive, the terminal (pl) is LOW'', and the output of the inverter (IN19) is ``t''high'', resulting in a one-shot circuit (O8γ).
) outputs a pulse. This allows flip 7
The 0 knob (F F 13) is reset and the terminal (ES)
becomes 'LOW' and enters the period mode.

Returning to FIG. 9, CFTCl shown at the bottom right is a light emission amount control circuit, and this circuit (F
A specific example of TCl) will be described later based on FIG. Also, (MC2) is a microcontroller.
The operation 2) will be described later based on the flowcharts of FIGS. 13 and 14. In the timing mode, the terminals (FC), (CF), (E
S) are all “Low”, and the terminal (fO
) to (fl5) are all 'L OW', so the outputs of the NOR circuits (NO3) and (NO5) are °l-I.
It's Lgh u. As described later, light emission m l
The output (INS) of the l1lJ m circuit (FTCl) is 2.5m5 when the fully charged irx contact (Sx) is opened.
It is "low" until ec has elapsed, then it becomes "H1g11' for 1 m5ec," then it becomes "LOW" for s, 5m5ec, and becomes "l-(high" for another 2 m5ec. , from then on it remains “L OW”.This terminal (I
Even if the X contact (SX) is opened and the output of the AND circuit (AN24) is in the full state, the signal from the NS) is forcibly set to "cOll", then the OR circuit (OR2), the AND circuit (AN21), Output via OR circuit (OR5),
AND circuit (AN18) and AND circuit (AN 19)
), 1-transistor (BT35), (BT
37), the signal from the terminal (INS) is output to the terminal (A2). In addition, in the standby state, the AND circuit (AN33) is sent from the AND circuit (AN24) in the fully charged state.
) if the output is 'I'igb°', a signal of 'l-1-1i' is output, and if it is not charged, a signal of 'low' is output. If it is fully charged, the transistor (BT8
3), (BT35) is conductive, and the line (α2) is “'H”.
1gh" signal is output, and if it is not charged, the transistor (
BT81), ([3T37) are conductive and 'Low
” signal is output.

When the FC mode is entered, the mode discrimination circuit (TIC) terminal (
FC) becomes 'High', the output of the NOR circuit (NO5) and the output of the AND circuit (AN21) = LOW
'l yell. Mode discrimination circuit (TIC) terminal (10)
When becomes "l-1igb", this signal becomes OR circuit <
The output of OR7>, (OR5) is set to ``High'' and a signal of 1-1ioh'' is output to the terminal (north 2). This signal becomes the signal of bit bO in the garment 1, ie, the wearing signal. The terminal (fl) of the mode discrimination circuit (TIC) is
l igt+ ” When K, an AND circuit (AN29>
becomes active, and if the light emitting part (FLO2) of the flash device (1) in Fig. 1 is in the bounce state, the switch (SB1) is closed and the 'Low' signal is not in the bounce state. (SB1) CarfOM
Sale "Higll" (7) The signal is an AND circuit (AN
29).

Therefore, from the AND circuit (AN'29), l-1-1i''
When the signal is output, the AND circuit (A N 18
) output is “G11g1+”, AND circuit (A N 1
9) becomes 'LOW' and the transistor (BT8)
3), (8th line 35) is connected, and the line (including 2) is “
The signal “Htgh” is output. On the other hand, the signal “L O
When a signal of "W" is output from the AND circuit (AN29), the output of the AND circuit (AN18) becomes LOW, and the output of the AND circuit (AN19) becomes "Trigb".
Transistors (BT81) and (B T 37) conduct and a LOW” signal is output to the line (mantle 2). This signal becomes the parent/child signal of bit b1 in Table 1. Mode discrimination circuit (Tic) When the terminal (f2) becomes 1high, the AND circuit (AN31) becomes active.

As a result, a signal from the AND circuit (A33) is output. The AND circuit (AN33) connects the two main capacitors (CI) of the flash device I (I) in Figure 1.
), (C2') reach a predetermined value, and the outputs of the charging completion detection circuit (CHDI) and (CH, C2) both reach the specified value.
When it becomes "High", a signal of 'l-1-1i' is outputted.The output of this AND circuit (AN33) is outputted to bit b2 of Table 1, that is, the line (α2) as a fullness signal.Mode discrimination circuit (TIG) terminal (3) is “Hi”
gh”, the AND circuit (AN35) becomes active, and the dimming completion indication circuit (INF) (details are shown in the 12th
(described later based on the figure) is output to the line (Ko2) as the signal of bit b3 in Table 1. Then, terminals (f4) and (f
5) becomes -Hi o i Tl, the terminal (f4
), (f5) are not connected anywhere, so the OR circuit (
The output of OR5) is 'Low', and the AND circuit (A
The output of N19) is
18) is "L OW", transistors (BT81) and (BT37) are conductive, and the line (
The -I LOWl- signal is output to the input 2). As shown in Table 1, bit b4 is a preliminary timing, and bit b5 is a discrimination signal indicating this system.

Terminals (f6), (f7.
) is a NOR circuit (N
The output of O3) becomes “LOW” and the AND circuit (8N
18) and the output of the AND circuit (A N 19) are both "
LOW”.

Therefore, the transistors (BT35) and (BT37) become non-conductive, and the transistor (BT33) becomes conductive or non-conductive depending on the signal input from the line (2). Then, at this timing, as explained in Table 1 and shown in the IC, a light emission mode signal determined by the flash comma roller is input. If the line (including 2) becomes “'1” high u, the transistor (BT33)
conducts and the output of the inverter (IN 13) is °”l
-1-1i'', if the line (α2) is LOW'', the transistor (BT33) becomes non-conductive and the inverter (I
The output of N13) becomes "'LOW". While the terminal (f6) of the mode discrimination circuit (TIC) is in the "high" state, the AND circuit (AN25) becomes active, and the clock pulse (seventh pulse) from the terminal (p3) is output. D flip 70 tip (DF3
) latches the bit b6 signal from terminal (p2).

And the terminal (f7) of the mode discrimination circuit (TIC) is "
@igh”, the AND circuit (AN27) becomes active, the 8th pulse from the terminal (p3) is output, and the D flip-flop (DF5) outputs the 8th pulse from the terminal (p2).
) is latched. Flipf [
The data latched in the chips (DF3) and (DF5) are sent to the input terminals (Nl) and (i1) of the microcontroller (MC2).
2), and the light emission state according to the light emission mode is determined. In addition, if other flash devices are installed in addition to this flash device (1), as explained in Table 1, bits b6 and b7 (one of them is "') - (1)
g1)", the OR circuit (OR8) output G, t"l-1-1i" The output of the 7nd circuit (AN23) is the terminal (f8) of the mode discrimination circuit (TIC). ) ~ (r15) output is " +-+ igh
During n, the output of the NOR circuit (NO3) is 'LOW' and the terrain (jL2) k: is in a state where no signal is output. In this case, as mentioned above,
Simultaneous emission mode or sequential emission mode, bit b8
The signal from ~b15 is output from the flash controller 1 roller to the line (north 2) and read by the camera body. During this time, the transistors (BT35) and (BT7) remain non-conductive, interfering with data exchange between the flash controller and the camera body. It will never be.

If the signals latched in the flip-flops (DF3 > and (DF5) are both 'LOW', it means that one or more flash devices are connected to the camera body. In this case, the OR circuit (OR8), AND circuit (AN2
The output of 3) is 'LOW' and the output of the NOR circuit (NO3) is 'High', and the AND circuit (AN18)
and the AND circuit (A N 19> is active, and the line (
It is now possible to output data to α2). The mode discrimination circuit (TIC) terminal (f8) is High11”
Then, this Higl+” signal is connected to the OR circuit (OR9
'), and as before, the line (α
-Higl and JT signals are output to 2). This is the attachment signal of bit b8 shown in Table 1. Terminal (f
9) becomes “High, JT”, the OR circuit (
The output of OR9) is '1Ovi', so line (92)
becomes “low”.

This is a discrimination signal for pins 1 to b9 shown in Table 1.

The terminal (flo) of the mode discrimination circuit (TIC) is “+-+”
toh”, the signal indicating the open/closed state of the switch (SB1) is output from the AND circuit <AN37) and the OR circuit (OR9).
It is output from the line (α2). This is Table 1
It is a sequential light emission signal of bit blo of the light emitting unit (FLO
2) is in the bounce state, the flash mode (
The line (L2) is set to “IO
W” and determines that the camera body is in sequential flash mode (parent-child flash mode).Mode determination circuit (TIC)
When the terminal (fll) becomes 'High', the charging completion signal from the AND circuit (AN33) is output from the AND circuit (AN3).
9), is output to the line (Fu2) via the OR circuit (OR9).

By the way, the 7 lip-flop (FF2) is reset to 1 by the pulse output from the one-shot circuit (082) when the terminal (FC) of the mode discrimination circuit (T (C) becomes ``H1g signal 1''). In the single light emission mode, when the transistor (BT35) is turned on as a fullness signal by the pin 1)11, the transistor (BT3) is turned on.
3) becomes conductive, and the terminal (p2) becomes 11g11°'. In this case, the AND circuit (A N 20) is 'LOW
”, the flip-flop (FF2) remains in the reset state. Therefore, the output of the NAND circuit is °'I-Hg
h” makes the AND circuit (AN22) active and the terminal (
The light emission start signal from the light emission control circuit (FTCI)
to communicate. On the other hand, when charging is not completed, the transistor (BT37) is conductive and the line (α2) is “L”.
OW”, but this causes the transistor (BT33)
becomes non-conducting and the terminal (p2) becomes 'LOW'. As a result, the flip 70 (FF2) G is set and the output of the NAND circuit (NA5) is set to the terminal (ES). When it becomes ``LOW'', the AND circuit (AN22) becomes disabled and the terminal (
Even if a light emission start signal is output from pl), flash light emission is not performed. Therefore, it is determined whether the flash HE itself fires based on the fullness signal sent to the camera body with bit b11, and whether the camera body performs flash photography based on the fullness signal sent with bit b11. The system does not malfunction because it has already decided whether the

When in multi-flash mode, the flash device is set to bits b8-b.
The flash controller 1-roller does not output the signal 15, but as described later, it outputs a ``High'' signal if both flash devices are fully charged, and a ``LOW'' signal if at least one is not fully charged. Output to 2). This signal is read as a full charge signal by the camera body, but the flash device also uses a flip-flop (
It is read by FF2) and it is determined whether or not to emit light.

Also, the output to the flash device line (magazine 2) is '
The output current when outputting a Hig117' signal is °'
1. The input current is smaller than the input current when outputting the "ow" signal. That is, a difference is provided in impedance. This configuration is used to perform the following operations.

A conceivable option is to prepare a connector that connects each terminal of two or more flash devices to the camera body in parallel, and to use a multi-flash connector to cause each flash device to emit light at the same time. When connected like this, the terminal (fll) becomes “’ Hi.
gh” and outputs a full charge signal, if at least one flash device is not in a full state, the transistor (8-3γ) of at least one flash device
conducts and the transistor (BT
Even if the transistor (BT35) is conductive, the current from the transistor (BT35) is connected to the constant current circuit (C(10)) and the transistor (B
Since the current is limited to a constant current by rO3), even if the transistor <BT35) conducts, this output current will be limited to the 1-transistor (BT3
It flows into 7>. Therefore, the transistor (BT
33) cannot conduct in any flash Hfflf,
The flip-flop (FF2) is connected to the cell 1, and the flash device connected to the connector for multiple lights cannot emit light.

The terminal (f12) of the mode discrimination circuit (T I C) is "'
1-1-1i''', the dimming completion display circuit (, I N
The signal from F) is output to the line (north 2) via an AND circuit (AN41) and an OR circuit (OR9).

These are the FCC signals indicated by bit b12 in Table 1, which are read by the camera body and used to indicate the status of the flash device. Mode discrimination circuit terminal (f13)
, (f14), (f15) are °' High
”, the output of the OR circuit (OR9) is “OTV” and the line (OR2) remains “L-OW”, which is a reserved state as shown by bits b13, b14, and b15 in Table 1. It's a bit...

Next, the light emission IIJIII operation in the ES mode will be explained using the m9 diagram and the 11th factor. The X contact (Sx) of the camera body V in Figure 1 is opened and the terminal (ρ1) is
”, if the flip-flop (FF2) is in the reset state at this time, the NAND circuit (NA5) becomes ' Hi
gh” signal, and if it is in the full state, the output (FSA) of the AND circuit (AN22) becomes “High”.This causes the one-shot circuit (08
A pulse of ')-1ight'' is output from 9), which resets the flip-flop (FF15) via the OR circuit (OR13) and resets the flip-flop (FF17).

(FF14) is set, and the Q output of the flip-flop (FF14) becomes 'Hi (ill'), so that the counter (CO5) is released from the 1~ state, and the decoder ([)E3) is It becomes possible to output.The decoder (DE3) has a terminal (pl) of "
When 2.5m5ec passes slightly after I"igl+", a pulse of 'l-11 (111") is output from the terminal (τ5), and after 3.5m5ec, a pulse of "l-l igb" is output from the terminal (τ6). Output pulse, 6 m5e
When c elapses, a pulse of 'l-1+gh'' is output from the terminal (τ7), when g m5ec elapses, a 'High' pulse is output from the terminal (τ8), and when 11m5ec elapses, a 'High' pulse is output from (τ9). Therefore, the Q output of the flip-flop (FF I5) is 2.5 m after the terminal (pl) becomes
Until 5ec, it remains "'LOW" and (pl) becomes "Higb", and it is 2.5m5ec~3.5m5
ec") (igl+ °', 3Jmsec ~
9 m5ec becomes 'LOW' again, 9 l1ls
As ec passes, it becomes ") light" again and becomes 11.
When m5ec elapses, it becomes LOW again.This Q output is input to the OR circuit (OR2> in FIG. 9 via the terminal (INS>).

At this time, since the terminal (pl) becomes "1 (high"), the output of the AND circuit (AN24) becomes "Low" even in the fully charged state, and the output from the OR circuit (OR2) becomes "1 (high"). ) is in a state where a signal is output.

In ES mode, the output of the NOR circuit (NO3) is “H1”.
gh'', it is output as is from the AND circuit (AN21) and output to line (1) in the same manner as the signal described above.This signal is sent to the camera body as a signal for controlling the amount of light emitted as described above based on FIG. If this flash device is attached to a camera body that does not output a pulse indicating the mode on the line (α3), the terminal (E
S) is “low”, so when it becomes fully charged, the terminal (pl)
')light' is output to the terminal (FSA) and light is emitted.

The terminal (013) of the microcomputer (MC2) in FIG.
The terminal (011) is the terminal that becomes 'Higl+' in the parent-child light emitting mode. The terminal (012) is a terminal that becomes 'il igb' in the sequential emission mode and the post-emission mode.

(010) is a terminal that becomes "1igb" in simultaneous flash mode or single flash mode. Terminal (014) is "l-1-1i" in automatic light control mode, and "'" in manual setting mode. This is the terminal that becomes “LOW”.

In FIG. 9, (FLD) is a circuit that outputs a signal of the amount of light emitted in automatic light control mode and manual setting mode,
The output terminals (el) and (C2) of this circuit (FLD) and the output terminal (old) of the decoder (DE5) in Fig. 11,
Table 3 shows the relationship between (d2), (d3), light emission mode, and light emission m.

Table 3 As is clear from this table, when only 1/2 of the total light is emitted, the terminal (d2) of the decoder (DE5) is
+gh', and the 1- transistor (BT, 43) becomes conductive. The light emitted from the light emitting section (FLO2) is directly received by the phototransistor (PTI), and the output current of this phototransistor (PTl) is
When the output of the OR circuit (OR21) becomes '@ig++'' to prevent the OR circuit (LO2) from emitting light, the OR circuit (OR21)
20) becomes “low”, the transistor (
8T45) becomes non-conductive and is integrated by the capacitor (C15). When the integrating cylinder bar of the capacitor (C15) exceeds the potential determined by the resistors (R5) and (R7), the output of the comparator (AC3) is reversed to 'l-1-1i'.
One-shot circuit (0811), from 'l-1-1i°
A pulse of " is output, and the light emission is stopped by this pulse. When only 1/4 of the total light is emitted, the terminal (d3) becomes 1+g11" and the transistor (BT41) becomes conductive. And Photo 1 Helangista (PTl)
The output current is integrated by a capacitor (C13) whose capacity is half that of the capacitor (C15). Therefore, the light emission stop signal is half the light emission amount when the terminal (d2) is 'Highb'.In addition, in the case of full light emission and automatic 1FJI dimming, the OR circuit is activated when the terminal (dl) is 'High'. (OR20) remains 'High', the transistor (BT45) remains conductive, and the one-shot circuit (0811) does not output a pulse for stopping light emission.

First, the operation of parent-child light emission mode will be explained. In this case, the terminal (011) of the microcomputer (MC2) is “High”
becomes an OR circuit (OR15).

(OR17), (OR19) (D output 1fi ”H
t(lh" 1.C12. Therefore, at this time, the output of the AND circuit (AN51) becomes "'High" for 2.5 m5ec after the X contact (Sx) is closed, and the OR circuit ( The output (ST2) of OR21) is l-(high
” and the light emitting part (PuO2) emits light.During this light emission, in automatic light control mode, the AND circuit (AN65) is active, and the light emission stop signal from the camera body is sent through the terminal (p3). If there is an input deviation, the signal is processed by an AND circuit (
AN65), terminal (SF
3), and the light emission of the light emitting unit (PuO2) is stopped. In the manual setting mode, the AND circuit (AN63) is active, and the light emission stop signal from the one-shot circuit (0811) is sent to the AND circuit (AN63) and the OR circuit (
It is output to the terminal (SF3) via OR25) and stops the light emitting section (PuO2) from emitting light. Next, the X contact (SX
) has been closed for 3.5n+sec.
Until 11 seconds have elapsed, the AND circuit (AN55
)'s output (ST1) becomes 'l-1-1i', and the light emitting part (FLOI) emits light.Then, in automatic light control mode, the terminal (014) of the microcomputer (MC2) becomes '@igh'.
”, the light emission stop signal from the terminal (p3) is output from the AND circuit (AN67) to the terminal (SPl'),
The light emission of the light emitting unit (FLO1) is stopped. on the other hand,
In manual setting mode, the microcontroller (MC2) terminal (
014) is “'low”, so it is an AND circuit (AN
67) does not output a light emission stop signal and the light emission unit (FLO
I') is full emission. In addition, in this case, if the automatic dimming mode is selected, the second light emission stop signal from the terminal (p3) is output from the AND circuit (AN61) and the OR circuit (OR23).
), is output via the AND circuit (AN69), and is output to the terminal (
FDS) and is input to the dimming completion indicating circuit (INF).

In the simultaneous light emission mode or single light emission mode, the terminal (010) of the microcomputer (MC2') becomes @igh", and the output of the OR circuit (OR17) becomes "l-1igl+".
”. Therefore, after the X contact (Sx) opens,
．． Until 5m5ec, the output of the AND circuit (ΔN51) becomes l-1-1i'', and the output of the OR circuit (OR21) (
ST2) becomes “@ig!1”. This causes the light emitting part (PuO2) to emit light, and in automatic light control mode,
During this light emission, the light emission stop input from the terminal (p3) (
No. H changes from AND circuit (AN65) to OR circuit (OR25)
) to the terminal (SF3), and the light emitting part (PuO
The light emission of 2) is stopped. On the other hand, in manual setting mode, the pulse from the one-shot circuit (0811) is output to the AND circuit (AN63), the OR circuit (OR25), the terminal (ST2), and the light emitting part (PuO2).
The light emission is stopped. In this case, a "High" signal is not output to the terminal (ST1), and the light emitting section (FLOI)
) does not emit light. In addition, the light emission stop signal that is input from the terminal (p3) to the dimming completion display circuit (INF) during 2.5m5ec after the X contact (SX) is opened is sent to the AND circuit (AN59) and the OR circuit ( OR23), AND circuit (
AN69).

In the sequential light emission mode and first light mode, the terminal (01
3) becomes “High”’ and OR circuit (OR15),
(OR17), (OR19) output is “l-1-1i”
2.5m5 since the X contact (Sx) was opened.
The open terminal (ST2) up to ec becomes "H+g+1". As a result, the light emitting part (PuO2) emits light, and during this light emission, the terminal (O3) or the one-shot circuit (
The light emission is stopped by the light emission stop signal from 0811). In addition, the dimming completion display circuit (INF) has an X contact (SX).
The light emission stop signal that is input from the terminal (O3) from the time when 3.5m5ec has passed since the X contact (SX) is closed until 6m5ec has passed after the X contact (SX) is opened is sent to the AND circuit (AN61). , an OR circuit (OR23), and an AND circuit (AN69). Therefore, even if the first light does not reach 2/3 of the proper exposure, FDC display is performed if the sum of the first light and the second light becomes appropriate.

In the after-emission mode, the AND circuit (AN53) becomes active, and after the X contact (SX) is closed, 3.5m5
The AND circuit (A
The output of N53) becomes '@igh', and the light emitting part (
FLO2) emits light, and during this light emission, a light emission stop signal from the terminal (O3) or the one-shot circuit (0811) is output to the terminal (SF3'), and the light emission of the light emitting section (FLO2) is stopped. In addition, the dimming completion indication circuit (INF) is also displayed from the time when the light has passed by 3.5 m5ec from the opening of the X contact (Sx) to the time when the light has passed 13 m from the time when the X contact (SX) is opened.
A light emission stop signal is input from the terminal (O3) until 5 eC elapses. Note that the light emitting section (FLOI) does not emit light even in the first light and after light modes.

Next, based on FIG. 12, the dimming completion display circuit (INF>
I will explain about it. When a light emission stop signal for indicating completion of dimming is input from the output terminal (FDS) of the light emission control circuit (FTCI), the flip-flop (FF21) is set. At this time, in the ES mode, the terminal (ES) of the mode discrimination circuit (T1.C) in Fig. 9 is "Hi! Jh", so
The output of the AND circuit (AN71) becomes "low", and the counter (CO7) is in a reset state. Then, the time mode is set and the terminal ([S) is set to "'"
When it becomes “Low”, the output of the AND circuit (AN71) becomes “
l-1-1i'', the output of the inverter (IN20) becomes 'low''', and the FDC signal goes through the AND circuit (
AN35). Also, an AND circuit (AN71
) becomes °′1”Hgh++, the counter (C
The reset state of the counter (CO7) is released and the counter (CO7)
starts counting clock pulses (φ2) from the microcomputer (<MC2). Counter (CO7) terminal ([0
) outputs an 8Hz clock pulse, and the transistor (BT47) outputs a light emitting diode (L) at 8Hz.
Dl ) flashes and covers. Then, after 3 seconds have elapsed, the terminal (tl) becomes 'High', the flip-flop (FF21) is reset via the OR circuit (OR27), the counter (CO7) is reset, and the inverter (IN20) is reset. The output is “’ @ igl+
” and the light emitting diode (LDI) turns off.

Also, when the shooting interval is short, a light emitting diode (LD)
1) is displayed, the mode becomes ES mode, and the mode discrimination circuit (TIC) (7) terminal (ES) in Fig. 9 becomes "Hi! Ih".
N'; K Root, AND circuit (AN71) output is 1
It becomes “LOW” and the inverter (IN20) (7) output 1fi is “High”.

Further, the counter (CO7) is reset and the light emitting diode (LDl) is turned off. Also, the terminal (
When ES) becomes Hi (J11''), a pulse is output from the one-shot circuit (OS13) and the flip-flop (FF21) is reset.

Next, the operation of the microcomputer (MC2) shown in FIG. 9 will be explained based on the flow rates shown in FIGS. 13 and 14. In the CF mode, the mode discrimination circuit (TIC) terminal (
CF) becomes "'l-1igl+", a signal of "'l-1-1i" is input to the interrupt terminal (+1>) of the microcomputer (MC2), and the operation starts from step S3.

In step S3, interrupts to the terminal (1t) of the microcomputer (MC2) are enabled, and data to the terminal (SIN> is read based on the clock pulse from the terminal (O3) to the terminal (SCK>). This flash photography aperture value data (Δvf) is set in a predetermined register in the microcomputer (MC2).

Next, read the serial data (film sensitivity (ISv and exposure control mode)) in the same way and set it in the specified register of the microcomputer (MC2).Furthermore, read another byte of lens focal length data (fv) and set it in the specified register of the microcomputer (MC2). (MC2
) in the specified register. With the above steps, data from the camera body will be loaded. Next, data for counting a constant value (for example, 10s6C) is set in the internal counter, and an interrupt is generated when the counter reaches the set predetermined value. Next is the terminal (:113).

It is determined whether or not (N4) is "'@high", and if both are "'High", the automatic light control mode is set, so the process moves to step 815. On the other hand, at least one of the terminals (i13) or (i14) is
-ow”, it is determined in step 814 whether the exposure control mode read from the camera body is M mode.

If it is M mode, it is hand a setting mode, and S1
Move to step 8. On the other hand, if the flash device is not in the M mode, the flash device enters the automatic light control mode even if it is set to the manual fJJ tJ constant mode and moves to step 815. In step 815, an automatic display indicating that the automatic light control mode is in effect is performed, and the terminal (014) is set to 'High.
h”, flag AMF is set to “1”, and the process moves to step S21.

On the other hand, in step 818, a manual display is performed to indicate that the hand f/I constant mode is set, and the terminal (014)
is set to ``Low'', the flag AMF is set to ``0'', and the process moves to step 821.

From step S21, terminals (ilO), (ill
), the light emission mode is determined according to the input signal to (i12). Terminals (i12) and (ill) are High”
If so, it is the simultaneous light emission mode, and the simultaneous light emission mode is displayed in step S23, and the terminal (010) is connected to ")(
igh” Toshi T: Terminal (011), (012)
.

(013> is set to 'Low' and the process moves to step 834. Then, in step 834, the terminal (ilo) is set to 'Low'.
If it is "High", the light emitting part (FLO2) is in a frontal light state and it moves to step 83G. On the other hand, the terminal (ilo) is "1 o".
w”, it is in a bounce state, so a bounce display is performed and the process moves to step 860.

If the terminal (i12) is ")(igt+" and the terminal (ill) is "LOW", it is the first light, and in this case step 82
At 4, set the terminal (013) to l-(ight) to indicate that it is the first light mode, and then set the terminal ((NO>, (011),
(012) is set to "LOW" and the process moves to step S55. If the terminal (i12) is 'LOW' and the terminal (ill) is 'High', it is the after-emission mode,
At step 827, connect terminal (012) to 'l-1-1i'
The terminal (010
).

(011) and (013) are set to “Low”.
Move to step 34. Terminal (i12), (
ill ) is "LOW", only the flash 1ffi (I) is attached to the camera body directly or via the controller, and the process moves to step S29. In step S29, the terminal (ilo)
When the terminal (110) is "HIGH", the 6M light unit (FLO2) is in the front light state, and is in the paired light emission mode, and in step 830, the single light emission display state is established. is displayed, and the process moves to step S31.On the other hand, if the terminal (ilo) is "LOW", the light emitting part (FL, 02) of the flash device (I) is in the bounce state and the parent/child flash mode is activated. indicates that it is parent-child emission mode in step 8413, pμj child (011) is 'l-1-1i', terminal (0
10) , (012) , (013) 'low'
shall be. Then, based on the maximum light emission amount and minimum light emission amount of the light emitting unit (FLOl), the maximum value and minimum light emission amount IVM
, IVI11 is set, and the process moves to step 841.

In step 836, data on the illumination angle (this is the light emitting part (F
The illumination angle of LO2) is variable, and data corresponding to this illumination angle (ZD outputs) is taken in from the illumination angle data output circuit (ZD) and the illumination angle is displayed. Next, it is determined whether the flag AMF is 1'', and the flag AMF is
If is °'1", step 840; if °0'°, input terminal (i13).

The level of (i14) is determined. In the automatic light control mode or full light emission mode, the maximum light emission amount of the light emitting unit (FLO2) is set to lvyari, and the minimum light emission interval is set to Iv+n.

On the other hand, if G is turned off in full flash mode, the maximum flash output set at that time is set to IVM, and the minimum flash output is set to Ivn+.
As a result, the process moves to step 841. In step 341, it is determined whether or not an interchangeable lens is attached to the camera body. If no lens is attached, a message indicating that there is no lens is displayed, and the process moves to step 359. Here, if the interchangeable lens is not attached to the camera body, specific data is input to the flash device as the image value data Avf, and when the flash determines that this data has been input, the interchangeable lens is not installed. Once it is determined in step 841 that the lens is attached, the process moves to step S43, where IVM +Sv -Avf-DVM IVIIl+SV -Avf=Dvm ++ (15
), the maximum exposure is 11i! The distance DVM and the shortest shooting distance [)vm are calculated. next,
Determine whether the maximum shooting distance @ □ vm is shorter than the limit shooting distance Dvm determined by parallax, etc., and if D Vllll < [) VL, the maximum shooting distance [) vm is the limit. Shooting distance DVL
is adopted, and the process moves to step S52.

In the step S52, it is determined whether the flag AMF is 1'', and if it is "1" and it is automatic light control mode, the interlocking range is displayed from the maximum light emission (VM) and the minimum light emission lIvm,
If the flag AMF is "O°' and the manual setting mode is selected, the shooting distance for the appropriate exposure is displayed based on the maximum light emission flkIv bar.Then, based on the aperture value data Avf for flash photography (aperture value, After displaying the focal length based on the focal length data [V of the interchangeable lens and the film sensitivity based on the film sensitivity data 3v, the process returns to step 812, and the mode discriminating circuit (TIC ) terminal (CF) is “” H
When the interrupt terminal (it) becomes H+gh'', the operation from step S3 is performed again. In addition, in step S55, it is determined whether or not an interchangeable lens is installed in the same way as 841. If it is installed, the process moves to step S57, and if it is not installed, a message indicating that the lens is not installed is displayed and the process goes to step 859. Transition.

The modes in which the interlocking range or Wi shadow distance for proper exposure are displayed are when there is no bounce state in simultaneous flash, single flash, and after flash modes, and when in parent-child flash mode.
In the parent-child light emission mode, the interlocking range or shooting distance based on the light emitting unit (FLO1) is displayed. The interlocking range or shooting distance is not displayed when the light emitting unit (FLO2) is in a bounce state in the first light mode, simultaneous light emission, or after light emission. Incidentally, if a bounce state occurs due to simultaneous light emission, post-light emission, or single light emission, a bounce display is performed in step 335, and then the process moves to step 560.

Then, if there is a bounce during the post-emission, the probability that it will be correct is low, so a warning is issued and the process moves to step 855.

In FIG. 14, when power is supplied to the microcomputer (MC2), operations from step 370 are performed.

First, in step S70, the display on the display (FDPI) is turned off, the terminal (01G) is set to "
)light” and terminal (011).

(012) and (013) are set to "low" and the process moves to step 874.

In step 374, input terminal (it3), (+1
4)) and determines whether it is in automatic light control mode. If it is the automatic lighting mode, automatic display is performed, the terminal (014) is set to 'l-1ight', the flag AMF is set to 1", and the process moves to step S81.

In step 374, a manual display is performed to determine that the automatic light control mode is not set, and the terminal (014) is set to "'".
LOW”, flag AM14 is set to “O”, and the process moves to step 381. In step S81, l5O10 is set.
5v=5, which corresponds to 0, is set, and in step S82, a signal from the input terminal (+10) is determined to determine whether the light emitting unit (PLO2') is in a bounce state. And if it is in a bounce state, S9
After the bounce display is performed in step 4, the process moves to step 395. In step 882, the light emitting unit (FLO
88 when it is determined that 2) is in the front light state.
Proceed to step 3 and output the illumination angle data output circuit (ZD)
Import the beam angle data from. The illumination angle is then displayed based on that data. Next, the flag AMF is '1''
to determine whether automatic dimming mode is on. Then, in the automatic light control mode, the maximum light emission period IVM and the minimum light emission period 1tIvm are set based on the irradiation angle of the light emitting unit (PuO2). Then, the calculation IVM +3v -GVM 'Ivm +Sv=Gvm is performed, the maximum guide number QVM and the minimum guide number Qvm are displayed at 180100, and the process moves to step 895. On the other hand, if it is determined in step S85 that the AMF is 0'' and the automatic dimming mode is not set, the light emission interval IVM is set based on the set value signals from the terminals (i13) and (i14) and the illumination angle, and the GV
The calculation M=fvM+3v is performed, the maximum guide number GVM based on the set value is displayed, and the process moves to step 395.

In step S95, a message indicating that there is no lens is displayed to indicate that no data regarding the lens is sent from the camera body, and 15O100 is displayed, and the process proceeds to step S97.
Move to the next step. In steps 897, 98 and 99, it is repeatedly checked whether the setting state of the external setting means has changed, and if the setting state has changed, the process returns to step 870 and the above-described operation is performed again to switch the display state.

An interrupt signal is input from the terminal (CF) to the interrupt terminal (eye), and the interrupt signal is input from the terminal (CF) within a certain period of time (for example, 10 seconds) after the counter interrupt is enabled in step S11. If no signal is input, the microcomputer (MC)
2), an interrupt is generated by the internal counter, and the operations from step S70 are performed. Therefore, even if data from the camera body is no longer input, the display will be based on the data from the camera body for 1 osec.
As time passes, only data that can be displayed using only the values set on the flash device will be displayed.

Next, the flash device (If) or mouth 1 will be explained based on FIGS. 15, 16, and 17. FIG. 15 shows a specific example of the control circuit (PuO2) or (PuO3) in FIG. 1, and only the parts that are different from those in FIG. 9 are shown, and corresponding terminals are given the same symbols as in FIG. 9. (See Figure 9 for the same parts).

In the case of this flash device, there is only one light emitting unit (PuO3) or (PuO4), and the parent-child light emitting mode is not established. Therefore, in the FC mode, there is no need to output a signal indicating parent-child mode in bits b1 and 10, so the terminal of the mode discrimination circuit (TiG) <rl
>, <rio) outputs are directly connected to the OR circuit (O
R7), (OR9), and bits b1. blO
As a result, a 'Higb' signal is output.
The microcomputer (MC3') does not indicate the parent-child flash mode and is not provided with a terminal (011) that outputs a Higb'' signal.Furthermore, the operation of the light emission control circuit (FTC2) and the microcontroller (MC3') depends on the flash device ( Although this is different from 1), the different parts will be explained with reference to FIG. 17.

FIG. 16 shows only the parts that are different from FIG. 11 (see FIG. 11 for the same parts). First, in the simultaneous or single light emission mode, the microcomputer (MC3) terminal (0
10) becomes l Higl, -1, and the OR circuit (OR3
1) output becomes °'High. Therefore, the terminal (S
T4), from the time when the camera body's X contact (S
-1i” flip-flop (FF17) (11th
The Q output of the Q output of
O4) lfifa light. During the light emission, if the automatic light control mode is selected, a light emission stop signal from the terminal (p3) is output to the terminal (SF3) via the AND circuit (AN83) and the OR circuit (OR39), and the AND circuit ( A N
87) to the dimming completion display circuit (INF), and the light emitting part (PuO2> or (PuO2) shown in FIG.
4) The light emission stops and a light adjustment completion message is displayed. When in manual setting mode, one-shot circuit (0811) (11th
(see figure) is outputted via an AND circuit (AN85) and an OR circuit <0R39), and light emission is stopped.

In the early light mode, the terminal (013) of the microcomputer (MC3) in Figure 15 becomes ")light" and the OR circuit (OR circuit) is activated.
31) The output of (OR33) becomes "-Hlgl,u.Then, the Q output of the flip-flop (FF17) is outputted via the AND circuit (AN75) and the OR circuit (OR35), and the light emitting section (FLO3) or (FLO
4) emits light as soon as the X contact is closed. In this case as well, the light emission is stopped by the light emission stop signal that is input during the light emission. On the other hand, the dimming completion display circuit (INF
), in automatic dimming mode, 2.
The Q output of the flip-flop (FF19) which becomes "+-+ +gh" during 5m5ec is
81), is output from the OR circuit (OR37), and a light emission stop signal is input from the terminal (p3) during this period.

In the after-emission mode, the terminal (012) is ")light"
”, and the output of the OR circuit <0R33) is +-++ah
”.

Then, after 3.5m5ec has elapsed from the time when the is output and light emission starts. Then, the light emission is stopped based on a light emission stop signal input from the terminal (p3) or the one-shot circuit (0811) during this light emission. At this time, if the automatic dimming mode is selected, the stop signal inputted from the terminal (p3) during the light emission is passed through the AND circuit (AN87) to the dimming display section (
INF).

FIG. 17 is a flowchart of the operation of the microcomputer (MC3) in FIG. 15, showing only the parts that are different from the flowchart in FIG. 13, and the same parts as in FIG. 13 will be explained with reference to FIG. 13. .

From 821, terminals (ill), (
The light emission mode is determined by looking at the output state of N2). If the terminals (N2) and (ill) are both 'High', it is the simultaneous light emission mode, and the simultaneous light emission mode is displayed in step sioi, and the terminal (010) is set to ')-1ig11' in step 5105. terminal <012)
.

(013) is set to "LOW", and the process moves to step 334, where it is determined whether or not there is a bounce state. Terminal (A12)
is "d)l igl, II and the terminal (ill) is "l
ow", it is the first light mode, and the first light mode is displayed in step 5102, and the terminal (013) is set to "
@igh”, terminals (010) and (012) are ‘LO’
When the terminal (A12) is "LOW" (the terminal (A12) is "LOW" (the terminal 111 is "OFF-1i"
gh”, displays the after-emission mode, and connects the terminal (012
) to 'l-1igl+'', terminal (010), <0
13) is set to ``LOW'' and moves to step 334. If both terminals (A12) and (ill) are set to ``ow'', one line light emission mode is displayed in step 104, and step 5105 is executed. Add 9 lines to the step.

FIG. 18 is a diagram showing a specific example of the internal circuit (CNC) of the flash controller (ff>).

(TiG) is a mode discrimination circuit, which is the same as the mode discrimination circuit of FIG. 9 whose specific example is shown in FIG. 10, and is designated by the same reference numeral. First, the operation in FC mode will be explained. First, the terminal (fO) of the mode discrimination circuit (TIC) ~
While (f5) is °' Hi9h, it is a NOR circuit (NOll
), the output of (NO15) becomes “LOW” and the AND circuit (AG2).

(AG64), (AGI), and (AG65) become disabled, and data from lines (A2) and (α12) can be read. Then, the signal from the line (North 2) is output to the terminal (r21) via the transistor (8T53) and inverter (IN27), and the signal from the line (Q 12) is output to the terminal (r21).
The signal is output to the terminal (r22) via the 1-transistor (BT69) and the inverter (IN31). And bits bo, b2 . from terminal (r21). b
3. The b5 signal is a D flip-flop (DFll)
, (DF13) , (DF15) .

(DF17) is latched. On the other hand, pits bo, bl, b2. from the terminal (r22). b3. The b5 signal is a D flip 70 knob (DF19), (DF21)
, (DF23), (DF25), and (DF27). The switches (88) are the same number if the sequential light emission mode is selected, and are opened if the simultaneous light emission mode is selected. D flip 70 knobs (11 to D).

(D F 19) both have their Q outputs “)−1
If it is igb, it means that two flash devices are installed, and the output of the AND circuit (AG47) is '
) lil;i11″′.Meanwhile, at least one D flip-flop (DFll) or (D l”19
) is “low”, the two flash devices are not connected, and the AND circuit (AG47
) is 'Low', and the output (α-0) of the AND circuit (AG45) and the output of the AND circuit (AG59) are both 'LOW'.

D flip-flop (DF17) and (DF27)
is a flip 70 tube that latches the distinction signal at bit b5, but when both input the 'low' signal, both the two flash devices are compatible with this system, and at this time, the AND circuit <AG63) is”
)-1igh ++ signal is output. On the other hand, at least one of the two flash devices is connected to the terminal (QJ2
), the output of the AND circuit (AG63) will be "LOW".If both of the AND circuits (AG61) are compatible with this system, When the sequential mode is selected in the device, the output of the AND circuit (AG61) is "'"
On the other hand, if at least one flash device is not compatible with this system, the sequential mode is selected and the output of the AND circuit (AG61) is 'lOW' even if the switch <SS> is open. It has become. Then, when two flashes [2 are installed and the AND circuit (AG47) is set to 1right, the AND circuit <A
If the output of G61) is "High", the mode becomes sequential light emission mode, and the output (G0) of the AND circuit (AG45) becomes 'l-
1-1i". On the other hand, even if the output of the AND circuit (AG47) becomes 'High', the output of the AND circuit (AG61)
When the output becomes 1ow'', the output of the AND circuit (ΔG59) becomes ``High'' and the simultaneous mode is established.

In the sequential mode, when the terminal (f6) of the mode discrimination circuit (Tic) is ')high', the AND circuit (AG5
9) is sent to the AND circuit (AG
41), OR circuit (OR47), (OR43).

(OR41), AND circuit (AGl), transistor <
B T 5? ) to line (Q,2). And the terminal (f7) of the mode discrimination circuit (Tic)
When becomes ``High'', the ``High'' signal from the AND circuit (AG47) goes to the AND circuit (ΔG43).
, :t7[8(OR47), (OR43), (OR41
).

AND circuit (AG2) l-transistor (BT55)
It is output to the line (琵2) via. Therefore, the flash device directly connected to the hot flash of the camera body receives an "oi" signal indicating the after-emission mode.

On the other hand, when the terminal ([6) is 'l-11g11'', '
The ")ligl+" signal from the AND circuit (AG47) is an AND circuit (AG55), an OR circuit <0R51),
It is output to the line (Part 2) via the AND circuit (AG64) and the transistor (BT65). When the terminal (t7) of the mode discrimination circuit (TIC) becomes 'H+gh', the 1ow'' signal from the AND circuit (AG59) is output to the AND circuit <AG57), the OR circuit (OR51), the AND circuit (AG65), and the I - Output to line (G12) via transistor (BT67). Therefore, a signal of 10'', ie, first light mode, is input to the flash device directly connected to the flash controller.

In the simultaneous flash mode, the AND circuit (A G 47)
, (A, G59) are both "'l-(+9+1°
', and therefore, the AND circuit (AG41), (AG
43).

From (AG55) and (AG57), the terminal (f(5)
.

When (f7) is "l-(ight"), ' l-1ight
” signal is output and both flash devices are sent this signal. That is, both flash devices are
11" simultaneous flash mode signal is sent. When neither the sequential mode nor the simultaneous mode is installed, that is, when no flash device or only one flash device is installed, the output of the AND circuit (A G 47) is LOW, and the output of the AND circuit (ΔG59) also becomes 1ow. Therefore, bit b6. As for b7, a signal of "'oo" is output to the lines (G2) and (α12), and the flash device that reads this signal determines that only the flash device that it read is attached to the camera.

Next, terminals (f8) to (f
15) will explain data transfer during “H+gh”. First, when the Q output of the D flip-flop (DF19) is "l-1-1i", that is, when no attachment signal is input from the line (α12), the terminal (G3) is l-1
-1i+", and during this time the output of the OR circuit (ORJ6) is ')-figh'", so the AND circuit (
The output of AG13) becomes “High”.

Therefore, the output of the NOR circuit (NOll) is 'L OW'
”, AND circuit <AG2), (AGl) is in a disabled state and line (α2) is in a high impedance state. When the mounting signal is input from both lines (α2) and 112), AND circuit (AG47) The output of 'l-(
igh", and the AND circuit (AG21) becomes active. First, the "l-1tgh" signal of the terminal (f8) is transferred from the OR circuit (OR49) to the AND circuit (AG21), the OR circuit (OR43), and the OR circuit (OR41). , AND circuit (AG
2), the line (North 2
) is output. This is the attachment signal of bit b8 shown in Table 1. Mode discrimination circuit (TIC) terminal (f9)
When becomes °'l-(high", the D flip-flop (
A signal obtained by inverting the output (α6) of the OR circuit (OR55) which inputs the Q outputs of DF27) and (DF17) is output from the AND circuit (AG33) and output to the line (α2). The output (α6) of the OR circuit (OR55) is small (if a flash device compatible with this system is installed on both sides, it will be "@i'gh", and by inverting this and outputting it, at least one side will be output) If a flash device compatible with this system is installed on
The signal “OW” is output from the line (magazine 2). This is the discrimination signal shown by bit b9 in Table 1. The terminal (rlo) of the mode discrimination circuit (Try) is output from the line (magazine 2).
) light”, the output of the AND circuit (AG45) (
A signal obtained by inverting α0) is output from the AND circuit (AG35). The AND circuit (AG47) becomes "'l-1-1i" in the sequential light emission mode. Therefore, this signal becomes the sequential signal shown by bit b10 in Table 1. The terminal (fll) of the mode discrimination circuit (TIC) is “High”
”, the output (α2) of the AND circuit (AG49) is output from the AND circuit <AG37) and is output to the line (north 2).The AND circuit (AG49) is connected to the D flip 70 tube (DF13 , (DF23), and each 7-lip 70-tub latches the fullness signal sent from the flash device at bit b2.

Therefore, the AND circuit (AG49) becomes ")light" when both flash devices are in the full state, and this signal becomes the full state signal shown by bit b11 in Table 1. The terminal (N2) of the mode discrimination circuit (TIC) is “’H”
When it becomes igh ++, the AND circuit (AG39) becomes active, and a signal obtained by inverting the output (α5) of the OR circuit (OR53) is output to the line (AG2). OR circuit (
OR53) is D flip 70 knob (DF15), (D
With the Q output of F25) as input, the flip-flop (D
F15) and (DF25) latch the FCC signal at hit b3 from each flash device. Therefore, F on bit b3 from at least one flash device
When a DC signal is being output, the output of the OR circuit (OR53) becomes 'l-(high'), which is inverted to 'low' and output to the line (cL2').This signal is shown in Table 1. This becomes the FDC signal of bit b12.Terminals (f13), B14) of the mode discrimination circuit (TIC).

When (f15.) becomes 'High', the line i2 remains 'LOW', which corresponds to bit b13゜b in Table 1.
14 and b15, these are reserved bits.

The attachment signal is input from the line (212), and the Q output (α1) of the D flip-flop (D F 19) is "')
light”, no installation signal is input from the line (A2), and the Q output of the D flip 70 tube (DFll) is
If it is “LOW”, the AND circuit <AG51)
The output of “Htgh” becomes “Htgh”, and the AND circuit (A G 1
9) becomes active. First, the mode discrimination circuit (Tic)
When the terminal (f8) is 'Highll', this signal is directly sent to the OR circuit (OR45) and the AND circuit (AG19).
, are output from the off circuits (OR43) and (OR41) and are output to the line (Q2). This becomes the attachment signal for bit b8. When the terminal (f9) becomes “) light”, the Q output (α8) of the D flip-flop (DF27)
) is output from the AND circuit (A G 27). This signal is a discrimination signal for bit b5, and this signal is output to the line (Q2) and becomes a discrimination signal for bit b9. When the terminal (flo) becomes '@1g11'', the Q output (α4) of the D slip flop (DF, 21) is output from the AND circuit (A G 27). This signal is sent to the line (fL12) side. If the attached flash device is in the parent-child flash mode, it is ``LOW'', and if it is in the single flash mode, it is ``HIGH''.

This signal is applied to the terminal (ri) of the mode discrimination circuit (TIC).
o) is output to the line (α2) at the timing of “'1-l1g1+” and becomes the sequential light emission mode signal shown by bit b10 in Table 1. Mode discrimination circuit (TI
When the terminal (fll) of C) becomes Hi, L, II, the AND circuit (AG29) outputs a D flip 70 tube (DF
The Q output (α3) of 23) is output. This signal is the fullness signal bit b2 from the line (12) and is the fullness signal bit b2 from the terminal (f
When ll ) is ``High ++, line (
α2), which is not shown in Table 1, causes a beep! ~b11 becomes a fullness completion signal. Mode discrimination circuit (TIC) terminal (f
12) becomes ')light', the D flip-flop (
Q output (α7) of DF25) is AND circuit (AG31)
is output from. This flip 70 knob (DF25) is bit b12 and the F input from line (fL12)
This is a DC signal, and this signal is used by the mode discrimination circuit (TIC).
) is output to the line (north 2) at the timing when the terminal (fl'2) becomes "High", resulting in an FDC signal of pitch 1-b12. Mode discrimination circuit (Tic) terminal (
f13), (f14), (N5) are 'l-1
-1i'', the line (see 2) is 'low'' and is a reserved bit.

In the CF mode, the mode discrimination circuit (TIC) terminal (
CF) becomes °'High, so the NOR circuit (NOI
I) outputs a 'LOW' signal, and the AND circuit (A
G2>, (AGl) becomes disabled, and transistors 1 to (BT53) become conductive or non-conductive depending on the signal from the line (bruise 2), and the inverter (IN2
The signal from the line (α2) is output from the output (r21) of 7). And the terminal (CF> is 'l-1-1i
”, the AND circuit (AG53) becomes active, and the signal from the terminal (r21) becomes the AND circuit (AG53).
), OR circuit (OR51), AND circuit (AG(34)
, (AG65), transistor (BrO3), (Br
O3) to line <QJ12). Therefore, data from the camera body is output from line (include 2) to line (912) via the flash controller, and is read into the flash device each time.

When in ES' mode, t, t, D flip 70 knobs (D
If the installation signal is not latched in F19), the Q output (α3) is “l-(high”) and the terminal (ES) is “I-”.
1igt+', so the AND circuit (A G 13
) output is I Higl, 11, NOR circuit (N 01
1) Output is "low", transistor (BT55)
, (BT57) are in a non-conductive state. If the Q output (α1) of the D flip-flop (D F 19) latches the attachment signal, the terminal (ES') becomes °'l-
(high”, the AND circuit (AG23) becomes active. Therefore, the signal from the flash device that is input to the line (north 12) is input via the transistor (BrO9) and inverter (IN31), and the terminal ( r22), but this signal is output from the AND circuit (AG23) and output to line (incl. 2).Therefore, the integral synchronized with the light emission output from the flash device mentioned above to line (α12). A control signal is output to line (α2) via the flash controller 1-roller.

In the sequential light emission mode, the output (α0) of the AND circuit (AG45) becomes Hight+”
II) becomes active. And the X contact on the camera body (
When Sx) is closed and the line (λ1) becomes "LOW", the 1-transistor (BT59) becomes conductive and the terminal (
rl) goes High.At this point, the flip-flop (FF23) is in the 1- state, so
When the terminal (rl) becomes 'High', the output of the AND circuit (AG11) becomes 'l-1-1i', the counter (COll) is released from the reset state, and
COll) is the clock pulse (φ
3) Count. Then, when the X contact (SX) is opened and 6 +n5ec is shed, the terminal (re) becomes ')
If both flash devices are fully charged and the terminal (α2) is “l-1high”, the AND circuit (Δ
The output of 088) becomes "Highl, Il", the transistor (BT7L) becomes conductive, and the line i21 becomes 'L O
W". As a result, the flash device <Il[) shown in FIG. 1 emits light. That is, the flash device ff1
After (1) emits light and then (■) emits light to achieve proper exposure, the flash device (III) emits light. When the flip-flop (FF23) is set, the output of the AND circuit (AG71) becomes '1 ow' and the counter (Coil) is reset. Then, the X contact (Sx) is opened and the transistor (BT59) becomes non-conductive. When the terminal (rl) falls to LOW, a pulse is output from the one-shot circuit (OS 17), and the flip-flop (FF23) is turned on and returns to its initial state.

When in multi-flash mode, the flash device is set to bits b8-b.
The flash controller does not output the signal 1.5, but as described above, if both flash IIs are in the fully charged state, the flash controller outputs the "high" signal, and if at least one is not in the fully charged state, it outputs the "low" signal ( bll) is output to the line (QJ2).This signal is read by the camera body as a fullness signal, but also by the flash device, it is read by a flip-flop (FF2) to determine whether or not to emit light. , the flash device directly connected to the flash controller 1-○-
When it is determined that both are fully charged in the multi-light mode, the output of the AND circuit (A086) becomes ") (igb"'), and when the terminal (fll) becomes 'Higb', the AND circuit (AG92) and the OR The output of the circuit (OR72) is H
This signal is output to the line (α12) and sends a signal to the flash device to enable light emission.On the other hand, if at least one flash device is not in a full state,
Since the output of the AND circuit <AG8G) is ``low'', a ``LOW'' signal is output to the line (Q12), and a signal indicating that light should not be emitted is sent to the 7 Lascico device. Also, when not in multi-light mode, inverter 1
The output of N50) becomes ')l igl+'', and the flash device connected to controller 1 to roller is fully charged.
If the terminal (α9) is High and TI, the terminal (tii)
・When becomes 'High', the output of the AND circuit (Ag90) becomes "'l-1igt+", the AND circuit (A
The output of G90) becomes 'l(high'). Therefore,
This "'')light" signal is an OR circuit (OR72)
, (OR51) to the line (magazine 12), and is read by the flash device, so that the flash device becomes ready to emit light. On the other hand, the flash device is not fully charged and the D flip-flop (DF23) is
If the signal w'' is latched and the terminal (α9) is “LOW”, when the terminal (111) becomes “High”, a “Low” signal is output to the line (α12),
The flash device reads this signal and becomes unable to emit light.

The output of the NOR circuit (N O13) is the terminal (FC).

(When DF and (ES) are 'LOW', that is, in the timing mode, it becomes 'l-(high'). Also, if the flash device is not installed on the line (α12) side and the terminal is closed α3) is “Hi9h”, the AND circuit (, A
The output of the NOR circuit (NOll) becomes 'Low', and both the transistors (BT55) and (BT57) become non-conductive.

On the other hand, the flash device is installed at '4A on the line (QJ12) side.
If it is, the terminal (α1) becomes “)(high” and the AND circuit (AG17) becomes active.Then, the fullness signal input from the line (α12) at bit b2 is input to the D flip-flop. If the terminal (α9) is latched by the pin (DF: 23) and is “High”, the AND circuit (AG 1
7) becomes "@igh" during the period state. Therefore, when the 7 lash device on the line (α12) side outputs a fullness signal, the controller is in the "High" state during the timing state.
Outputs the signal to line (incl. 2).

Effects of the Invention As described above, according to the present invention (-), the display operation of the display means for displaying the interlocking range based on the flash unit's own light emission is selected as the sequential light emission mode in which light is emitted sequentially in cooperation with other flash devices. When the flash device is set to emit light before the other flash devices mentioned above, the display operation is disabled, and the display operation is performed in other cases. The interlocking range is displayed only by the flash device (fllll, the flash device whose light emission is controlled to ultimately obtain the proper exposure), and the displayed value guarantees at least the proper exposure even when there is almost no amount of light irradiated by the device that provides the first light. This is a very useful value.Furthermore, since the interlocking range is not displayed in a flash device that emits light first, it also has the advantage that the order of light emission can be easily confirmed visually.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the overall configuration of a flash photography system to which the present invention is applied, and Figure 2 is a microcomputer (
3 is a flowchart showing a specific example of the flash status display set in step #38 in FIG. 2, and FIG. 4 is a flowchart for explaining the operation of the MCI), FIG. FIG. 5 is a flowchart showing the operation for flash light calculation of step #42 in FIG. 2, and FIG. 6 is a flowchart showing the operation for step #42 in FIG. 2.
FIG. 7 is a circuit diagram showing a specific example of the input/output controller (IOC) in FIG. 1, and FIG.
A circuit diagram showing a specific example of the light emission open control circuit (FST) shown in the figure,
FIG. 9 is a circuit diagram showing a specific example of the control circuit (FLCI) in the flash unit @(I) in FIG.
Figure 10 shows the mode discrimination circuit (TIC>
A circuit diagram showing a specific example of, FIG. 11 is a circuit diagram showing a specific example of the luminescence amount i in FIG.
A circuit diagram showing a specific example of the IJ ta11 circuit (FTo, 1), FIG. 12 is a circuit diagram showing a specific example of the dimming completion indicating circuit (INF) in FIG. 9, and FIGS. 15 is a flowchart for explaining the operation of the microcomputer (MC2) shown in the figure.
II) control circuit (FLC2) and (FLC
3). Figure 1θ is a circuit diagram showing a specific example of the main part of the light emission control circuit (FTo2) in Figure 15. Figure 17 is a circuit diagram of the microcontroller (MC3") in Figure 15. A flowchart showing the main parts of the operation, and FIG. 18 is a circuit diagram showing a specific example of the internal circuit (CNC) of the flash controller shown in FIG. 1. ■: Camera body, ■, ■: Electronic flash light emitting device. ■: Flash controller, MC1, MC2, MC1
: Microcomputer, FTCI, FTo2 : Light emission amount control means, 88,010: First detection means, 012.013: Second
Detection means, FDPI, FDP3: Display means. Applicant Minolta Camera Co., Ltd. WJtS Figure 16 Continuation of page 1 [phase] Inventor Hiroshi Hosomizu Inside Azuchicho Camera Co., Ltd., Higashi-ku, Osaka City

Claims (1)

[Claims] 1. In an electronic flash light emitting device equipped with a light emitting amount control means that stops emitting light when the integral value of the reflected light from the subject reaches a predetermined value, sequential light emission in which light is emitted one after another in cooperation with other electronic flash light emitting devices a first detecting means for detecting whether a mode is selected; and a second detecting means for detecting whether a pre-light state in which light is emitted before the light emission of the above-mentioned electronic flash light emitting device is selected. Based on the detection means, photographic aperture value, film sensitivity, and predetermined or set light output amount of the own light emitting unit, data regarding the range or limit of the subject distance that can give an appropriate exposure by light emission is determined, and the data is calculated. A display means that performs a display based on data, and a display operation of the display means is prohibited when the first and second detection means respectively detect that the sequential light emission mode and the first light state are selected; A display device for an electronic flash light emitting device, comprising a display control means for permitting a display operation in the case of.