JP2574902B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2574902B2
JP2574902B2 JP1242191A JP24219189A JP2574902B2 JP 2574902 B2 JP2574902 B2 JP 2574902B2 JP 1242191 A JP1242191 A JP 1242191A JP 24219189 A JP24219189 A JP 24219189A JP 2574902 B2 JP2574902 B2 JP 2574902B2
Authority
JP
Japan
Prior art keywords
thermal expansion
substrate
coefficient
expansion coefficient
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1242191A
Other languages
Japanese (ja)
Other versions
JPH03105954A (en
Inventor
正英 岡本
一二 山田
太佐男 曽我
明 田中
信之 牛房
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1242191A priority Critical patent/JP2574902B2/en
Publication of JPH03105954A publication Critical patent/JPH03105954A/en
Application granted granted Critical
Publication of JP2574902B2 publication Critical patent/JP2574902B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素子を搭載した半導体装置における
素子搭載用基板及びその製造方法に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element mounting substrate in a semiconductor device having a semiconductor element mounted thereon and a method of manufacturing the same.

〔従来の技術〕[Conventional technology]

従来の半導体装置には、熱膨張係数の異なるSi素子と
GaAs素子同一基板上に搭載するものはなく、Si素子のみ
またはGaAs素子のみを搭載していた。
Conventional semiconductor devices have Si elements with different coefficients of thermal expansion.
No GaAs element was mounted on the same substrate, only the Si element or only the GaAs element was mounted.

また、特開昭63−111659号公報に記載のように、Si素
子の上にGaAs素子を形成していた。また、従来の素子搭
載用基板は、素子の熱膨張係数とモジユール基板の熱膨
張係数の間の均一な熱膨張係数を有する基板であつた。
Further, as described in JP-A-63-111659, a GaAs device is formed on a Si device. Further, the conventional element mounting substrate has a uniform thermal expansion coefficient between the thermal expansion coefficient of the element and the thermal expansion coefficient of the module substrate.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上記従来技術は、Si素子とGaAs素子を別別の基板上に
搭載していたため、半導体素子間の配線長が長くなり、
信号伝播遅延が大きいという問題があつた。
In the above prior art, since the Si element and the GaAs element are mounted on different substrates, the wiring length between the semiconductor elements becomes longer,
There is a problem that the signal propagation delay is large.

またSi素子の上にGaAs素子を形成した場合には、Siと
GaAsの熱膨張係数が異なるため、Si部とGaAs部の接続信
頼性が低く、温度サイクルによるはがれ、破壊が生じや
すいという問題があつた。
When a GaAs element is formed on a Si element,
Since the thermal expansion coefficients of GaAs are different, there has been a problem that the connection reliability between the Si portion and the GaAs portion is low, and the GaAs is easily peeled off and broken due to a temperature cycle.

本発明の目的は熱膨張係数の異なる複数の種類の素子
を素子間の配線長を短かく、信頼性を良く基板上に搭載
することにより、信号伝播遅延を小さくすることにあ
る。いいかえると、熱膨張係数の異なる複数の種類の素
子を同一基板上に近接して信頼性良く搭載すること及び
素子搭載用基板を提供することにある。
An object of the present invention is to reduce signal propagation delay by mounting a plurality of types of elements having different thermal expansion coefficients on a substrate with a short wiring length between the elements and high reliability. In other words, it is to provide a plurality of types of elements having different thermal expansion coefficients close to each other on the same substrate with high reliability and to provide an element mounting substrate.

本発明の他の目的は、基板の上に基板の熱膨張係数と
異なる熱膨張係数を有する素子を信頼性良く搭載するこ
とにある。
Another object of the present invention is to reliably mount an element having a thermal expansion coefficient different from that of the substrate on the substrate.

〔課題を解決するための手段〕[Means for solving the problem]

上記目的を達成するために、熱膨張係数の異なる複数
の成分からなり、該成分の配合比が少しずつ異なる複数
枚のグリーンシートを積層,熱圧着,脱バインダ,焼結
し、厚さ方向に熱膨張係数の傾斜を有する基板を作製す
る。熱膨張係数の異なる複数の種類の半導体素子のうち
最も熱膨張係数の小さい素子の熱膨張係数以上かつ最も
熱膨張係数の大きい素子の熱膨張係数以下の熱膨張係数
を有するモジユール基板上に、前述の方法で作製した、
モジユール基板側から素子側に行くに従つて、熱膨張係
数を該モジユール基板の熱膨張係数の値から、各素子の
熱膨張係数の値まで逐次変化させた素子搭載用の基板を
搭載し、その上に各素子を搭載したものである。
In order to achieve the above object, a plurality of green sheets comprising a plurality of components having different coefficients of thermal expansion, each having a slightly different mixing ratio of the components, are laminated, thermocompressed, debindered, sintered, and then sintered in a thickness direction. A substrate having a slope of a coefficient of thermal expansion is manufactured. On a module substrate having a thermal expansion coefficient equal to or higher than the thermal expansion coefficient of the element having the lowest thermal expansion coefficient and equal to or lower than the thermal expansion coefficient of the element having the highest thermal expansion coefficient among a plurality of types of semiconductor elements having different thermal expansion coefficients, Prepared by the method of
As going from the module substrate side to the element side, a substrate for mounting an element is mounted in which the coefficient of thermal expansion is sequentially changed from the value of the coefficient of thermal expansion of the module substrate to the value of the coefficient of thermal expansion of each element. Each device is mounted thereon.

また、複数の種類の半導体素子のうちの1種類の半導
体素子の熱膨張係数に等しい熱膨張係数を有するモジユ
ール基板上に、その1種類の半導体素子のみは直接搭載
もしくは該半導体素子および該モジユール基板の熱膨張
係数に等しい熱膨張係数を有する素子搭載用基板を介し
て搭載し、他の半導体素子は該モジユール基板上に、モ
ジユール基板側から素子側に行くに従つて、熱膨張係数
を該モジユール基板の熱膨張係数の値から、各素子の熱
膨張係数の値まで逐次変化させた素子搭載用基板を介し
て搭載してもよい。
In addition, on a module substrate having a thermal expansion coefficient equal to the thermal expansion coefficient of one of a plurality of types of semiconductor elements, only the one type of semiconductor element is directly mounted or the semiconductor element and the module substrate are mounted. The other semiconductor elements are mounted on the module substrate via the element mounting substrate having a coefficient of thermal expansion equal to the coefficient of thermal expansion of the module. The components may be mounted via element mounting substrates that are sequentially changed from the value of the thermal expansion coefficient of the substrate to the value of the thermal expansion coefficient of each element.

また前述の手段において、該モジユール基板と該素子
搭載用基板の一部もしくは全部を作製時に一括積層して
1つの基板とし、その上に素子を搭載してもよい。
Further, in the above-described means, a part or all of the module substrate and the element mounting substrate may be collectively laminated at the time of manufacturing to form one substrate, and the element may be mounted thereon.

また複数の種類の半導体素子のうち最も熱膨張係数の
小さい素子の熱膨張係数以上かつ最も熱膨張係数の大き
い素子の熱膨張係数以下の熱膨張係数を有するモジユー
ル基板上に、該モジユール基板の熱膨張係数の値と各素
子の熱膨張係数の値の間の熱膨張係数の値を有する素子
搭載用基板をそれぞれ搭載し、その上に各素子を搭載し
てもよい。
In addition, on a module substrate having a thermal expansion coefficient equal to or higher than the thermal expansion coefficient of the element having the lowest thermal expansion coefficient and equal to or lower than the thermal expansion coefficient of the element having the highest thermal expansion coefficient among a plurality of types of semiconductor elements, An element mounting substrate having a thermal expansion coefficient between the value of the expansion coefficient and the value of the thermal expansion coefficient of each element may be mounted, and each element may be mounted thereon.

また、複数の種類の半導体素子のうちの1種類の半導
体素子の熱膨張係数に等しい熱膨張係数を有するモジユ
ール基板上に、その1種類の半導体素子のみは直接搭載
もしくは該半導体素子および該モジユール基板の熱膨張
係数に等しい熱膨張係数を有する素子搭載用基板を介し
て搭載し、他の半導体素子は、該モジユール基板上に、
該モジユール基板の熱膨張係数の値と各素子の熱膨張係
数の値の間の熱膨張係数の値を有する素子搭載用基板を
それぞれ搭載し、その上に各素子を搭載してもよい。
In addition, on a module substrate having a thermal expansion coefficient equal to the thermal expansion coefficient of one of a plurality of types of semiconductor elements, only the one type of semiconductor element is directly mounted or the semiconductor element and the module substrate are mounted. Mounted via an element mounting substrate having a thermal expansion coefficient equal to the coefficient of thermal expansion of the other semiconductor elements, on the module substrate,
An element mounting substrate having a coefficient of thermal expansion between the value of the coefficient of thermal expansion of the module substrate and the value of the coefficient of thermal expansion of each element may be mounted, and each element may be mounted thereon.

また前述の熱膨張係数が均一な素子搭載用基板の上
に、該素子搭載用基板の熱膨張係数の値と各素子の熱膨
張係数の値の間の熱膨張係数の値を有する素子搭載用基
板をさらにそれぞれ1ケずつもしくは複数搭載し、その
上に各素子を搭載してもよい。
Further, on a device mounting substrate having a uniform thermal expansion coefficient as described above, a device mounting device having a value of thermal expansion coefficient between the value of the thermal expansion coefficient of the device mounting substrate and the value of the thermal expansion coefficient of each device. One or more substrates may be further mounted, and each element may be mounted thereon.

また、素子搭載用基板の厚さ方向に熱膨張の傾斜を設
ける際、傾斜は直線的でなく、実際に素子を搭載し作動
させたときの該素子搭載用基板の厚さ方向の熱応力分布
が等しくなるように設けた方がより良い。
Also, when providing a gradient of thermal expansion in the thickness direction of the element mounting substrate, the gradient is not linear, and the thermal stress distribution in the thickness direction of the element mounting substrate when the element is actually mounted and operated. It is better to provide them so that

また、モジユール基板と熱膨張係数の傾斜を有する素
子搭載用基板の一部もしくは全部を作製時に一括積層し
て1つの基板とするには、同組成のグリーンシート複数
枚を積層した上に、前述の熱膨張係数の値を逐次変化さ
せた複数枚のグリーンシートを積層,熱圧着後,脱バイ
ンダ,焼結して作製すればよい。
Also, in order to form a single substrate by laminating a part or all of the module mounting substrate having a gradient of thermal expansion coefficient with the module substrate at the time of fabrication, a plurality of green sheets of the same composition are laminated and A plurality of green sheets in which the value of the thermal expansion coefficient is sequentially changed may be formed by laminating, thermocompression bonding, binder removal, and sintering.

また上記の手段を用いて多層配線基板を作製する場合
には、グリーンシートを積層する前に、該グリーンシー
トの所定位置に穴あけ、導体印刷後、上記手段を用いて
作製すればよい。
When a multilayer wiring board is manufactured by using the above-described means, a hole may be formed in a predetermined position of the green sheet before laminating the green sheet, and after the conductor is printed, the multilayer wiring board may be manufactured by using the above-described means.

また、基板の上に基板の熱膨張係数と異なる熱膨張係
数を有する素子を搭載するには、基板の上に、前述の方
法で作製した、熱膨張係数の値を厚さ方向に、基板の熱
膨張係数の値から素子の熱膨張係数の値まで逐次変化さ
せた素子搭載用基板を搭載し、その上に素子を搭載すれ
ばよい。
To mount an element having a coefficient of thermal expansion different from the coefficient of thermal expansion of the substrate on the substrate, the value of the coefficient of thermal expansion prepared by the above-described method is set on the substrate in the thickness direction. It is sufficient to mount an element mounting substrate which is sequentially changed from the value of the coefficient of thermal expansion to the value of the coefficient of thermal expansion of the element, and mount the element thereon.

〔作用〕[Action]

上記方法で作製した半導体装置では、半導体素子とモ
ジユール基板との間に、熱膨張係数の値をモジユール基
板側から素子側に行くに従つて、該モジユール基板の熱
膨張係数の値から、各素子の熱膨張係数の値まで逐次変
化させた素子搭載用基板を介するため、半導体素子と素
子搭載用基板との接続部分および素子搭載用基板とモジ
ユール基板との接続部分における熱膨張係数の大きな差
がなく、それによつて、各接続部分において熱応力によ
る破壊が生じない。よつてこの方法を用いると、熱膨張
係数の異なる複数の種類の半導体素子を同一モジユール
基板上に近接して、信頼性良く搭載することができる。
In the semiconductor device manufactured by the above method, the value of the coefficient of thermal expansion between the semiconductor element and the module substrate is changed from the value of the coefficient of thermal expansion of the Through the device mounting substrate that is sequentially changed to the value of the thermal expansion coefficient of the semiconductor device, there is a large difference in the thermal expansion coefficient between the connection portion between the semiconductor device and the device mounting substrate and the connection portion between the device mounting substrate and the module substrate. Therefore, no breakage due to thermal stress occurs in each connection portion. Therefore, by using this method, a plurality of types of semiconductor elements having different thermal expansion coefficients can be mounted on the same module substrate in close proximity and with high reliability.

〔実施例〕〔Example〕

(実施例1) 本発明の半導体装置の一実施例を第1図に断面図とし
て示す。第1図において、1,2はそれぞれ、Si半導体素
子およびGaAs半導体素子である。SiとGaAsのほぼ中間の
熱膨張係数を有するムライト(3Al2O3・2SiO2)モジユ
ール基板3の上にはんだボール4を介して、ムライト−
シリカ(SiO2)−ガラス(Al2O3 35wt%,MgO 14wt%,Si
O2 51wt%)複合焼結基板5および、ムライト−アルミ
ナ(Al2O3)−ガラス(Al2O3 35wt%,MgO 14wt%,SiO2
51wt%)複合焼結基板6を搭載し、それらの上にさらに
はんだボール4を介して、それぞれSi半導体素子1およ
びGaAs半導体素子2を搭載したものである。ここで3a,5
aおよび6aは導体配線であり、7は入出力用または電源
用コバールピンである。
Embodiment 1 One embodiment of the semiconductor device of the present invention is shown in FIG. 1 as a cross-sectional view. In FIG. 1, reference numerals 1 and 2 denote a Si semiconductor element and a GaAs semiconductor element, respectively. A mullite (3Al 2 O 3 .2SiO 2 ) module 3 having a thermal expansion coefficient substantially intermediate between that of Si and GaAs is placed on a mullite module 3 via solder balls 4.
Silica (SiO 2 )-glass (Al 2 O 3 35 wt%, MgO 14 wt%, Si
O 2 51 wt%) composite sintered substrate 5 and mullite-alumina (Al 2 O 3 ) -glass (Al 2 O 3 35 wt%, MgO 14 wt%, SiO 2
(51 wt%) A composite sintered substrate 6 is mounted, and a Si semiconductor element 1 and a GaAs semiconductor element 2 are further mounted thereon via solder balls 4. Where 3a, 5
a and 6a are conductor wirings, and 7 is a Kovar pin for input / output or power.

次に本発明の半導体装置の作製方法の実施例を説明す
る。平均粒径2.5μmのムライト粉末(3Al2O3・2SiO2
90.0重量部、平均粒径1.0μmのガラス粉末(Al2O3 3wt
%,MgO 14wt%,SiO2 51wt%)10重量部に樹脂として平
均重合度1000のポリビニルブチラール5.9重量部をボー
ルミルに入れ、3時間乾式混合する。更に、可塑剤とし
てブチルフタリルグリコール酸ブチル1.9ml,溶剤として
トリクロロエチレン46.0ml,テトラクロロエチレン17.0m
l,ヘーブチルアルコール18.0重量部を加え12時間湿式混
合しスラリを作成する。次に、真空脱泡処理によりスラ
リから気泡を除去し、粘度調整を行なう。次いで、スラ
リをドクターブレードを用いてシリコーン処理したポリ
エステルフイルム支持体上に乾燥後0.23mmの厚さになる
ように塗布し、炉を通して乾燥し、セラミツクグリーン
シートを作製する。このセラミツクグリーンシートをシ
リコーン処理したポリエステルフイルム支持体より取り
外し、切断する。このようにして作製したセラミツクグ
リーンシートをグリーンシートパンチ器を用いて、切断
するとともに、ガイド用の穴を形成する。その後、この
ガイド用の穴を利用してセラミツクスグリーンシートを
固定し、パンチ法により直径0.3mmのスルーホールを所
定位置にあけた。更にタングステン粉末:エチルセルロ
ース:ポリビニルブチラール:n−ブチルカルビトールア
セテート=79.1:1.59:0.61:18.7(重量比)の導体ペー
ストをセラミツクグリーンシートにあけたスルーホール
に充填し、次に、スクリーン印刷法により所定回路パタ
ーンに従つて上述の導体ペーストをセラミツクグリーン
シートの両面に印刷した。次に、このセラミツクスグリ
ーンシートを切断し、位置合わせ後、120℃,5分,25kg/c
m2の圧力で積層・熱圧着した後、基板焼成炉中にセツト
し、水分を含有した窒素及び水素の混合ガス中で、1時
間に200℃の昇温速度で加熱し、1630℃で1.5時間保持し
て焼結し、ムライト・モジユール基板3を作製した。
Next, an example of a method for manufacturing a semiconductor device of the present invention will be described. Mullite powder with an average particle size of 2.5 μm (3Al 2 O 3 .2SiO 2 )
90.0 parts by weight, glass powder (Al 2 O 3 3wt
%, 14 wt% of MgO, 51 wt% of SiO 2 ), and 5.9 parts by weight of polyvinyl butyral having an average degree of polymerization of 1000 as a resin are put into a ball mill and dry-mixed for 3 hours. Furthermore, butyl butyl phthalyl glycolate 1.9 ml as a plasticizer, trichloroethylene 46.0 ml as a solvent, tetrachloroethylene 17.0 m
l, 18.0 parts by weight of hebutyl alcohol is added and wet mixed for 12 hours to prepare a slurry. Next, air bubbles are removed from the slurry by vacuum defoaming treatment, and the viscosity is adjusted. Next, the slurry is dried on a silicone-treated polyester film support using a doctor blade and then coated to a thickness of 0.23 mm, and dried through a furnace to produce a ceramic green sheet. The ceramic green sheet is detached from the silicone-treated polyester film support and cut. The ceramic green sheet thus produced is cut using a green sheet punch and a hole for guide is formed. Thereafter, the ceramics green sheet was fixed using the holes for guides, and through holes having a diameter of 0.3 mm were formed at predetermined positions by a punch method. Further, a conductive paste of tungsten powder: ethyl cellulose: polyvinyl butyral: n-butyl carbitol acetate = 79.1: 1.59: 0.61: 18.7 (weight ratio) is filled in the through-hole formed in the ceramic green sheet, and then screen printing is performed. The above-mentioned conductor paste was printed on both sides of the ceramic green sheet according to a predetermined circuit pattern. Next, this ceramic green sheet is cut, and after positioning, 120 ° C., 5 minutes, 25 kg / c
After lamination and thermocompression bonding at a pressure of m 2 , the substrate was set in a substrate baking oven, heated in a mixed gas of nitrogen and hydrogen containing water at a heating rate of 200 ° C. for one hour, and heated at 1630 ° C. for 1.5 hours. The mullite module substrate 3 was manufactured by holding for a time and sintering.

同様の方法で、ムライト粉末90.0重量部、ガラス粉末
10.0重量部、ポリビニルブチラール5.9重量部に平均粒
径1.0μmの石英粉末をそれぞれ10,20,30,40,50重量部
加えた5種類のセラミツクグリーンシートを作製する。
これらのグリーンシートをムライトモジユール基板同
様,穴あけ,導体充填,印刷後,石英粉末量が少ない順
に下から上に位置合わせして積層,熱圧着した後、モジ
ユール基板と同様に焼成して、Si半導体素子搭載用基板
5を作製した。
In the same way, 90.0 parts by weight of mullite powder, glass powder
Five types of ceramic green sheets were prepared by adding 10.0 parts by weight, 5.9 parts by weight of polyvinyl butyral, and 10, 20, 30, 40, and 50 parts by weight of quartz powder having an average particle size of 1.0 μm, respectively.
Like the mullite module substrate, these green sheets are drilled, filled with conductors, printed, aligned from bottom to top in ascending order of the amount of quartz powder, laminated, thermocompressed, fired in the same manner as the module substrate, and baked. A semiconductor element mounting substrate 5 was produced.

また同様の方法で、ムライト粉末90.0重量部,ガラス
粉末10.0重量部,ポリビニルブチラール5.9重量部に、
平均粒径1.0μmのアルミナ粉末をそれぞれ10,20,30,4
0,50重量部和えた5種類のセラミツクスグリーンシート
を作製する。これらのグリーンシートを穴あけ導体充
填、印刷後、アルミナ粉末量が少ない順に下から上に位
置合わせして積層・熱圧着した後、焼成して、GaAs半導
体素子搭載用基板6を作製した。
In the same manner, mullite powder 90.0 parts by weight, glass powder 10.0 parts by weight, polyvinyl butyral 5.9 parts by weight,
Alumina powder with an average particle size of 1.0 μm was added to each of 10,20,30,4
Five kinds of ceramic green sheets mixed with 0.50 parts by weight are produced. These green sheets were punched, filled with conductors, printed, laminated, thermo-compressed, positioned from bottom to top in ascending order of the amount of alumina powder, and fired to produce a GaAs semiconductor element mounting substrate 6.

モジユール基板3の下面スルーホール部WにNiめつき
を施した後、コバールピン7を接続する。一方、Si半導
体素子1及びGaAs半導体素子2をそれぞれの素子搭載用
基板の上に95Pb−5Srはんだボール4を用いてCCB接続す
る。
After Ni plating is applied to the through hole W on the lower surface of the module substrate 3, the Kovar pin 7 is connected. On the other hand, the Si semiconductor element 1 and the GaAs semiconductor element 2 are CCB-connected on the respective element mounting substrates using 95Pb-5Sr solder balls 4.

最後に、これら素子を搭載した素子搭載用基板をモジ
ユール基板の上に60Pb−40Srはんだボール4′を用いて
CCB接続することにより、半導体装置を作製した。信号
及び電源は素4及び4′のはんだボール、素子搭載用基
板5及び6中のスルーホール導体5a及び6a、モジユール
基板3中のスルーホール導体3aを介して、ピン7から入
出力される。また素子間の信号のやり取りはモジユール
基板3内の横方向の配線36を通して行なわれる。
Finally, the device mounting substrate on which these devices are mounted is mounted on the module substrate by using 60Pb-40Sr solder balls 4 '.
A semiconductor device was manufactured by CCB connection. Signals and power are input and output from the pin 7 via the solder balls of the elements 4 and 4 ', the through-hole conductors 5a and 6a in the element mounting boards 5 and 6, and the through-hole conductor 3a in the module board 3. The exchange of signals between the elements is performed through the horizontal wiring 36 in the module substrate 3.

第1図の各部分の熱膨張係数の値を第2に図に示し
た。
The values of the coefficients of thermal expansion of the respective parts in FIG. 1 are shown in FIG.

モジユール基板3はSi素子1及びGaAs素子2の中間の
熱膨張係数を有し、素子搭載用基板5及び6はそれぞ
れ、厚さ方向に熱膨張係数の勾配を有する。
The module substrate 3 has a coefficient of thermal expansion intermediate between the Si element 1 and the GaAs element 2, and the element mounting substrates 5 and 6 each have a gradient of the coefficient of thermal expansion in the thickness direction.

本半導体装置では、熱膨張係数が大きく異なるSi素子
とGaAs素子を同一モジユール基板上に近接して、信頼性
良く搭載することができた。またそれにより、Si素子と
GaAs素子を高密度に実装することが出来、信号伝播速度
を従来の装置に比べ約1.5倍速くすることができた。
In this semiconductor device, a Si element and a GaAs element having significantly different coefficients of thermal expansion could be mounted with high reliability in close proximity on the same module substrate. In addition, it can
The GaAs device could be mounted at a high density, and the signal propagation speed was about 1.5 times faster than the conventional device.

(実施例2) 本発明の半導体装置の一実施例を第2図に断面図とし
て示す。第2図において1,2はそれぞれSiおよびGaAs半
導体素子である。Siの熱膨張係数に近い熱膨張係数を有
するムライト(3Al2O3・2SiO2)−シリカ(SiO2)−ガ
ラス(Al2O3 35wt%,MgO 14wt%,SiO2 51wt%)からな
るモジユール基板3の上に、Si半導体素子1ははんだボ
ール4′を介して直接搭載し、GaAs半導体素子2は、ム
ライト−シリカ(SiO2)−アルミナ(Al2O3)−ガラス
(Al2O3 35wt%,MgO 14wt%,SiO2 51wt%)からなる素
子搭載用基板5およびはんだボール4及び4′を介して
搭載したものである。6は入出力用または電源用コバー
ルピンである。
Embodiment 2 One embodiment of the semiconductor device of the present invention is shown in FIG. 2 as a sectional view. In FIG. 2, reference numerals 1 and 2 denote Si and GaAs semiconductor elements, respectively. Mullite having a thermal expansion coefficient close to the thermal expansion coefficient of the Si (3Al 2 O 3 · 2SiO 2) - silica (SiO 2) - modules made of glass (Al 2 O 3 35wt%, MgO 14wt%, SiO 2 51wt%) on the substrate 3, Si semiconductor element 1 is mounted directly through the solder balls 4 ', GaAs semiconductor element 2, mullite - silica (SiO 2) - alumina (Al 2 O 3) - glass (Al 2 O 3 It is mounted via an element mounting substrate 5 made of 35 wt%, MgO 14 wt%, SiO 2 51 wt%) and solder balls 4 and 4 ′. Reference numeral 6 denotes an input / output or power supply Kovar pin.

作製方法は実施例1とほぼ同様である。モジユール基
板3は、平均粒径2.5μmのムライト粉末90.0重量部、
平均粒径1.0μmのガラス粉末10重量部、平均粒径1.0μ
mの石英(SiO2)粉末50重量部に平均重量度1000のポリ
ビニルブチラール5.9重量部を添加したものを出発原料
とした。
The manufacturing method is almost the same as that of the first embodiment. 90.0 parts by weight of mullite powder having an average particle size of 2.5 μm,
10 parts by weight of glass powder having an average particle size of 1.0 μm, average particle size of 1.0 μm
A starting material was obtained by adding 5.9 parts by weight of polyvinyl butyral having an average weight of 1000 to 50 parts by weight of a quartz (SiO 2 ) powder of m.

また、GaAs素子搭載用基板5は、ムライト粉末90.0重
量部、ガラス粉末10.0重量部、ポリビニルブチラール5.
9重量部に、平均粒径1.0μmの石英粉末をそれぞれ45,3
5,15,5重量部加えた5種類のグリーンシートと、平均粒
径1.0μmのアルミナ粉末をそれぞれ5,15,25,35,45重量
部加えた5種類のグリーンシート計10種類のグリーンシ
ートを作製し、これらのグリーンシートを穴あけ、導体
充填、印刷後、先に示した順序で下から上に位置合わせ
して積層熱圧した後、焼成して作製した。
The GaAs element mounting substrate 5 was composed of 90.0 parts by weight of mullite powder, 10.0 parts by weight of glass powder, and polyvinyl butyral 5.
9 parts by weight of quartz powder having an average particle size of 1.0 μm
Five kinds of green sheets with 5,15,5 parts by weight added, and five kinds of green sheets with 5,15,25,35,45 parts by weight of alumina powder having an average particle size of 1.0 μm, respectively, for a total of 10 kinds of green sheets These green sheets were perforated, filled with conductors, printed, aligned in the order shown above from bottom to top, laminated, hot-pressed, and fired.

またSi半導体素子1はGaAs素子を搭載した素子搭載用
基板と同時に、モジユール基板上に60Pb−40Srはんだボ
ール4′を用いてCCB接続した。
The Si semiconductor element 1 was connected to the element mounting substrate on which the GaAs element was mounted, and at the same time, was connected to the module substrate by CCB using 60Pb-40Sr solder balls 4 '.

本半導体装置の信号伝播速度は、実施例1同様、従来
の装置の約1.5倍であつた。
As in the first embodiment, the signal propagation speed of the present semiconductor device is about 1.5 times that of the conventional device.

(実施例3) 本発明の半導体装置の一実施例を第3図に断面図とし
て示す。第3図において1,2はそれぞれSiおよびGaAs半
導体素子である。Siの熱膨張係数に近い熱膨張係数を有
するムライト(3Al2O3・2SiO2)−シリカ(SiO2)−ガ
ラス(Al2O3 35wt%・MgO 14wt%,SiO2 51wt%)からな
り、GaAs半導体素子2を搭載する部分のみはその上にム
ライト−シリカ(SiO2)−アルミナ(Al2O3)−ガラス
(Al2O3 35wt%,MgO 14wt%,SiO2 51wt%)からなる素
子搭載部分を形成してある基板3の上に、はんだボール
4を介して、Si及びGaAs素子をそれぞれ搭載したもので
ある。5は入出力用または電源用コバールピンである。
Embodiment 3 An embodiment of the semiconductor device of the present invention is shown in FIG. 3 as a sectional view. In FIG. 3, reference numerals 1 and 2 denote Si and GaAs semiconductor elements, respectively. It consists of mullite (3Al 2 O 3 .2SiO 2 ) -silica (SiO 2 ) -glass (Al 2 O 3 35 wt%, MgO 14 wt%, SiO 2 51 wt%) having a thermal expansion coefficient close to that of Si, Only the portion on which the GaAs semiconductor element 2 is mounted is an element composed of mullite-silica (SiO 2 ) -alumina (Al 2 O 3 ) -glass (Al 2 O 3 35 wt%, MgO 14 wt%, SiO 2 51 wt%). On a substrate 3 on which a mounting portion is formed, Si and GaAs elements are mounted via solder balls 4 respectively. Reference numeral 5 denotes an input / output or power supply Kovar pin.

作製方法は実施例1および2とほぼ同様である。基板
3は、平均粒径2.5μmのムライト粉末90.0重量部、平
均粒径1.0μmのガラス粉末10重量部、平均粒径1.0μm
の石英(SiO2)粉末50重量部に平均重合度1000のポリビ
ニルブチラール5.9重量部を添加したものを出発原料と
したグリーンシートを穴あけ、導体充填、印刷した。こ
のシートを位置合わせして積層した上に、ムライト粉末
90.9重量部、ガラス粉末10.0重量部、ポリビニルブチラ
ール5.9重量部に平均粒径1.0μmの石英粉末をそれぞれ
45,35,25,15,5重量部加えた5種類のグリーンシート
と、平均粒径1.0μmのアルミナ粉末をそれぞれ5,15,2
5,35,45重量部加えた5種類のグリーンシート計10種類
のグリーンシートを作製し、穴あけ、導体充填・印刷し
たものを先に示した順序で下から上に位置合わせして積
層して、全体を一括熱圧着した後、焼成して作製した。
The fabrication method is almost the same as in Examples 1 and 2. The substrate 3 was composed of 90.0 parts by weight of mullite powder having an average particle size of 2.5 μm, 10 parts by weight of glass powder having an average particle size of 1.0 μm, and 1.0 μm in average particle size.
A green sheet was prepared by adding 50 parts by weight of quartz (SiO 2 ) powder and 5.9 parts by weight of polyvinyl butyral having an average degree of polymerization of 1000 as a starting material, and a conductor was filled and printed. After aligning and laminating this sheet, mullite powder
90.9 parts by weight, glass powder 10.0 parts by weight, polyvinyl butyral 5.9 parts by weight quartz powder having an average particle size of 1.0 μm
Five kinds of green sheets added with 45,35,25,15,5 parts by weight and alumina powder having an average particle size of 1.0 μm were added to 5,15,2, respectively.
Five kinds of green sheets with a total of 5,35,45 parts by weight were added, and a total of 10 kinds of green sheets were prepared, drilled, filled with conductors and printed, aligned in the order shown above from bottom to top, and laminated. After that, the whole was thermocompression-bonded at a time and fired.

またSi及びGaAs半導体素子は基板3上に60Pb−40Srは
んだボール4を用いてCCB接続した。
The Si and GaAs semiconductor elements were CCB-connected on the substrate 3 using 60Pb-40Sr solder balls 4.

本半導体装置の信号伝播速度は、従来の装置の約1.6
倍であつた。
The signal propagation speed of this semiconductor device is about 1.6 times that of the conventional device.
It was double.

〔発明の効果〕〔The invention's effect〕

本発明は、以上説明したように構成されているので以
下に記載されるような効果を奏する。
Since the present invention is configured as described above, it has the following effects.

すなわち、熱膨張係数の異なる複数の種類の半導体素
子を同一モジユール基板上に近接して信頼性良く搭載す
ることができる。
That is, a plurality of types of semiconductor elements having different coefficients of thermal expansion can be mounted on the same module substrate in close proximity and with high reliability.

それにより半導体装置内全体の配線長を短かくするこ
とができ、信号伝播速度が高速化される。
As a result, the entire wiring length in the semiconductor device can be shortened, and the signal propagation speed is increased.

【図面の簡単な説明】[Brief description of the drawings]

第1図,第3図,第4図は本発明の半導体装置の断面
図、第2図は第1図の各部分の熱膨張係数の値を示した
説明図である。 1……Si半導体素子、2……GaAs半導体素子、3……モ
ジユール基板、3a……モジユール基板内スルーホール配
線、3b……モジユール基板内横方向配線、4……95Pb−
5Srはんだボール、4′……60Pb−40Srはんだボール、
5……Si半導体素子搭載用基板、5a……Si半導体素子搭
載用基板内スルーホール配線、6……GaAs半導体素子搭
載用基板、6a……GaAs半導体素子搭載用基板内スルーホ
ール配線、7……入出力または電源供給用ピン、8……
モジユール基板、9……GaAs半導体素子搭載用基板、10
……基板。
1, 3, and 4 are cross-sectional views of the semiconductor device of the present invention, and FIG. 2 is an explanatory diagram showing the values of the coefficients of thermal expansion of the respective parts in FIG. DESCRIPTION OF SYMBOLS 1 ... Si semiconductor element, 2 ... GaAs semiconductor element, 3 ... Module board, 3a ... Through hole wiring in module board, 3b ... Horizontal wiring in module board, 4 ... 95Pb-
5Sr solder ball, 4 '…… 60Pb-40Sr solder ball,
5 ... Si substrate mounting substrate, 5a ... Through hole wiring inside Si semiconductor device mounting substrate, 6 ... GaAs semiconductor device mounting substrate, 6a ... Through hole wiring inside GaAs semiconductor element mounting substrate, 7 ... ... Pin for input / output or power supply, 8 ...
Module substrate, 9 ... GaAs semiconductor element mounting substrate, 10
……substrate.

フロントページの続き (72)発明者 田中 明 茨城県日立市久慈町4026番地 株式会社 日立製作所日立研究所内 (72)発明者 牛房 信之 茨城県日立市久慈町4026番地 株式会社 日立製作所日立研究所内Continued on the front page (72) Inventor Akira Tanaka 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd.

Claims (22)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】熱膨張係数の異なる複数の種類の半導体素
子のうち最も熱膨張係数の小さい素子の熱膨張係数以上
かつ最も熱膨張係数の大きい素子の熱膨張係数以下の熱
膨張係数を有するモジユール基板上に、モジユール基板
の熱膨張係数と各素子の熱膨張係数の間の熱膨張係数を
有し、かつ厚さ方向に熱膨張係数の勾配を有する素子搭
載用基板を搭載し、その上に各素子を搭載したことを特
徴とする半導体装置。
1. A module having a thermal expansion coefficient equal to or higher than the thermal expansion coefficient of the element having the lowest thermal expansion coefficient and equal to or lower than the thermal expansion coefficient of the element having the highest thermal expansion coefficient among a plurality of types of semiconductor elements having different thermal expansion coefficients. On the substrate, a device mounting substrate having a coefficient of thermal expansion between the coefficient of thermal expansion of the module substrate and the coefficient of thermal expansion of each element, and having a gradient of the coefficient of thermal expansion in the thickness direction, is mounted. A semiconductor device having each element mounted thereon.
【請求項2】熱膨張係数の異なる複数の種類の半導体素
子のうちの1種類の半導体素子の熱膨張係数に等しい熱
膨張係数を有するモジユール基板上に、その1種類の半
導体素子のみは直接搭載もしくは該半導体素子および該
モジユール基板の熱膨張係数に等しい熱膨張係数を有す
る素子搭載用基板を介して搭載し、他の半導体素子は該
モジユール基板上に、モジユール基板の熱膨張係数と各
素子の熱膨張係数の間の熱膨張係数を有し、かつ厚さ方
向に熱膨張係数の勾配を有する素子搭載用基板を介して
搭載したことを特徴とする半導体装置。
2. A module substrate having a thermal expansion coefficient equal to the thermal expansion coefficient of one of a plurality of semiconductor elements having different thermal expansion coefficients is directly mounted on a module substrate. Alternatively, the semiconductor element and the module substrate are mounted via an element mounting substrate having a coefficient of thermal expansion equal to the coefficient of thermal expansion of the module substrate, and other semiconductor elements are mounted on the module substrate and the coefficient of thermal expansion of the module substrate and A semiconductor device having a thermal expansion coefficient between thermal expansion coefficients and mounted via an element mounting substrate having a thermal expansion coefficient gradient in a thickness direction.
【請求項3】室温から液体窒素温度までの温度サイクル
試験を1000サイクル行なつても熱応力による破壊が生じ
ないことを特徴とする請求項1または2に記載の半導体
装置。
3. The semiconductor device according to claim 1, wherein no destruction due to thermal stress occurs even after 1000 cycles of a temperature cycle test from room temperature to liquid nitrogen temperature.
【請求項4】請求項1または2に記載の半導体装置にお
いて、該モジユール基板と該素子搭載用基板を作製時に
一括積層して1つの基板とし、その上に素子を搭載した
ことを特徴する半導体装置。
4. The semiconductor device according to claim 1, wherein said module substrate and said element mounting substrate are collectively laminated at the time of fabrication to form one substrate, and an element is mounted thereon. apparatus.
【請求項5】請求項1または2記載の半導体装置におい
て、該モジユール基板と該素子搭載用基板の一部を作製
時に一括積層として1つの基板としたことを特徴とする
半導体装置。
5. The semiconductor device according to claim 1, wherein the module substrate and a part of the element mounting substrate are integrally laminated at the time of fabrication to form one substrate.
【請求項6】熱膨張係数の異なる複数の種類の半導体素
子のうち最も熱膨張係数の小さい素子の熱膨張係数以上
かつ最も熱膨張係数の大きい素子の熱膨張係数以下の熱
膨張係数を有するモジユール基板上に、該モジユール基
板の熱膨張係数の値と各素子の熱膨張係数の値の間の均
一な熱膨張係数の値を有する素子搭載用基板をそれぞれ
搭載し、その上に各素子を搭載したことを特徴とする半
導体装置。
6. A module having a thermal expansion coefficient equal to or higher than the thermal expansion coefficient of the element having the lowest thermal expansion coefficient and equal to or lower than the thermal expansion coefficient of the element having the highest thermal expansion coefficient among a plurality of types of semiconductor elements having different thermal expansion coefficients. On the substrate, each of the element mounting substrates having a uniform coefficient of thermal expansion between the value of the coefficient of thermal expansion of the module substrate and the value of the coefficient of thermal expansion of each element is mounted, and each element is mounted thereon. A semiconductor device characterized by the following.
【請求項7】請求項6または7記載の半導体装置におい
て、該素子搭載用基板の上に、該素子搭載用基板の熱膨
張係数の値と各素子の熱膨張係数の値の間の均一な熱膨
張係数の値を有する素子搭載用基板をさらにそれぞれ搭
載し、その上に各素子を搭載したことを特徴とする半導
体装置。
7. The semiconductor device according to claim 6, wherein a uniform thermal expansion coefficient between the value of the thermal expansion coefficient of the element mounting substrate and the value of the thermal expansion coefficient of each element is provided on the element mounting substrate. A semiconductor device, further comprising an element mounting substrate having a coefficient of thermal expansion, and each element mounted thereon.
【請求項8】熱膨張係数の異なる複数の種類の半導体素
子のうちの1種類の半導体素子の熱膨張係数に等しい熱
膨張係数を有するモジユール基板上に、その1種類の半
導体素子のみは直接搭載もしくは該半導体素子および該
モジユール基板の熱膨張係数に等しい熱膨張係数を有す
る素子搭載用基板を介して搭載し、他の半導体素子は、
該モジユール基板上に該モジユール基板の熱膨張係数の
値と各素子の熱膨張係数の値の間の均一な熱膨張係数の
値を有する素子搭載用基板をそれぞれ搭載し、その上に
各素子を搭載したことを特徴とする半導体装置。
8. A module substrate having a thermal expansion coefficient equal to the thermal expansion coefficient of one of a plurality of types of semiconductor elements having different thermal expansion coefficients, and only the one type of semiconductor element is directly mounted. Or mounted via an element mounting substrate having a coefficient of thermal expansion equal to the coefficient of thermal expansion of the semiconductor element and the module substrate, other semiconductor elements,
On the module substrate, element mounting substrates having a uniform thermal expansion coefficient between the value of the thermal expansion coefficient of the module substrate and the value of the thermal expansion coefficient of each element are mounted, and each element is mounted thereon. A semiconductor device characterized by being mounted.
【請求項9】請求項1,2,4または5に記載の半導体装置
において、該素子搭載用基板の熱膨張係数の勾配が直線
的でなく、実際に素子を搭載し作動させたときの該素子
搭載用基板の熱応力の厚さ方向の分布が等しくなるよう
に、熱膨張係数の勾配つけたことを特徴とする半導体装
置。
9. The semiconductor device according to claim 1, wherein the gradient of the coefficient of thermal expansion of the substrate for mounting the element is not linear, and when the element is actually mounted and operated. A semiconductor device characterized in that a thermal expansion coefficient is graded so that distribution of thermal stress in a thickness direction of an element mounting substrate becomes equal.
【請求項10】厚さ方向に熱膨張係数の勾配を有するこ
とを特徴とする基板。
10. A substrate having a thermal expansion coefficient gradient in a thickness direction.
【請求項11】請求項4または5記載の、該モジユール
基板と該素子搭載用基板を一括積層したことを特徴とす
る基板。
11. A substrate according to claim 4, wherein said module substrate and said element mounting substrate are laminated together.
【請求項12】請求項1ないし9記載の半導体装置にお
いて、該モジユール基板および該素子搭載用基板が多層
配線基板であることを特徴とする半導体装置。
12. The semiconductor device according to claim 1, wherein said module substrate and said element mounting substrate are multilayer wiring substrates.
【請求項13】請求項10または11記載の基板において、
該基板が多層配線基板であることを特徴とする基板。
13. The substrate according to claim 10, wherein
A substrate, wherein the substrate is a multilayer wiring substrate.
【請求項14】熱膨張係数の異なる複数の成分からな
り、該成分の配合比が少しずつ異なる複数枚のグリーン
シートを積層、焼結することを特徴とする厚さ方向に熱
膨張係数の勾配を有する基板の製造方法。
14. A gradient of a thermal expansion coefficient in a thickness direction, comprising laminating and sintering a plurality of green sheets comprising a plurality of components having different thermal expansion coefficients and a slightly different mixing ratio of the components. A method for manufacturing a substrate having:
【請求項15】同組成のグリーンシート複数枚を積層し
た上に、請求項14記載の複数枚のグリーンシートを積層
後、焼結することを特徴とする基板の製造方法。
15. A method for manufacturing a substrate, comprising: laminating a plurality of green sheets having the same composition, laminating a plurality of green sheets according to claim 14, and sintering.
【請求項16】請求項14または15において、該グリーン
シートを穴あけ、導体印刷後,積層,焼結することを特
徴とする基板の製造方法。
16. A method for manufacturing a substrate according to claim 14, wherein said green sheet is perforated, printed with a conductor, laminated and sintered.
【請求項17】請求項1ないし9または12に記載の半導
体装置において、該半導体素子が封止されていることを
特徴とする半導体装置。
17. The semiconductor device according to claim 1, wherein said semiconductor element is sealed.
【請求項18】請求項10,11または13記載の基板を用い
たことを特徴とする半導体パツケージ。
18. A semiconductor package using the substrate according to claim 10, 11, or 13.
【請求項19】請求項1ないし9または12または17に記
載の半導体装置を用いたことを特徴とする電子計算機。
19. An electronic computer using the semiconductor device according to claim 1. Description:
【請求項20】請求項10,11または13に記載の基板を用
いたことを特徴とする電子計算機。
20. An electronic computer using the substrate according to claim 10, 11, or 13.
【請求項21】請求項18に記載の半導体パツケージを用
いたことを特徴とする電子計算機。
21. An electronic computer using the semiconductor package according to claim 18.
【請求項22】請求項19ないし21に記載の電子計算機に
おいて、各半導体素子の上面から同じ手段の冷却装置を
設けたことを特徴とする電子計算機。
22. An electronic computer according to claim 19, wherein a cooling device of the same means is provided from the upper surface of each semiconductor element.
JP1242191A 1989-09-20 1989-09-20 Semiconductor device Expired - Lifetime JP2574902B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1242191A JP2574902B2 (en) 1989-09-20 1989-09-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1242191A JP2574902B2 (en) 1989-09-20 1989-09-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH03105954A JPH03105954A (en) 1991-05-02
JP2574902B2 true JP2574902B2 (en) 1997-01-22

Family

ID=17085649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1242191A Expired - Lifetime JP2574902B2 (en) 1989-09-20 1989-09-20 Semiconductor device

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Country Link
JP (1) JP2574902B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2960276B2 (en) * 1992-07-30 1999-10-06 株式会社東芝 Multilayer wiring board, semiconductor device using this substrate, and method of manufacturing multilayer wiring board
US5888630A (en) * 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly
US7692287B2 (en) 2004-05-21 2010-04-06 Nec Corporation Semiconductor device and wiring board
JP4840245B2 (en) * 2007-04-27 2011-12-21 株式会社日立製作所 Multi-chip module
JP5367523B2 (en) 2009-09-25 2013-12-11 新光電気工業株式会社 Wiring board and method of manufacturing wiring board
JP7056620B2 (en) * 2019-03-28 2022-04-19 株式会社デンソー Electronic device
DE102020205686A1 (en) 2020-05-06 2021-11-11 Robert Bosch Gesellschaft mit beschränkter Haftung Electronic device

Also Published As

Publication number Publication date
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