JP2573388B2 - Information processing device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application Field of the Invention Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment Effect of the Invention [Summary] Access is requested from the processor and the An information processing apparatus to which access permission is given from a memory to a processor. The present invention relates to an information processing apparatus capable of dynamically adjusting a memory access speed of a processor. A memory permitting an access requested by the processor, a register whose value is rewritten by a program running on the processor, and forcibly suppressing the request and request permission at regular intervals for a predetermined period according to the register value. An access speed control circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which access is requested from a processor and access permission is given to the processor from a memory.

The processor used in this type of apparatus has reduced the cost per unit function due to improved performance, and as a result, many application software are provided for various fields.

[Prior Art] In FIG. 5, when an access is requested from the processor 10 to the memory 12, the request is given to the AND gate 20-2 of the memory 12, and is taken into the memory.

Then, the memory access permission signal sent from the memory 12 is applied to the AND gate 20-1 of the processor 10, and is taken into the processor.

As a result, when the processor 10 requests access to the memory 12, when the memory 12 permits the access, the access of the processor 10 is started in the next cycle of the permission signal transmission as shown in FIG.

Since the performance of the processor 10 is greatly improved in a short time and the cost per function is reduced, many application softwares are provided for various fields.

However, depending on the application software, the processing speed of the processor 10 is too high, which hinders execution.

Therefore, the following measures are taken. Here, three examples are shown.

A NOP (non-operation instruction) is inserted between machine language instructions of the program to adjust the processing speed of the processor 10.

For example, when the processing speed of the processor 10 is halved, three NOPs are inserted as shown in FIG. 7B for a three-step machine language instruction shown in FIG. 7A. .

When three NOPs are inserted into a machine instruction of 30 steps, this processing becomes 33 steps, and the processor 10
Processing speed is adjusted to 30/33.

As described above, since it is necessary to insert the number of NOPs corresponding to the number of machine language instructions, the number of NOPs must be considered for each program.

Further, in the case of a machine instruction word whose processing speed varies depending on the data length / data value, it is actually impossible to uniformly adjust the processing speed of the processor 10 for such a program.

The application software is recreated so that the processing is completed in a fixed time, and the application software is adjusted to the processing speed of the processor 10.

In this case, since the number of application software is enormous, a great deal of labor is required to change the program.

The processing speed of the processor 10 is adjusted by adjusting the clock (cycle down or stopping the clock for a certain period of time).

In this case, the dynamic RAM refresh timer and clock incorporated in the processor are out of order.

[Problem to be Solved by the Invention] Therefore, an apparatus shown in FIG. 8 has been proposed.

In the figure, AND gates 20-3 and 20-4 and a timer signal generation circuit 22 provided outside are provided between the processor 10 and the memory 12.

Further, a timer signal t generated by the timer signal generation circuit 22 for a predetermined continuous cycle length during a fixed length period to the AND gates 20-4 and 20-3, and a memory access request signal transmitted by the processor 10, Timer signal generation circuit
A timer signal t of 22 and an access permission signal transmitted from the memory 12 are given.

In this example, when the processor 10 requests access to the memory 12 and the memory 12 permits the access, the timer signal t is transmitted from the access speed control circuit 16 to the AND gate 20.
Only when given to −3, 20-4, the processor 10 is accessed.

Also, even when the processor 10 requests access to the memory 12 and the memory 12 permits the access, the timer signal t is output from the access speed control circuit 16 to the AND gate.
When given to 20-3 and 20-4, the processor 10 is not accessed.

Therefore, when performing a predetermined process, the processor 10 is stopped, and the time required for the process becomes longer.

Therefore, depending on the generation period of the timer signal t, the processor
The processing speed of 10 is adjusted in the decreasing direction.

For example, in the case of FIG. 9, the processing speed of the processor 10 is adjusted to 1/2 by the timer signal t generated for three out of six cycles.

According to this proposal, the processing speed of the processor 10 can be uniformly adjusted without inserting the number of NOPs corresponding to the number of machine language instructions, and the application software need not be recreated.

Further, since the processing speed of the processor 10 can be adjusted without stopping the clock, the timer and clock incorporated in the processor do not go out of order.

However, in this proposal, since the generation period of the timer signal t is fixed, it is necessary to set the processing speed of the processor 10 to the generation period of the timer signal t for each application software.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide an information processing apparatus capable of dynamically adjusting the performance of a processor.

[Means for Solving the Problems] To achieve the above object, an apparatus according to the present invention is configured as shown in FIG.

In the figure, the processor 10 requests access to the memory 12, and the memory 12 permits the access requested by the processor 10.

Further, a register 14 whose value is rewritten by a program running in the processor 10 is provided, and an access request is forcibly transmitted at a constant interval for a predetermined period by an access speed control circuit 18 in accordance with the value of the register 14. Permissions are suppressed.

[Operation] According to the present invention, the processor 10 receives the timer signal t generated at a constant interval for a predetermined period according to the value of the register 14.
Memory access speed is forcibly suppressed.

Then, the value of the register 14 can be rewritten from the processor 10.

Hereinafter, a preferred embodiment of the device according to the present invention will be described with reference to the drawings.

In FIG. 2, when an access is requested from the processor 10 to the memory 12, the request is sent to the AND gate 20-.
4 to the AND gate 20-2 of the memory 12;
The data is stored in the memory 12.

Then, the memory access permission signal sent from the memory 12 is supplied to the AND gate 20-1 of the processor 10 via the AND gate 20-3, and is taken therein.

A register 14 and an access speed control circuit 16 are provided between the processor 10 and the memory 12. As shown in FIG. Given to 14.

The value of the register 14 is rewritten by a program running on the processor 10.

The value of the register 14 is read into the access speed control circuit 16 as an initial value, and the access speed control circuit 16 generates a timer signal t for a predetermined continuous cycle length within a certain length of time according to the read value of the register 14. Is generated,
The timer signal t is applied to AND gates 20-3 and 20-4, respectively.

Then, when the processor 10 requests access to the memory 12 and the memory 12 permits the access, the access speed control circuit 16 supplies a timer signal t corresponding to the value of the register 14 to the AND gates 20-3 and 20-4. Only when
Access of the processor 10 is started.

Also, even when the processor 10 requests access to the memory 12 and the memory 12 permits the access, the timer signal t is output from the access speed control circuit 16 to the AND gate.
If not given to 20-3, 20-4, the processor
10 accesses are not made.

In FIG. 4, the register 14 by the access speed control circuit 16 is used.
The generation of the timer signal t corresponding to the value of
For example, when the value of the register 14 is set to 1001, the timer signal t is continuously generated over a period of 4 × 16 μs, and the access speed control circuit 16
−3, 20-4.

Then, the timer signal t over the next 4 × 16 μs period
Is not generated, and the timer signal t is not supplied from the access speed control circuit 16 to the AND gates 20-3 and 20-4.

For this reason, in this example, the memory access processing speed of the processor 10 is adjusted to decrease by a factor of 1/2.

As described below, according to this embodiment, the processor 10
The memory access speed is forcibly suppressed by a timer signal t generated for a predetermined continuous cycle length during a fixed length period corresponding to the value of the register 14.

Since the value of the register 14 can be rewritten from the processor 10, the processing speed of the processor 10 can be dynamically adjusted for each program.

Therefore, the memory access speed of the processor 10 can be automatically adjusted according to each application software.

According to the present invention, the processing speed of the processor can be dynamically adjusted by rewriting the value of the register as needed.

Therefore, the memory access speed of the processor can be automatically set in accordance with each application software, and therefore, handling of the application software becomes easy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the invention, FIG. 2 is a diagram illustrating the configuration of an embodiment, FIG. 3 is a diagram schematically illustrating registers and an access speed control circuit, FIG. FIG. 6 is an explanatory view of the configuration of the conventional example, FIG. 6 is an explanatory view of the operation of the conventional example, FIG. 7 is an explanatory view of the operation of NOP insertion, FIG. 8 is a schematic explanatory view of the proposed apparatus, and FIG. FIG. 10 Processor 12 Memory 14 Register 16 Access speed control circuit 20-1, 20-2, 20-3, 20-4 AND gate 22 Timer signal generation circuit 24 Data bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Odawara 1015 Ueodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Eiji Kanaya 1015 Kamiodanaka Nakahara-ku Kawasaki-shi Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-2-153427 (JP, A)

Claims (1)

(57) [Claims] A processor (10) for requesting access to a memory (12), a memory (12) for permitting access requested by the processor (10), and a value rewritten by a program running on the processor (10). And an access speed control circuit (16) that forcibly suppresses the request and the request permission at regular intervals for a predetermined period according to the value of the register (14). Information processing device.