JP2570428B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2570428B2 JP2570428B2 JP1215645A JP21564589A JP2570428B2 JP 2570428 B2 JP2570428 B2 JP 2570428B2 JP 1215645 A JP1215645 A JP 1215645A JP 21564589 A JP21564589 A JP 21564589A JP 2570428 B2 JP2570428 B2 JP 2570428B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- substrate
- semiconductor device
- joint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48724—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
- H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
- H01L2224/48992—Reinforcing structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/85951—Forming additional members, e.g. for reinforcing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、基板上に固定された半導体素体の反基板側
に設けられたアルミニウム膜からなる電極にアルミニウ
ム線がボンディングされる半導体装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an aluminum wire is bonded to an electrode made of an aluminum film provided on a side opposite to a substrate of a semiconductor body fixed on the substrate. .
例えばパワートランジスタモジュールのように複数の
半導体素子からなる半導体装置において、半導体素体を
基板上に固定し、各素体の反基板側に設けられた電極を
他の素体の電極あるいは端子と接続するために、電極に
導線を結合する。このような結合の方法として、電極を
アルミニウム膜により形成し、導線として用いられるア
ルミニウム線を超音波ボンディングにより接合すること
が行われる。このあと、基板，半導体素体および導線の
上を機械的応力を及ぼさないゲル状のシリコーン樹脂で
覆い、外力あるいは湿気から保護していた。For example, in a semiconductor device including a plurality of semiconductor elements such as a power transistor module, a semiconductor element is fixed on a substrate, and an electrode provided on a side opposite to the substrate of each element is connected to an electrode or terminal of another element. To do so, a conductor is coupled to the electrode. As such a bonding method, an electrode is formed of an aluminum film, and an aluminum wire used as a conductive wire is bonded by ultrasonic bonding. Thereafter, the substrate, the semiconductor element, and the conductive wire are covered with a gel-like silicone resin that does not exert a mechanical stress to protect the substrate from external force or moisture.
半導体装置の導電状態で半導体素体が発熱する。この
発熱によって起こる温度変動により故障が発生する。こ
の故障のうち、電極と導線との接合部の剥離が問題とな
っている。この剥離現象を微視解析した結果、結合部の
周囲の電極を形成しているAl膜のAl結晶が素体の発熱に
より再配列現象を起こすことによることがわかった。す
なわち、トランジスタ等のチップの電極に10５〜６A/cm
2程度の電流が流れると、上部電極であるAl膜が再配列
現象を起こし、100℃以上になると、それまで配位（11
1）面があらわれていたのが（100）面があらわれ、この
現象によりAl線の接合部がもち上げられ、剥離が起こ
る。The semiconductor element generates heat in the conductive state of the semiconductor device. Failure occurs due to temperature fluctuations caused by this heat generation. Among these failures, peeling of the joint between the electrode and the conductive wire has become a problem. As a result of microscopic analysis of this peeling phenomenon, it was found that the Al crystal of the Al film forming the electrode around the joint portion was caused by a rearrangement phenomenon due to heat generation of the element body. That is, 105 to 6 A / cm is applied to the electrodes of a chip such as a transistor.
When a current of about 2 flows, the Al film, which is the upper electrode, undergoes a rearrangement phenomenon.
1) The (100) plane appears instead of the plane, and this phenomenon raises the joint of the Al wire and causes peeling.
本発明の目的は、このようなAl電極に起こる再配列に
基づく電極と導線との剥離現象が防止された信頼性の高
い半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device in which a peeling phenomenon between an electrode and a conductive wire based on such rearrangement of an Al electrode is prevented.
上記の目的を達成するために、本発明は、基板上に固
定された半導体素体の反基板側に設けられたアルミニウ
ム膜からなる電極にアルミニウム線がボンディング接合
される半導体装置において、電極のアルミニウム線との
接合部が10-4kg/cm2より大きく５×102kg/cm2より小さ
い圧縮応力を接合部に発生させる有機絶縁性樹脂によっ
て被覆されたものとする。In order to achieve the above object, the present invention provides a semiconductor device in which an aluminum wire is bonded and bonded to an electrode formed of an aluminum film provided on a side opposite to a substrate of a semiconductor body fixed on a substrate. It is assumed that the joint with the wire is coated with an organic insulating resin that generates a compressive stress at the joint that is greater than 10 −4 kg / cm 2 and less than 5 × 10 2 kg / cm 2 .
電極に電流が流れた場合、Alと電流との相互作用でAl
原子は移動し、それまでの配位（111）面から垂直の（1
00）面が表われるようになる。これによってAl膜が持ち
上げられ、接合部の剥離が生ずる。このようなAlと電流
の相互作用による力はクーロン力の10倍とされる。すな
わち、Al膜をもち上げる力をＦとすると次の式で与えら
れる。When a current flows through the electrode, the interaction between Al and the current
The atom moves and is perpendicular (1) from the previous coordinated (111) plane.
00) The surface appears. As a result, the Al film is lifted, and peeling of the joint occurs. The force due to the interaction between Al and the current is set to be 10 times the Coulomb force. That is, when the force for lifting the Al film is F, it is given by the following equation.
ここで、εはAlの比誘電率で4.5、ε０は真空の誘電
率で8.85419×10-12F/m、ｅは電気素量で1.60214×10
-19C、ｒはAlの原子半径で2.862Åである。これから計
算すると次の値が得られる。 Here, ε is a relative dielectric constant of Al of 4.5, ε 0 is a dielectric constant of vacuum at 8.85419 × 10 −12 F / m, and e is an elementary quantity of 1.60214 × 10
-19 C, r is the atomic radius of Al, which is 2.860 °. Calculating from this gives the following value:
Ｆ＝6.26×10-5kg/cm2 本発明により接合部に覆われる絶縁物は、接合部に10
-4kg/cm2より大きい圧縮応力を発生させるが、この応力
は上記のＦより大きく、電流との相互作用でAl膜が持ち
上げられるのを抑制する。しかし、この応力が大きすぎ
ると、Al膜の変形ないし破壊を招くおそれがある。そこ
でこの応力σの値を純アルミニウムの降伏点５×102kg/
cm2以下に抑えておく。F = 6.26 × 10 −5 kg / cm 2 The insulator covered by the joint according to the present invention
A compressive stress of more than -4 kg / cm 2 is generated, which stress is larger than the above-mentioned F, and suppresses the lifting of the Al film due to the interaction with the current. However, if this stress is too large, the Al film may be deformed or broken. Therefore, the value of this stress σ is calculated as the yield point of pure aluminum 5 × 10 2 kg /
Keep it below 2 cm.
第１図は本発明の一実施例を示し、銅基板１上にセラ
ミック絶縁基板２、銅接続導体板３を介して、例えばト
ランジスタチップのような半導体素体４が固定されてい
る。半導体素体の上面には、例えば蒸着によって形成さ
れるAl電極膜５が被着しており、この電極膜５にAl導線
６が超音波ボンディングで接合されている。このボンデ
ィング後にAl導線６とAl電極膜５との接合部をポリイミ
ド膜７で覆う。さらに、基板１と側壁９からなる容器に
シリコーン樹脂ゲル８を充填し、基板上の各部品を汚
染，湿気から遮断し、腐食，特性劣化等から保護する。
ポリイミド膜７は成膜時の温度から常温に至る間に収縮
し、Al膜５に圧縮応力を加える。このときAl膜５に発生
する応力σは次の式で与えられる。FIG. 1 shows an embodiment of the present invention. A semiconductor element 4 such as a transistor chip is fixed on a copper substrate 1 via a ceramic insulating substrate 2 and a copper connection conductor plate 3. An Al electrode film 5 formed, for example, by vapor deposition is adhered on the upper surface of the semiconductor body, and an Al conductive wire 6 is joined to the electrode film 5 by ultrasonic bonding. After this bonding, the junction between the Al conductor 6 and the Al electrode film 5 is covered with a polyimide film 7. Further, a container formed of the substrate 1 and the side wall 9 is filled with a silicone resin gel 8 to protect each component on the substrate from contamination and moisture, and to protect against corrosion, characteristic deterioration, and the like.
The polyimide film 7 contracts from the temperature at the time of film formation to room temperature, and applies a compressive stress to the Al film 5. At this time, the stress σ generated in the Al film 5 is given by the following equation.
σ＝αＥΔＴ ここでαは被覆絶縁体の線膨脹係数、Ｅは絶縁体のヤ
ング率、ΔＴは膜形成温度と常温の間の温度差である。σ = αEΔT where α is the coefficient of linear expansion of the coated insulator, E is the Young's modulus of the insulator, and ΔT is the temperature difference between the film formation temperature and room temperature.
第１表は種々の絶縁性誘電体のα,E,ΔＴおよびそれ
から計算されるσの値を示す。Table 1 shows the values of α, E, ΔT and σ calculated from various insulating dielectrics.
この表から接合部を覆う材料としてはポリイミド樹脂
あるいはSiO2（酸化けい素）の応力σが５×102kg/cm2
より小さいものが適していることがわかる。さらに、こ
のうちのポリイミド樹脂のαはアルミニウムのαの23.1
3×10-6/℃に近いので、ポリイミド樹脂が最も適してい
る。 According to this table, the material covering the joint is polyimide resin or SiO 2 (silicon oxide) having a stress σ of 5 × 10 2 kg / cm 2.
It turns out that a smaller one is suitable. Furthermore, α of the polyimide resin is 23.1 of α of aluminum.
Since it is close to 3 × 10 −6 / ° C., polyimide resin is most suitable.
第２図は第１図に示した構造の半導体素子に対し、オ
ン２秒，オフ20秒のパワーサイクルをくり返したときの
半導体素体の温度差とパワーサイクル耐量との関係を示
し、実線21はAl導線６とAl電極膜５との接合部を直接シ
リコーン樹脂ゲルで覆った場合、点線22は上記の実施例
のようにポリイミド膜７で覆った場合である。ポリイミ
ド膜で覆ったことによりパワーサイクル耐量が大幅に改
善されたことがわかる。FIG. 2 shows the relationship between the temperature difference of the semiconductor element and the power cycle capability when the power cycle of ON 2 seconds and OFF 20 seconds is repeated for the semiconductor device having the structure shown in FIG. Represents the case where the joint between the Al conductor 6 and the Al electrode film 5 is directly covered with the silicone resin gel, and the dotted line 22 represents the case where the polyimide film 7 is covered as in the above embodiment. It can be seen that the power cycle capability was significantly improved by covering with the polyimide film.
本発明によれば、トランジスタなどの半導体素体の上
部Al電極膜とAl導線との接合部を電気的影響がなく、か
つ10-4kg/cm2より大きく５×102kg/cm2より小さい圧縮
応力を接合部に発生させる有機絶縁性樹脂により被覆す
ることにより、半導体素体への通電時にAl電極膜が再配
列現象を起こして接合部をもち上げる現象を機械的応力
により抑制することができ、パワーサイクル耐量の大幅
に向上した半導体装置が得られた。According to the present invention, the junction between the upper Al electrode film of a semiconductor element such as a transistor and an Al conducting wire has no electrical influence, and is larger than 10 −4 kg / cm 2 and larger than 5 × 10 2 kg / cm 2 . By covering the joint with an organic insulating resin that generates a small compressive stress, the mechanical stress prevents the Al electrode film from rearranging and raising the joint when energized to the semiconductor body. As a result, a semiconductor device having greatly improved power cycle capability was obtained.
第１図は本発明の一実施例の半導体装置の要部断面図、
第２図は従来の半導体装置と第１図に示した半導体装置
のパワーサイクル耐量とオン・オフ時における温度差と
の関係線図である。 1:基板、2:絶縁板、3:接続導体板、4:半導体素体、5:Al
電極膜、6:Al導線、7:ポリイミド膜。FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention,
FIG. 2 is a diagram showing the relationship between the power cycle capability of the conventional semiconductor device and the semiconductor device shown in FIG. 1 and the temperature difference at the time of ON / OFF. 1: substrate, 2: insulating plate, 3: connecting conductor plate, 4: semiconductor body, 5: Al
Electrode film, 6: Al conductor, 7: polyimide film.
Claims (1)
に設けられたアルミニウム膜からなる電極にアルミニウ
ム線がボンディング接合されるものにおいて、電極のア
ルミニウム線との接合部が10-4kg/cm2より大きく５×10
2kg/cm2より小さい圧縮応力を接合部に発生させる有機
絶縁性樹脂によって被覆されたことを特徴とする半導体
装置。An aluminum wire is bonded to an electrode made of an aluminum film provided on a side opposite to a substrate of a semiconductor body fixed on a substrate, wherein a bonding portion between the electrode and the aluminum wire is 10 -4. 5 x 10 larger than kg / cm 2
A semiconductor device coated with an organic insulating resin that generates a compressive stress of less than 2 kg / cm 2 at a joint.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215645A JP2570428B2 (en) | 1989-08-22 | 1989-08-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215645A JP2570428B2 (en) | 1989-08-22 | 1989-08-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0379062A JPH0379062A (en) | 1991-04-04 |
| JP2570428B2 true JP2570428B2 (en) | 1997-01-08 |
Family
ID=16675836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1215645A Expired - Lifetime JP2570428B2 (en) | 1989-08-22 | 1989-08-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570428B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112014006759B4 (en) * | 2014-07-30 | 2019-02-21 | Hitachi, Ltd. | Semiconductor device, method for manufacturing a semiconductor device and power conversion device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5936933A (en) * | 1983-05-25 | 1984-02-29 | Hitachi Ltd | Formation of passivation film |
-
1989
- 1989-08-22 JP JP1215645A patent/JP2570428B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0379062A (en) | 1991-04-04 |
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