JPS5936933A - Formation of passivation film - Google Patents
Formation of passivation filmInfo
- Publication number
- JPS5936933A JPS5936933A JP58090681A JP9068183A JPS5936933A JP S5936933 A JPS5936933 A JP S5936933A JP 58090681 A JP58090681 A JP 58090681A JP 9068183 A JP9068183 A JP 9068183A JP S5936933 A JPS5936933 A JP S5936933A
- Authority
- JP
- Japan
- Prior art keywords
- film
- passivation film
- bonding pad
- dam
- polyimide resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、パシベーション膜の製法に関′１−る。[Detailed description of the invention] The present invention relates to a method for manufacturing a passivation film.
一般に、ダイオード、トランジスタ等の半導体素子並び
にこれらの素子を集積したＩＯ＋ＬＳＩは、外部雰囲気
たとえば水分−′Ｐ有杏不ＪｊＬ’物等の影響を受けや
すくその特性が劣化しやすい。その一つに基体表面のア
ルミニウム配線層の腐食問題があり、特に樹脂−Ｍ正形
半導体装置では、エポキシ系樹脂等封止に用いる樹脂が
吸水性であることから大きな問題である。In general, semiconductor elements such as diodes and transistors, as well as IO+LSIs in which these elements are integrated, are susceptible to the influence of external atmosphere, such as moisture, and their characteristics tend to deteriorate. One of these problems is the corrosion of the aluminum wiring layer on the surface of the substrate, which is a serious problem especially in resin-M type semiconductor devices because the resin used for sealing, such as epoxy resin, is water-absorbing.
従来、上記アルミニウム配線層の腐食を防止する方法と
しては、アルきニウム配線層トを酸化シリコン等のバシ
ベ〜ジョン膜で覆う方法が一般に用いられている。その
場合、そのパシベーション膜を形成する方法としては、
アルミニウムの融点を考慮して低温の化学気相成長法（
ＯＶＤ法）あるいはスパッタ法等が用いられる。Conventionally, as a method for preventing corrosion of the aluminum wiring layer, a method has generally been used in which the aluminum wiring layer is covered with a vacillation film of silicon oxide or the like. In that case, the method for forming the passivation film is as follows:
Considering the melting point of aluminum, low-temperature chemical vapor deposition method (
OVD method) or sputtering method is used.
ところで、上記アルミニウム配線層上を覆うパシベーシ
ョン膜は、それを厚くすればするほどその耐雰囲気性（
すなわち保護性）を向上させることができる。耐雰囲気
性を容認できる厚はとしては、膜の種類にもよるが最低
２〜３μｍ８度である。しかしこの様に上記パシベーシ
ョン膜を厚く形成しようとする場合、ＯＶＤ法では１〜
１，５μｍ以上になるとクラックが発生しゃすく、また
スバゾタ法では膜の生成速度が極めて遅い等の問題が生
ずる。By the way, the thicker the passivation film that covers the aluminum wiring layer, the more its atmospheric resistance (
In other words, protection) can be improved. The thickness that allows for acceptable atmosphere resistance is at least 2 to 3 μm and 8 degrees, although it depends on the type of film. However, when trying to form the passivation film thickly in this way, the OVD method
When the thickness exceeds 1.5 .mu.m, cracks are likely to occur, and in the Subazota method, problems arise such as extremely slow film formation speed.
一万、上記パシベーション膜材料としてポリイミド樹脂
等の有機樹脂膜を用いる方法がある。この方法では、樹
脂溶液の粘度あるいは塗布時の回転数をコントロールす
ることにより、容易に厚膜な′得ろことができる。しか
しながら、このパシベーション膜としての有機樹脂膜は
、基体上面全体に形成されてスクライプ領域にも膜厚の
大なる有機樹脂膜が形成きれることより、ダイ分割時に
スクライプがやりにくいと共に、スクライプ領域近傍の
有機樹脂膜が下地膜とはがれたりあるいはそれ自体がひ
っかき等の機械的価撃に弱いため破損したりして信頼度
の悪いパシベーション膜になってしまう欠点がある。However, there is a method of using an organic resin film such as polyimide resin as the passivation film material. In this method, a thick film can be easily obtained by controlling the viscosity of the resin solution or the rotation speed during coating. However, this organic resin film as a passivation film is formed on the entire upper surface of the substrate, and a thick organic resin film can be formed even in the scribe area, which makes it difficult to scribe when dividing the die, and also makes it difficult to scribe the area near the scribe area. There is a drawback that the organic resin film may peel off from the base film or may be damaged due to its vulnerability to mechanical shock such as scratching, resulting in an unreliable passivation film.
それゆえ本発明の目的は、上述した従来の諸問題を解決
し、もって高信頼度のパシベーション膜を得るパシベー
ション膜の製法を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a passivation film that solves the above-mentioned conventional problems and thereby provides a highly reliable passivation film.
本発明によれば、素子およびボンティングパッド電極を
半導体基体に形成し、該ボンディングバノド電極にワイ
ヤをボンディングした後、前記ボンティングパッド電極
部を訝む前記半導体基体の表面をポリイミド樹脂で覆う
ことを特徴とする。According to the present invention, after forming an element and a bonding pad electrode on a semiconductor substrate and bonding a wire to the bonding pad electrode, the surface of the semiconductor substrate surrounding the bonding pad electrode portion is covered with a polyimide resin. It is characterized by
第１図〜第２図は、本発明の検討段階で、本発明者が考
えたＭＯ８ＩＯにおけろパシベーション膜の製法を工程
順に示す断面図である。同図を用いて本発明にかかるＭ
Ｏ８ＩＯにおけるパシベーション膜の製法を工程順に詳
述する。FIGS. 1 and 2 are cross-sectional views showing, in order of steps, a method for manufacturing a passivation film in MO8IO, which was considered by the inventor at the stage of studying the present invention. M according to the present invention using the same figure.
A method for manufacturing a passivation film in O8IO will be explained in detail in the order of steps.
ｔ７″）まず、第１図に略本するようなＭＯ８素子が形
成された基体（ウェーハ）を用意する。同図において、
■は、シリコンウェーハで、この表面にソース並びにド
レインである拡散層１ａ、ｌｂが設けられている。２は
、フィールド酸化シリコン膜、３は、ゲート酸化シリコ
ン膜、４は、ゲート電極である低抵抗の多結晶シリコン
層、４ａは、ソースを極並びにソース用配＃ｉ層、４ｂ
〜４ｃは、第１層配線層、５は、リンシリケートガラス
膜などの絶縁膜、６と６ａは、アルミニウム配線層等の
第２層配線層、７は、第２層配線層を保護するための酸
化シリコン膜等の絶縁膜、８は、ボンディングバノド領
域である。t7'') First, a substrate (wafer) on which MO8 elements are formed as schematically shown in FIG. 1 is prepared. In the same figure,
(2) is a silicon wafer, on the surface of which diffusion layers 1a and 1b, which serve as a source and a drain, are provided. 2 is a field silicon oxide film, 3 is a gate silicon oxide film, 4 is a low-resistance polycrystalline silicon layer which is a gate electrode, 4a is a source pole and source wiring #i layer, 4b
4c is a first wiring layer, 5 is an insulating film such as a phosphosilicate glass film, 6 and 6a are a second wiring layer such as an aluminum wiring layer, and 7 is for protecting the second wiring layer. An insulating film such as a silicon oxide film 8 is a bonding band region.
すなわち、第１図に略本するものは、シリコンウェーハ
１に選択不純物拡散等の種々のウェーハ処理を施こして
ＭＯ８累子素子設け、その後にこれらのＭＯ８素子等の
電極並びに相互配線を多層配線構造にしてシリコンウェ
ーハ・１上に設けたものである。In other words, what is schematically shown in FIG. 1 is to perform various wafer treatments such as selective impurity diffusion on a silicon wafer 1 to provide MO8 cumulative elements, and then to connect electrodes and interconnections of these MO8 elements with multilayer wiring. The structure is provided on a silicon wafer 1.
（イ）第１図に示すような基体上面全体にボンデイング
バノド電極および本発明にかかるダムを形成するための
アルミニウム膜を形成し、フオトエ・ンチング技術を用
いて不要なアルミニウム膜を取り除いてボンデインダバ
ンド電極９並びにダム１０を同時に形成する（第２図）
。ダム１０の形状として種々の態様のものとすることが
できるが、本実施例においては、ポンプイングツくノド
ＩＩ極９の内周縁に閉じた形状をもって形成し２、その
膜厚は１μｍ程度のものとする。なお、本実施例におい
ては、ダム１０の製作にあたっては、ポンディングパッ
ド酸、極９を形成するためのアルシミニウム真空蒸着膜
→フォトエツチングによるノくターン形成というプロセ
スを利用しているが、これに限定されず、ポンディング
パッド電極９とは別個の製造プロセスを用い、その材料
としてアルミニウムではｉＣ＜、種々の金属膜あるいは
絶縁膜を用いて製作することができろ。(a) An aluminum film for forming a bonding vane electrode and a dam according to the present invention is formed on the entire upper surface of the substrate as shown in FIG. 1, and unnecessary aluminum film is removed using a photo-etching technique to bond Forming the in-band electrode 9 and dam 10 at the same time (Fig. 2)
. The shape of the dam 10 can be various, but in this embodiment, it is formed in a closed shape on the inner peripheral edge of the pump throat II pole 9, and the thickness of the dam is about 1 μm. do. In this embodiment, the dam 10 is manufactured using a process in which a bonding pad acid is used, an aluminum vacuum-deposited film for forming the pole 9 is turned, and a notch is formed by photoetching. The bonding pad electrode 9 can be manufactured using a manufacturing process different from that of the bonding pad electrode 9, using aluminum as the material, various metal films, or insulating films.
（つ）ついで、ダム１０内側の絶縁膜７にパシベーショ
ン膜としてポリイミド樹脂の液状の絶縁物１１滴下法に
より充填する。この場合、ポリイミド樹脂の液状のＰ３
縁物１１は、その表面張力とダム１０の膜厚とにより、
ダム１０の膜厚の２〜３倍の高さにもつあがる。しかも
液状の絶縁物１１を滴不塗布するものであるために、シ
リコンウェーハ】上の絶縁膜７表面の凹凸部を埋めしか
もその絶縁物１１表面は、この下地膜である、絶縁膜７
表面の凹凸にもかかわらず平坦なものとなる。(1) Next, the insulating film 7 inside the dam 10 is filled with a liquid insulating material 11 of polyimide resin as a passivation film by a dropping method. In this case, liquid P3 of polyimide resin
Due to its surface tension and the thickness of the dam 10, the edge 11
It also rises to a height that is two to three times the thickness of the dam 10. Moreover, since the liquid insulator 11 is not applied dropwise, it fills in the irregularities on the surface of the insulating film 7 on the silicon wafer, and the surface of the insulator 11 is coated with the insulating film 7, which is the underlying film.
Despite the unevenness of the surface, it is flat.
（勾 ついで、熱処理を行なってポリイミド樹脂の液状
の絶縁物１１を硬化させて（ベーキング処理）、パシベ
ーション膜１１ ａ 全形成”ｆル。(Then, heat treatment is performed to harden the liquid insulator 11 made of polyimide resin (baking treatment), and the passivation film 11a is completely formed.
（３） シリコンウェーハ１−ヒのスクライプ領域にダ
イヤモンドツール等で鳩を入れ、しかる後ダイ分割しＩ
Ｃチップを得る（舗２図）、、ついで、１０チツプをダ
イボンディングし、金線やアルミニウム線等の金属細線
をホンディングバッド電極９にワイヤボンディング−ｊ
６゜
上述した本発明にかかるＭＯ８ＩＯにおけるバシベーシ
ョン膜の製法は、パシベーション１ｌｌａを形成する前
にあらかじめ、所定の膜厚をもってダム】Ｏを設けてお
き、このダム１０内に液状の絶縁物１１を滴下法等によ
り充填して、この充填きれた液状の絶縁物をダム１０に
よって堰止めて所定の厚膜に形成するものであ乞。その
ため、従来においてパシベーションｐＡ１１ ａとして
のポリイミド樹脂膜を数μｍ形成する際には、塗布やベ
−り等の作業時間が８時間程度必要であった（数回の塗
布、ベーク作業を行なって数μｎ〕の厚膜を得る必要が
ある）ものが、本発明にかかるパシベーション膜の製法
によれば、ポリイミド樹１１１Ｎヲ形成するための塗布
、ベーク作業時間を９０分程度に短縮することができる
。(3) Insert a dove into the scribe area of silicon wafer 1-1 using a diamond tool, etc., and then divide the die.
Obtain C chips (Fig. 2).Next, 10 chips are die-bonded, and a thin metal wire such as gold wire or aluminum wire is wire-bonded to the bonding pad electrode 9.
6. The method for manufacturing the passivation film in MO8IO according to the present invention described above is to provide a dam with a predetermined film thickness in advance before forming the passivation layer 1lla, and to fill the liquid insulator 11 within this dam 10. The insulator is filled by a dripping method or the like, and the filled liquid insulator is dammed by the dam 10 to form a predetermined thick film. Therefore, in the past, when forming a polyimide resin film of several micrometers as passivation pA11a, it took about 8 hours for coating, baking, etc. According to the passivation film manufacturing method according to the present invention, the coating and baking time for forming the polyimide tree 111N can be shortened to about 90 minutes.
また、本発明にかかるパシベーション膜の製法によれば
、ダム１（１の膜厚を所定の値に設定することにより、
所望の膜厚を液状の絶縁物］１の塗布燵を機械的にコン
トロールして自動的にかつ制御よく得ることができろ。Further, according to the method for manufacturing a passivation film according to the present invention, by setting the film thickness of the dam 1 (1) to a predetermined value,
A desired film thickness can be obtained automatically and with good control by mechanically controlling the coating method of liquid insulating material (1).
そのため、自動化したパシベーション膜の製作ができる
。Therefore, automated production of passivation films is possible.
さらに本発明は、ウェーハ処理工程中に、パシベーショ
ン膜を形成することができ、しかもスクライブ領域には
パシベーション膜１１ａを被覆することなく、ダイ分割
できるものである。そのため、ダイ分割はパシベーショ
ン膜の膜厚にかかわりなく容易となり、ダイ分割時にバ
シベ〜ジョン換１１ａに何らの３Ｍ傷をも与えず、厚膜
とあいまって高信頼度のパシベーション膜１１ａを得る
ことができる。Further, according to the present invention, a passivation film can be formed during the wafer processing process, and die division can be performed without covering the scribe area with the passivation film 11a. Therefore, die separation becomes easy regardless of the film thickness of the passivation film, no 3M damage is caused to the passivation film 11a during die separation, and a highly reliable passivation film 11a can be obtained due to the thick film. can.
第３図〜第４図に略本するものは、上記製法の変形例と
して完成された本発明の実施例であるＭ０８１０におけ
るパシベーション膜の製法を工程順に示す断面図である
。本発明のパシベーション膜の製法は、ポンディングパ
ッド電極の外周縁にダムを設け、ワイ・ヤボンディング
後に、液状の絶縁物を塗布しベー りしたものである。3 and 4 are cross-sectional views showing, in order of steps, a method for manufacturing a passivation film in M0810, which is an embodiment of the present invention completed as a modification of the above manufacturing method. The method for manufacturing the passivation film of the present invention is to provide a dam on the outer periphery of the bonding pad electrode, and after wire bonding, apply a liquid insulator and base it.
本発明のものは、前述したパシベーション膜の製法に比
して、ポンディングパッドｔｍをもパシベーション膜に
より被覆したことに特長がある。The present invention is characterized in that the bonding pad tm is also covered with a passivation film, compared to the above-mentioned passivation film manufacturing method.
なお、本発明において、下地膜として酸化シリコン膜な
どの絶縁膜上にポリイミド樹脂のパシベーション膜を形
成したものであるが、ポリイミド樹脂膜と下地膜との密
着性を改善するために下地膜として酸化シリコン膜上に
アルミナ膜を形成し７た絶縁膜とずイ）こともできる。In the present invention, a polyimide resin passivation film is formed as a base film on an insulating film such as a silicon oxide film, but in order to improve the adhesion between the polyimide resin film and the base film, an oxidized base film is It is also possible to form an insulating film by forming an alumina film on a silicon film.
本発明は、ＭＯ５ＩＯに訃けるパシベーション膜の製法
に限定されず、ダイオ−ドウトランジスタ、１０．ＬＳ
Ｉ等種々の半導体装置あるいはハイフＩＩッド１０等の
種々の態様の電子部品におけろパシベーション膜の製法
に適用でき、所望の厚膜で膜性特に耐雰囲気性にすぐれ
た昼信頼度のパシベーション膜を得ろことができる。The present invention is not limited to the method of manufacturing a passivation film for MO5IO, but also for diode transistors, 10. L.S.
It can be applied to the manufacturing method of passivation films for various semiconductor devices such as I and various types of electronic components such as HiF II, etc., and has a desired thickness, excellent film properties, particularly atmospheric resistance, and daytime reliability passivation. You can get a membrane.
第１図〜第２図は本発明の検討段階で、本発明者によっ
て考えられたパシベーション膜の製法を示す断面し１、
第３図〜第４図は、本発明であるＭＯ８ＩＯにおけろパ
シベーション膜の製法を工程順に示す断面図である。
１・・・シリコンウェーハ、ｌａ、ｌｂ・・・ＭＩＪ１
層、２・・・フィールド酸化シリコン膜、３・・・ゲー
ト酸化シリコン膜、４〜４ｃ・・・第１層配線層、５・
・・層間絶縁膜、６，６ａ・・・第２層配線ｌ−１７・
・・絶縁膜、９・・・ポンディングパッドｔａ、１０・
・・タム、１１ａ・・・パシベーションｉ、１２・・・
ボンディングワイヤ。Figures 1 and 2 are cross-sectional views showing a method of manufacturing a passivation film devised by the inventor at the stage of research into the present invention. FIG. 3 is a cross-sectional view showing a method for manufacturing a membrane in the order of steps. 1...Silicon wafer, la, lb...MIJ1
Layer 2... Field silicon oxide film, 3... Gate silicon oxide film, 4-4c... First layer wiring layer, 5...
...Interlayer insulating film, 6, 6a...2nd layer wiring l-17.
...Insulating film, 9...Ponding pad ta, 10.
... Tam, 11a... Passivation i, 12...
bonding wire.
Claims (1)
に形成し、該ポンディングパッド電極にワイヤをボンデ
ィングした後、前記ポンディングパッド電極部を含む前
記半導体基体の表面をポリイミド樹脂で覆うことを特徴
とするパシベーション膜の製法。1. After forming an element and a bonding pad ta on a semiconductor substrate and bonding a wire to the bonding pad electrode, the surface of the semiconductor substrate including the bonding pad electrode portion is covered with polyimide resin. Manufacturing method of passivation film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58090681A JPS5936933A (en) | 1983-05-25 | 1983-05-25 | Formation of passivation film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58090681A JPS5936933A (en) | 1983-05-25 | 1983-05-25 | Formation of passivation film |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6001976A Division JPS52143766A (en) | 1976-05-26 | 1976-05-26 | Production of passivation film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5936933A true JPS5936933A (en) | 1984-02-29 |
Family
ID=14005272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58090681A Pending JPS5936933A (en) | 1983-05-25 | 1983-05-25 | Formation of passivation film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936933A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0379062A (en) * | 1989-08-22 | 1991-04-04 | Fuji Electric Co Ltd | Semiconductor device |
-
1983
- 1983-05-25 JP JP58090681A patent/JPS5936933A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0379062A (en) * | 1989-08-22 | 1991-04-04 | Fuji Electric Co Ltd | Semiconductor device |
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