JP2560765B2 - Large area semiconductor substrate manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A method for manufacturing a large-area semiconductor substrate, in which a silicon carbide thin film is epitaxially grown on a silicon wafer for the purpose of providing a semiconductor substrate having a size larger than a wafer scale. , A plurality of the silicon wafers are spread so that the silicon carbide thin film is in contact with a substrate having a size larger than that of the silicon wafer, and then the substrate and the silicon wafer are bonded to each other, and the silicon wafer bonded to the substrate is selected. Of the silicon carbide thin film is exposed on the substrate by mechanically etching and removing it.

[Industrial applications]

The present invention relates to a method for manufacturing a large-area semiconductor substrate having a size larger than a wafer scale.

[Prior Art] A semiconductor substrate used for manufacturing a semiconductor integrated circuit has been increasing in scale. The reason for this is to improve the productivity because it is possible to manufacture more integrated circuit chips in the same number of steps by using a large-area, large-diameter wafer. Conventionally, a pulling method (CZ method) has been used as a method for obtaining the largest-scale wafer, and a wafer having a diameter of 8 inches to 12 inches is manufactured.

[Problems to be solved by the invention]

However, the CZ method requires enormous equipment for manufacturing large-diameter (large-area) wafers. The diameter of the wafer produced by the CZ method depends on the pulling rate during single crystal growth. The larger the diameter, the slower the pulling rate must be. However, the slower the pulling rate, the more defects in the crystal tend to increase. Therefore, it becomes difficult to obtain a good quality single crystal. However, at present, there is no alternative to the CZ method that has the potential to efficiently produce larger area wafers.

The main object of the present invention is to be able to provide a large-area semiconductor substrate having a size larger than the current wafer scale.

[Means for solving problems]

The above-mentioned object is to have a semiconductor wafer scale size
Forming a single crystal semiconductor layer made of a semiconductor material which is not etched when the first substrate is removed by etching, and a first crystal substrate which is made of a material which is difficult to be etched when the first substrate is removed by etching. A plurality of the first substrates are formed on a second substrate having a size larger than that of the first substrate, and the single crystal semiconductor layers are spread so as to be in contact with the second substrate, and then the first substrate is spread. And a step of bonding the second substrate, and a step of selectively etching away the first substrate bonded to the second substrate to expose the single crystal semiconductor layer on the second substrate. It is achieved by the method for manufacturing a large area semiconductor substrate according to the present invention, which comprises:

[Work]

For example, a silicon carbide (SiC) thin film is epitaxially grown on one surface of a currently available silicon wafer, and a plurality of silicon wafers are spread on a substrate such as a glass plate having a size larger than that of the silicon wafer so that the SiC thin films are in contact with each other. After that, after bonding the substrate and the silicon wafer, the silicon wafer is selectively removed by etching to expose the SiC thin film. In this way, a substrate in which a plurality of single crystal semiconductor layers each made of an epitaxially grown SiC thin film are closely arranged is prepared. This substrate has an SOI structure. In addition, it is possible to provide an integrated circuit substrate having a larger area than the integrated circuit wafer currently in practical use.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view for explaining the principle of the present invention. First, a plurality of silicon wafers 2 each having a SiC (Epi-SiC) thin film 1 having a thickness of about 3000 Å epitaxially grown as described later are formed, as shown in FIG. 1A, for example, BPSG (borophosphosilicate glass). ) On the substrate 3 consisting of
After the SiC thin film 1 is in contact with the substrate 3 and is spread without any gap, the silicon wafer 2 and the substrate 3 are heated to bond the silicon wafer 2 and the substrate 3. Next, when the silicon wafer 2 is selectively removed by etching or the like, the Epi-SiC thin film 1 is left on the substrate 3 as shown in FIG.

Substrates 3 on which the Epi-SiC thin film 1 is formed can be formed on the Epi-SiC thin film 1 by implanting impurities, forming insulating layers and electrodes / wiring layers, and performing processing such as etching. Can be used as a large-area semiconductor substrate.

The large area semiconductor substrate obtained as described above is SOI (S
Silicon on Insulator) has the same structure, and has the advantage of being able to manufacture high-performance, highly integrated semiconductor integrated circuits. A gap may exist at the boundary between the Epi-SiC thin films 1 arranged on the substrate 3, and a step may occur between the surface of the Epi-SiC thin film 1 and the upper surface of the substrate 3, but this step is at most the Epi-SiC thin film. Since the film thickness of 1 is about 3000 Å, there is no problem even if wirings for interconnecting integrated circuits formed on different Epi-SiC thin films 1 are formed on the stepped portion.

FIG. 2 is a sectional view of the silicon wafer 2 on which the Epi-SiC thin film 1 is formed. For epitaxially growing a SiC thin film on the silicon wafer 2, the method filed by the present applicant may be used. (JP-A-62-15
5512, July 10, 1987, JP-A-62-163370, 1987
July 20th, Japanese Patent Application No. 61-167823, July 18, 1986) In summary, a conventional low pressure CVD (Chemical Vapor Deposition) apparatus is used, for example SiHCl ₃ (trichlorosilane) and C ₃ H ₈ By reacting (Proban) on the surface of a silicon wafer heated to about 1000 ° C under reduced pressure, a single crystal SiC film grows on the surface of the silicon wafer.

FIG. 3 is a cross-sectional view showing a process of arranging the silicon wafer 2 on the substrate 3 and removing the silicon wafer 2. First, as shown in FIG. A large-area substrate 3 made of quartz containing is prepared. Next, as shown in FIG. 3B, the silicon wafer 2 on which the Epi-SiC thin film 1 is formed as described above is arranged on the substrate 3 with the Epi-SiC thin film 1 facing downward. In this case, it is convenient that each silicon wafer 2 has a rectangular shape, but it is not limited to a rectangular shape, but may have a rhombic shape, and other asymmetrical shapes may be used as long as they can be arranged so as to be in close contact with each other. Absent. Normal,
Since the silicon wafer has a substantially circular shape, it may be processed into a rectangle or the like as described above either before or after the Epi-SiC thin film 1 is formed.

With the silicon wafers 2 arranged as shown in FIG. 3B, the substrate 3 is heated to a temperature at which it begins to soften. In the case of substrate 3 made of BPSG, this temperature is at least about 500 ° C.
In the case of the substrate 3 made of quartz containing a low concentration of impurities, the temperature is, for example, about 1200 ° C. As a result, the silicon wafer 2 and the substrate 3 are adhered and bonded.

Next, the silicon wafer 2 bonded to the substrate 3 is first thinned to a thickness of about 200 μm by a mechanical polishing method,
Further, the remaining silicon wafer 2 is treated with an aqueous solution of potassium hydroxide (KOH) or hydrofluoric acid (HF) and nitric acid (HN).
It is dissolved by immersing it in a known etching solution such as a mixed solution of O ₃ ). Since the Epi-SiC thin film 1 does not dissolve in this etching solution, it remains bonded to the substrate 3 as shown in FIG. 3 (c).

As described above, the number of ordinary silicon wafers or
A large-area semiconductor substrate having the Epi-SiC thin film 1 formed on the insulating substrate 3 having a large area of about 10 times as a single crystal semiconductor layer can be obtained. An integrated circuit is formed on the Epi-SiC thin film 1 according to a normal integrated circuit manufacturing process.

On the other hand, the Epi-SiC thin film 1 on the silicon wafer 2 before being bonded to the substrate 3 can be previously subjected to a process for forming an integrated circuit. An example of such processing will be described with reference to FIG.

Referring to FIG. 4 (a), a resist mask 5 having an opening in a predetermined region is formed on the Epi-SiC thin film 1 formed on the silicon wafer 2, and the Epi exposed in the opening is formed.
Impurities are implanted into the -SiC thin film 1 by using a known method such as ion implantation, and further heat-treated to form an impurity implantation layer 6. Like the impurity injection layer 61, this impurity injection layer can be formed to a depth reaching the silicon wafer 2. In such a deep impurity implantation layer 61, the silicon wafer 2 is bonded to the substrate 3 (not shown) later,
It can be used as a contact region on the surface of the Epi-SiC thin film 1 that appears when selectively removed. Generally, a high-concentration impurity is implanted in the impurity-implanted layer 61 for such a purpose.

Next, referring to FIG. 4 (b), an insulating layer such as SiO ₂ is formed on the Epi-SiC thin film 1 on which the impurity injection layer 6 and the like are formed as described above by using, for example, a known CVD technique. 7 may be formed. Further, a resist mask 8 having an opening provided in a predetermined region is formed on the insulating layer 7, and the insulating layer 7 exposed in the opening is removed by etching to remove the impurity implantation layer 6
It is also possible to form contact holes for the like.

Further, referring to FIG. 4 (c), the Epi-SiC thin film 1 on the silicon wafer 2 is selectively masked by a resist mask 9 to remove the exposed Epi-SiC thin film 1 from, for example, SiCl 2.
It is also possible to perform selective etching by known anisotropic dry etching using a mixed gas of ₄ (silicon tetrachloride) and Cl ₂ (chlorine). Further, after removing the resist mask 9, another semiconductor layer is formed on the selectively etched portion of the Epi-SiC thin film 1 as shown in FIG. 4 (d).
10 may be epitaxially grown.

Furthermore, referring to FIG. 4 (e), in a predetermined region on the Epi-SiC thin film 1 in which the impurity-implanted layers 6 and 61 are formed as described above, the same process as a normal integrated circuit manufacturing process is performed. , Gate electrode 11 and gate insulating layer 12 are formed and MOS
A transistor structure may be formed. In addition, Epi-SiC
Forming an interlayer insulating layer 13 on the thin film 1 and the gate electrode 11,
After forming a contact hole at a predetermined position in the interlayer insulating layer 13,
For connecting the impurity injection layer 6 forming the drain of the MOS transistor and the impurity injection layer 61 forming the contact region, for example, dungsten (W), gold (Au) or copper (Cu), or a refractory metal The wiring layer 14 made of silicide may be formed on the interlayer insulating layer 13.

As shown in FIG. 4A or FIG. 4E, when a deep impurity implantation layer 61 is previously formed in the Epi-SiC thin film 1 on the silicon wafer 2, the silicon wafer 2 is bonded to the substrate 3 and then selected. The impurity-implanted layer 61 is exposed on the surface of the Epi-SiC thin film 1 exposed by the selective removal. As shown in FIG. 5, a wiring layer 15 made of, for example, an Al (aluminum) layer is provided between the impurity-implanted layers 61, so that the circuit elements formed on the same or different Epi-SiC thin films 1 or Integrated circuits (both not shown) can be interconnected.

FIG. 6 is a sectional view showing another embodiment of the present invention,
Similarly to the above, after the Epi-SiC thin film 1 is formed on the silicon wafer 2, the BPSG layer 16 having a thickness of about 0.5 μm, for example, is formed on the Epi-SiC thin film 1 by using the known CVD technique. I'll do it. Similar to FIG. 1, such a silicon wafer 2 is placed close to each other on the substrate 3 so that the BPSG layer 16 is in contact with the substrate 3 and then heated at a temperature at which the BPSG layer 16 begins to soften. , The silicon wafer 2 and the substrate 3 are bonded together.
Thereafter, the silicon wafer 2 is removed in the same manner as in the above embodiment.

According to this embodiment, since the BPSG layer 16 acts as an adhesive layer between the silicon wafer 2 and the substrate 3, the heating temperature at the time of bonding can be changed to a desired temperature by adjusting the components of the BPSG layer 16. There is an advantage that the substrate 3 can be made of a high melting point ceramic such as alumina.

In addition, in the above-mentioned embodiment, on the silicon wafer 2.
Although the case where the Epi-SiC thin film 1 is produced is shown, a single crystal semiconductor layer made of a diamond thin film, a BN (boron nitride) thin film or the like may be grown on the silicon wafer 2. Also,
It is needless to say that the first substrate is not limited to the silicon wafer, and another single crystal or amorphous semiconductor substrate or an insulating substrate can be used depending on the method for forming the single crystal semiconductor layer.

In addition, since the Epi-SiC thin film has excellent heat resistance and a large refractive index, it was formed by the above method.
It is possible to fabricate a heat-resistant and high-reflectance reflecting mirror using an Epi-SiC thin film as a reflecting surface. Such a heat-resistant reflecting mirror can be used as a reflecting mirror for high-power laser light or microwaves.

Furthermore, the large area semiconductor substrate of the present invention can be applied to a liquid crystal display. That is, the substrate 3
If a transparent glass plate is used as the substrate and the thickness of the SiC layer formed thereon is thinned to 0.1 to 1 μm, a substrate having high light transmittance can be obtained. Then, a transistor or a stripe-shaped or matrix-shaped circuit is formed on this SiC layer, and a liquid crystal layer is sandwiched between two such substrates to form a liquid crystal display. As a result, a liquid crystal display in which a driving transistor, a memory cell, or both are arranged for each liquid crystal cell can be obtained.

〔The invention's effect〕

According to the present invention, an SOI larger than an ordinary semiconductor wafer
A large-area semiconductor substrate having a structure can be provided. This large-area semiconductor substrate has the effect of promoting higher performance and lower cost of semiconductor integrated circuits, as well as a heat-resistant reflecting mirror, large-area,
As mentioned in the example of high-performance flat panel display type,
This has the effect of facilitating the development of various applied devices.

[Brief description of drawings]

FIG. 1 is a perspective view for explaining the principle of the present invention, FIG. 2 is a sectional view of a silicon wafer on which an Epi-SiC thin film is formed, and FIG. 4 is a cross-sectional view showing the steps of the present invention, FIG. 4 is a cross-sectional view for explaining an example of a treatment preliminarily performed on the Epi-SiC thin film, and FIG. 5 is an Epi-SiC thin film exposed after bonding with the substrate. FIG. 6 is a perspective view showing a wiring layer formed on the surface, and FIG. 6 is a sectional view showing another embodiment of the present invention. In the figure, 1 is an Epi-SiC thin film, 2 is a silicon wafer, 3 is a substrate, 5 and 8 and 9 are resist masks, 6 and 61 are impurity injection layers, 7 is an insulating layer, 10 is a semiconductor layer, and 11 is a gate electrode. , 12 is a gate insulating layer, 13 is an interlayer insulating layer, 14 and 15 are wiring layers, and 16 is a BPSG layer.

Claims (1)

(57) [Claims] 1. A step of forming on a first substrate a single crystal semiconductor layer made of a semiconductor material which is not etched when the first substrate is removed by etching, and a step of hardly etching when the first substrate is removed by etching. A plurality of the first substrates formed on a second substrate made of a material and having a dimension larger than that of the first substrate, the single crystal semiconductor layers being in contact with the second substrate. And then bonding the first and second substrates together, and selectively etching away the first substrate bonded to the second substrate to remove the single crystal on the second substrate. A method of manufacturing a large-area semiconductor substrate, comprising the step of exposing a semiconductor layer.