JP2560654B2 - Signal processing circuit - Google Patents

Description

Detailed Description of the Invention [0001] BACKGROUND OF THE INVENTION The present invention relates to a television receiver.
In particular, NTSC system specifications caused by VTRs, etc.
Optimal signal processing is applied to non-standard signals that do not satisfy
The present invention relates to a signal processing circuit required. [0002] 2. Description of the Related Art In conventional television receivers, color signals
(C) is frequency-multiplexed with the luminance signal (Y)
Due to cross color, dot interference, and interlace
Line flicker and vertical resolution degradation due to source scanning
Is known to occur. Nikkei Elect in recent years
Ronix, July 1, 1985, pp. 195-2.
Page 18, Journal of the Television Society 1982 Volume 36, No. 1
No. 0, as discussed on pages 76-84
In addition, in order to improve the image quality by excluding these image quality deterioration factors
In addition, using semiconductor memory and digital signal processing technology,
Frame comb fill using the correlation of images in the time direction
Y / C separation by the data, scanning line by inter-field interpolation
The introduction of spatio-temporal processing technology such as double density and progressive scan conversion
It is considered. However, these means for improving image quality are
It is effective for still images as you know, but moving images
Will generate an interfering signal. So,
Image motion is detected from the difference signal between frames, and a still image is displayed.
For frame comb filter, inter-field interpolation
Spatio-temporal processing such as
If you stop the processing of and switch to spatial processing in the field
Introducing the so-called motion adaptive processing,
It is known that it enhances the practicality of science and realizes high image quality.
ing. [0003] SUMMARY OF THE INVENTION The above-mentioned prior art is based on the color sub-method.
Carrier frequency f_sc, Horizontal scanning frequency f_H, Vertical scanning frequency
Number f_VA television whose frequency is precisely controlled
John signal (hereinafter referred to as standard signal) is expected to be effective
You can wait, but home VTRs, personal computers, etc.
The color subcarrier frequency f_sc, Horizontal scanning frequency f_H,
Vertical scanning frequency f_VIs not related to the specified frequency
About vision signals (hereinafter referred to as non-standard signals)
There was a problem that the effect could not be expected. Taking the NTSC system as an example, the color sub
Carrier frequency f_scAnd horizontal scanning frequency f_HBetween [0005] [Equation 1] Of the horizontal scanning frequency f_HAnd vertical scanning frequency f_VWith
In between [0006] (Equation 2) The relationship is defined as follows, and between the luminance signal and the color signal
The frequency interleave relationship holds. This is the color vice
The phase of the carrier wave becomes opposite in phase between the signals separated by one frame period.
Indicates that Using this fact, the sum of frames
Frame comb shape, such as luminance signal from difference and color signal from difference
Can be realized. However, the frequency f_sc, F_H, F_VIs the number
1] and [Equation 2] are not satisfied, the frequency
Since the interleave relationship is not established, the luminance signal and the color signal
The image when it is determined that the image cannot be separated correctly and it is judged as a still image.
Deterioration of quality will be noticeable. Thus, conventional
In technology, it is important to understand the nature of standard / nonstandard signals.
Appropriate processing for non-standard signals
It was difficult to apply. The object of the present invention is to interfere with non-standard signals.
Non-standard signal detection times to achieve low signal processing
To provide a road. [0009] [Means for Solving the Problems]
Therefore, in the present invention, a synchronizing signal is input from the input television signal.
From the sync signal separated by n times the horizontal scanning cycle.
n × T_HPeriodic pulse (T_HIndicates the horizontal scanning period of the input signal
You. ) Is included in the television signal.
Phase synchronization with the color burst signal
Wave number f_scAPC that generates a clock with m times the frequency of
(Auto Phase Control) circuit, And the output pulse of this frequency divider and the n × T_HPeriodic pulse
The product which integrates the comparator which inputs and and the output of this comparator
A non-standard signal is detected by the output of the integrator with a divider.
You. [0010] [Action] Reference signal that divides and represents the color subcarrier frequency of the input signal
(Hereinafter, referred to as a carrier wave reference signal). Comparator
Is the carrier reference signal generated by this divider and the input signal
N × T indicating the frequency of the sync signal based on the sync signal_H
A cycle with a cycle reference signal (hereinafter referred to as a synchronization reference signal)
Compare the periods. If it is a reference signal, use [Equation 1], [Equation 2]
Since the two reference signals have the same period,
If they are standard signals, they will not match. The integrator is the comparison result
By accumulating
Determine whether. Therefore, from this integration result
Non-standard signals can be detected. [0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
You. Also, in all the following explanations, the NTSC system
Will be described as an example. 101 is an input terminal, 103 is
APC circuit, 105 is a frequency divider, 107 is a sync separation circuit,
110 is a synchronization reference generator, 112 is a comparator, and 113 is a product.
It is a divider. Television input from the input terminal 101
The signal is input to the APC circuit 103 and the sync separation circuit 107.
Becomes The APC circuit 103 outputs the television signal
The color burst signal included in
Phase locked loop that reproduces and outputs the desired clock 104
Is. The clock reproduced by this APC circuit (hereinafter referred to as A
104 is a color subcarrier frequency f._sc
Select a frequency that is m times higher. The sync separation circuit 107 is for inputting a television signal.
Horizontal sync signal 10 after separating the sync signal from the sync signal.
8 and a vertical sync signal 109, and a sync reference generator 110
Supply to. This sync reference generator 110 is
Either or both of the vertical sync signals 108 and 109
And the base of the sync signal frequency of the input TV signal.
A quasi-synchronous reference signal 111 is generated. This synchronization base
The quasi-signal 111 is one of the frequency divider 105 and the comparator 112.
It becomes an input. The frequency divider 105 uses the synchronization reference signal 111
Is initialized by and starts counting at the APC clock 104.
You. At this time, divide The color subcarrier frequency of the input signal
Other than the comparator 112 as the carrier wave reference signal 106 representing
Give to one input. The comparator 112 outputs the synchronization reference signal 11
Synchronization reference generated in the next cycle, with the frequency divider initialized by 1.
From the phase relationship between the pulse of the signal 111 and the pulse of the carrier reference signal,
Make a quasi / non-standard decision. That is, even if it is a standard signal
For example, since the above [Equation 1] and [Equation 2] are satisfied, the comparator 1
The phases of the two reference signals that are input to
If it is a signal, the phase of the pulse will shift, so
It is possible to compare the cycles due to the coincidence and non-coincidence of pulse phases.
You. This comparison result becomes the input of the integrator 113, and the disturbance
If the synchronization is disturbed due to, for example, the detection operation becomes unstable.
The comparison results, e.g.
Integration for a certain period of time. As a result, the detection results are safe.
The output 114 of this integrator 113 is non-standard detected
It becomes the signal 114. According to this embodiment, the color subcarrier frequency and the water
Determining whether or not the flat and vertical scanning frequencies have a predetermined relationship
It becomes possible to detect non-standard signals. Next, one implementation of the sync reference generator 110
An example will be described with reference to FIG. Reference numeral 201 is an AFC circuit, and 203 is a frequency divider.
You. The AFC circuit 201 comprises the sync separation circuit 1
The clock synchronized in phase with the horizontal synchronizing signal 108 extracted in 07.
Is a feedback loop that generates a clock. This A
Center frequency of VCO (voltage controlled oscillator) of FC circuit 201
For example the color subcarrier frequency It matches the horizontal scanning frequency of the television signal. But
The frequency divider 203 is To generate the synchronization reference signal 111 in the previous embodiment.
You will be able to live. Next, FIG. 3 shows the synchronization reference generator 110.
A second embodiment will be described. 301 is a mono-multi vibrator
Is. The mono multi-vibrator 301 is synchronized and separated.
The vertical synchronizing signal 109 that has been input
Is output. Therefore, in the previous embodiment,
The synchronization reference signal 111 is set to the field period, that is, n = 2.
When 62.5 is selected, the synchronization base is set as in this embodiment.
The quasi-generator 110 can be simplified. Also, n =
In case of selecting 1, the mono-multi vibrator
By using the horizontal sync signal 108 as an input,
Similarly, the synchronization reference signal 111 can be easily created. Next, FIG. 4 shows the synchronization reference generator 110.
A third embodiment will be described. 401 is an AFC circuit, 403 is an
Edge extraction circuit, and 404 is a gate circuit. This embodiment
Is the frame period, that is, the period of the synchronization reference signal 111.
That is, this is an example of the case of selecting n = 525. Sync
The separated horizontal synchronizing signal 108 is output from the AFC circuit 201.
It becomes an input and its output is phase-synchronized with it.
Generate horizontal sync pulse 402 as shown in 13 (p)
I do. In addition, the vertical synchronization signal 109 is a mono multi-vibrate.
Waveform is shaped by the lator 301 and is shown in FIG. 13 (n), for example.
A pulse having such a vertical scanning period is output. This vertical run
The pulse of the check cycle is output by the edge extraction circuit 403.
The falling edge of is extracted and, for example, as shown in FIG.
An extraction pulse is generated and applied to the gate circuit 404,
It is gated by the horizontal sync pulse 402. Horizontal sync signal
The vertical sync signal and the vertical sync signal are odd
Field and even field with phase 1/2 horizontal scanning period
It shifts. Therefore, at the output of the gate circuit 404, for example,
For example, if the field is out of phase as shown in Fig. 13 (q)
The edge signal for vertical synchronization is gated, and the
You can get Ruth. Next, the frequency divider 105, the comparator 112, and the integrator
One example showing the details of 113 is shown in FIG. 501 is
Counter, 502 is a shift register, and 503 and 510 are reset registers.
Set Set (RS) Philip flop (hereinafter RS-
Abbreviated as FF. ) 504 and 505 are NOT circuits, 50
6, 507 is an AND circuit, 508 is up / down (up)
/ Down) counter, 509 NOR circuit, 511
Edge extraction circuit, counter 501, shift register
Frequency divider 502, RS-FF 503, and NOT circuit 504
Device 105, NOT circuit 505, AND circuits 506, 5
07 up / down (up / down) the comparator 112.
n) Counter 508, NOR circuit 509, RS-FF5
10 constitutes an integrator, 113. The operation of FIG. 5 will be described with reference to FIG.
(A) is an APC clock with a frequency m times the color subcarrier frequency.
(B) is the carry output of the counter 501, (c)
Is the output of Q0 of the shift register 502, (d) is the shift
Output of Q3 of register 502, (e) RS-FF50
3 output, (f) output of NOT circuit 505, (g) ~
(H) is an output pulse 111 of the synchronization reference generator 110.
It is a figure showing an example of each. N × output from the synchronization reference generator 110
T_HThe period synchronization reference signal 111 is used as the edge extraction circuit 51.
Enter 1. The edge extraction circuit 511 is shown in FIG.
Sync reference input with APC clock (a) as shown in
Latch the signal (j) and re-latch the latched signal (k).
Signal that is delayed by one clock with respect to (k) and inverted.
Making the number (l) and obtaining the logical product of (k) and (l)
The APC clock for the rising edge of the sync reference signal.
Extracted as a 1-clock-wide pulse (m) synchronized with the clock
Things. The output of this edge extraction circuit 511 is NO.
Preset terminal of the counter 501 via the T circuit 504
Is given to each of the AND circuits 506 and 507.
It becomes the input of each one. The counter 501 is an APC black
Clock 104, synchronized with APC clock, edge
From the time when the extracted synchronization reference signal 512 is input Carry signal 513 is operated by APC clock 104
Input to the shift register 502 to
After the carry signal as shown in (b) is input, Q0
The output of Fig. 11 (c) and the output of Q3 are shown in Fig. 11 (d).
Carry signal is output by imming and RS-FF503
Set pulse and reset pulse. Therefore, RS
-FF503 is a 3-clock power supply as shown in FIG.
A carrier reference signal 106 having a loose width is generated. The power
The counter 501 is two clocks earlier than the predetermined count value.
Since it is set to generate a carry signal,
If the center of the pulse width of 3 clocks is a standard signal,
This is the position where the synchronization signal 512 arrives. This carrier standard
The signal 106 is input to the other input of the first AND circuit 507.
And a second AND circuit via the NOT circuit 505
It is the other input of 506. Therefore, the second AND
The carrier reference signal 106 input to the circuit 506 is
It becomes like 11 (f). Therefore, the first and second AND
Ratio composed of circuits 506 and 507 and NOT circuit 505
In the comparator 112, for example, the synchronization reference signal 512 is
When the time arrives as 1 (g), the first AND
The output from the circuit 507 is shown in FIG. 11 (h) and (i).
If the time arrives, the second AND circuit 506
Output from the carrier reference signal 106.
If the sync reference signal 512 is within the pulse width range of
If there is no reference signal, it can be determined as a non-standard signal. Well
Further, according to the comparator 112 of this embodiment, the synchronization reference signal is
The frequency where there is a steady deviation in the arrival position of No. 512
It seems that the non-standard signal with a numerical error or the arrival position is different each time.
Non-standard signals with various jitters can be detected as well. In this embodiment, the counter 501 counts
Generates a carry signal 2 clocks earlier than the specified value
And carry signal is delayed by 2 clocks.
So that the pulse time is equal to the predetermined count value.
Then, the carrier reference signal 106 is determined to be ± 1 clock.
I have a margin. This is the incoming synchronization reference signal 1
11 and the carrier reference signal 106 have a standard signal relationship.
Even if the APC clock 104 and the synchronization reference signal 111 are
Since the phase relationship is not fixed, the synchronization reference signal 111 is set to AP.
Clock of ± 1 clock when processing with C clock 104
This will cause quitter, so to prevent misjudgment due to this
is there. In addition, ± 1 clock is added to the carrier reference signal 106.
Noise in a weak electric field
It is possible to prevent a malfunction due to the influence of the above. This standard
Signal determination margin, that is, the carrier reference signal 10
The pulse width of 6 can be selected appropriately according to the accuracy of the signal processing system.
Wear. The first and second AND circuits 506,
The output of 507 is up / dow which constitutes the integrator 113.
It is supplied to the n counter 508 and becomes a standard signal detection output.
By the output of the first AND circuit 507, up / dow
The n counter 508 counts up by 1 bit and
Signal output by the second AND circuit 506
And count down one bit. This up / down cow
When the count value reaches 2N or 0, the key
Carry signal (count value = 2N) or borrow signal (count value)
= 0) is generated, the count value is initialized to N. this
The carry signal and borrow signal correspond to the first and second A
Whether the output of either ND circuit 506 or 507 is generated
This will occur when the rate becomes high, so
The fruits can be stabilized. Therefore, the generation of this carry signal
Detection by setting RS-FF510 by
The output 114 indicates that the input signal is a standard signal,
Also, the RS-FF510 is reset by the borrow signal.
By doing so, the detection output 114 is a non-standard signal
Indicates that there is. Therefore, according to this embodiment, the standard / non-standard
The quasi-signal can be detected easily and stably. Further, in this embodiment, the integrator 113 is set to u
It is composed of a p / down counter, but this is a bidirectional shift
It is obvious that the register can also be used. Next, the frequency divider 105, the comparator 112, the integration
A second embodiment showing the details of the container 113 will be described with reference to FIG.
I do. Reference numerals 601 and 609 are RS-FFs, 602 and 6
07 is an OR circuit, 603 is an AND circuit, 604 is NOT
Circuit, 605 and 608 are N-stage counters, and 606 is M-stage
The frequency divider 105 is the counter of the counter 501,
Shift register 502, RS-FF 503, 601, NO
T circuits 504, 604, OR circuit 602, AND circuit 6
In 03, the integrator 113 determines the N-stage counters 605, 60.
8, M stage counter 606, OR circuit 607, RS-F
It consists of F609. The comparator 112 is the same as in the previous embodiment.
Is. The basic operation of this embodiment is the same as that of the previous embodiment.
3 clocks from the output of RS-FF503
It is possible to obtain a carrier reference signal 106 with a pulse width of
In the comparator 112, the synchronization reference signal 512 and the
Compare carrier reference signals and use standard / non-standard detection pulses
Occur. This comparator output is given to the integrator 113.
And the RS-FF 60 that constitutes the frequency divider 105
1 set pulse and reset pulse. This R
When the comparator 112 detects a standard signal, the S-FF 601 is
When set, the output logic becomes "1" and the OR circuit 60
Given to 2. Accordingly, the synchronization reference signal 51
2 prohibits the initialization of the counter 501 by
Carry signal in phase with the numerical value, that is, the shift
Initialization is performed by the output of Q1 of register 502.
And the frequency divider is self-propelled, and the comparator 112 is a non-standard
If a signal is detected, the RS-FF 601 is reset.
And performs initialization with the synchronization reference signal 512.
To do. According to this,
If it is determined to be standard at the set cycle, the frequency divider 105
By self-propelled, the comparison cycle at the next comparison point
Is doubled, and if it is determined to be standard even in that cycle, the next
At the comparison point, the comparison cycle is tripled and the comparison cycle can be varied. I
Therefore, according to the present embodiment, the jitter of a specific frequency component is
Of the period set in the frequency divider 105
It is possible to detect all the jitter of frequency components,
The detection accuracy can be improved. For example, the cycle set in the frequency divider 105 is
If the field cycle is 1/60 sec, the comparison cycle is 1
Field, 1 frame, 1.5 frames, 2 frames
It can be changed. Generally, in VTR, cylinder
1 rotation jitter (60Hz), VDP, VHD
One-turn jitter of the star (VDP30Hz, VHD15Hz)
Component is large, and the frequency component is different in each system.
However, in this embodiment, the comparison cycle can be set as described above.
Since it can be changed, judgment at the frequency with the largest jitter is possible.
Easy to perform and more reliable judgment of non-standard signals
Can be done. The output of the comparator 112 is the same as that of the previous embodiment.
Similarly, after being integrated by the integrator 113, the non-standard detection signal 11
It becomes 4. Next, the operation of the integrator 113 in this embodiment will be described.
explain about. The first constituting the comparator 112
The output of the AND circuit 507 of
Of the second counter 606 via the OR circuit 607 and the OR circuit 607.
It becomes a lock input and the output of the second AND circuit 506.
Through the third counter 608 and the OR circuit 607.
Then, it becomes the clock input of the second counter 606. The first and third counters 605 and 608
Both generate a carry signal when counting to N,
The number becomes 0. Also, the second counter 606 is
Generates carry signal when counting up to (N ≦ M <2N)
Then, the count value becomes zero. The first and second AND circuits 5
If the probability of occurrence of either 06 or 507 becomes high,
The first or third counter 605, 608 is
The carry signal is generated before the second counter 606.
Therefore, the integrator 113 also determines the detection result as in the previous embodiment.
Normalization can be achieved and the carry signal of the first counter 605 and the first
The carry signal of the counter 606 of 2 is RS-FF609
As set pulse and reset pulse of
The integrated output of the RS-FF609.
The outgoing signal 114 is obtained. Therefore, according to this embodiment, the jitter
Improved detection accuracy and stable standard / non-standard detection
realizable. In the present embodiment, the integrator 113 has N stages.
Counters 605 and 608 of M and counter 606 of M stages
However, instead of these counters, there are N stages of series.
Configured using a shift register and a shift register of M stages,
Obviously, a similar effect can be obtained. Next, a third embodiment of the integrator 113 will be described.
Will be described with reference to FIG. 1401 and 1402 are OR
Circuit. In this embodiment, the integrator shown in FIG.
The first and third N-stage counters 605 and 608, the second
Any one of the M-stage counters 606 outputs a carry signal.
When output, all counters are initialized and the first N-stage counter is
The carry signal of the unter 605 sets the RS-FF 609.
The second M-stage counter 606 or the third N-stage counter.
The carry signal of the unter 608 drives the RS-FF 609.
Reset. In the integrator according to this embodiment, for example, the ratio
The standard / non-standard judgment results in the comparator 112 are almost equal.
In such cases (in such cases, the probability of non-standard
First, the second M-stage counter 606 carries a carry signal.
The carry signal causes the RS-FF
609 can now be reset to a non-standard signal
The detection sensitivity for the
You. Also in this embodiment, the first, second and second
Counters 605, 606, 608 of 3 are shift registers
May be Next, a fourth embodiment of the integrator 113 will be described.
Is shown in FIG. 1501 is a count value from 0 to 2L
The up / down counter, 1502 is a NOR circuit
is there. In this embodiment, the integration in the third embodiment is performed.
The result is further multiplied by the up / down counter 1501.
After that, it is supplied to the RS-FF609.
Things. According to the present embodiment, the standard / non-standard judgment result is obtained.
Prevent accidental judgment mistakes when the results are almost equal
Therefore, the determination result can be made more stable.
Also in this embodiment, the first, second and third counts
605, 606, 608 are shift registers, up / d
The down counter 1501 is a bidirectional shift register.
However, instead of the up / down counter, N-stage counter
With an integrator consisting of two counters and one M-stage counter
There may be. The frequency divider 105 and the integrator 1 described above
13 and the embodiment of the synchronization reference generator 110, etc.
May be arbitrary, but there is no problem. Regarding the non-standard signal detecting means NT
Although the SC method has been described as an example, the detection means of the present invention
If it is not limited to the NTSC system, it can be adjusted horizontally with the color subcarrier frequency.
And the vertical scanning frequency has a specific relationship
Obviously, it is applicable to any vision signal. Next, in the signal processing system by the detection circuit of the present invention,
An embodiment of the control means will be described with reference to FIG. Reference numerals 701 and 705 denote delay lines, and 702 and 72.
0,721 is an A / D converter, 717 is a bandpass filter
718 is an ACC (Auto Color Control) circuit,
719 is a color demodulation circuit, 703 is a motion detection circuit, and 706 is
Luminance separation frame comb filter, 707 is luminance separation
Line comb filter, 716 is a low-pass filter,
708, 712, 726 are mixers, 709, 728, 7
42 is a switch circuit, and 710 is a field interpolation fill.
711, 732, 733 are line interpolation filters, 7
13, 736, 737 are double speed conversion circuits, 714, 73
8, 739 is a D / A converter, 723 is a multiplexer,
724 is a color separation frame comb filter, and 725 is a color
Separation line comb filter, 729 is demultiplexing
It is sa. A television receiver input from the input terminal 101
Of the delay line 701 and the bandpass filter 717.
It becomes an input. Television signal passed through delay line 701
Is converted into a digital signal by the A / D converter 702 and converted into a digital signal.
Lame comb filter 706, line comb filter 7
07, input to the low pass filter 716,
The rhombus filter 706 is used for the luminance component by inter-frame processing.
In the line comb filter 707, the inter-line processing is
And each output is provided to mixer 708. Mixed
The combiner 708 calculates the motion amount detected by the motion detection circuit 703.
Accordingly, the output signal of the frame comb filter 706
To control the mixing ratio of the output signals of the line comb filter 707.
Control, and extract the luminance signal. This brightness signal is switched
Field interpolation filter 710 via path 709 and
Of the line interpolation filter 711 and the double speed conversion circuit 713.
It becomes an input. The outputs of these two interpolation filters are the mixer 7
12 is input to the control unit 12 and output from the motion detection circuit 703.
The mixing ratio is controlled by the control signal 704, and the interpolation signal 7
44 is made. The double speed conversion circuit 713 has the same phase in parallel.
When the current signal 743 and interpolation signal 744 input by
It is compressed for a while to obtain a time-sequential progressive scanning signal. On the other hand, it is input to the bandpass filter 717.
The television signal is a band in which the color signal is multiplexed.
Signal of the color is transmitted through the ACC circuit 718.
Color demodulation is performed on the path 719, and the demodulated color difference signal RY,
BY is applied to A / D converters 720 and 721, respectively.
Converted to digital signal. Digitally converted color
The difference signals R-Y and B-Y are sent to the pixel unit by the multiplexer 723.
Time-division-multiplexed with a frame comb filter 724
It is applied to the line comb filter 725, and the
Luminance component removal by logic and luminance component removal by line-to-line processing
The other processing is performed, and the control signal 70 is output from the mixer 726.
In 4, the mixing ratio is controlled and the color signal is extracted. This extraction
The generated color signal is demultiplied through the switch circuit 728.
Color difference signals RY and B-time-division multiplexed by the lexer 729
Y is separated, and the line interpolation filters 732 and 735 are used respectively.
Interpolation signals 732 and 734 are generated, and the double speed conversion circuit 73
6 and 737 are processed in the same way as the luminance signal, and double-density sequential running
It becomes an inspection signal. The above processing is conventionally applied to a standard signal.
Processing, which is not suitable for non-standard signals
As already mentioned. Therefore, the non-standard signal of the present invention
If a non-standard signal is detected in the detection circuit,
The output signal 114 causes the switch circuit 709 to pass the low pass signal.
Switch output of filter 716 to interpolation filter
Circuit 728 demultiplexes the output of multiplexer 723.
Control to supply to Lexa 729, so-called frequency
Change to Y / C separation by separation. At the same time,
It also controls the switch circuit 742. This switch circuit
742 is a clock supplied from the AFC circuit (hereinafter,
Called AFC clock) 262, and APC clock 10
4 and the input, the output is the A / D converter of the signal processing system
System of digital processing circuit from D to A converter
It is given to the signal processing system as a clock. At this time, A
Frequency of FC clock 262 and APC clock 104
Selects the same frequency. Then, the non-standard detection signal 11
According to 4, AP with high frequency stability in the case of standard signal
AFC clock when C clock 104 is a non-standard signal
262 is controlled to be supplied as a system clock.
You. Frame delay generally used for frame combs
The extended line is composed of a memory of the number of pixels for one frame.
You. For example, the sampling frequency of A / D conversion is set to the color subcarrier frequency.
Wave number In case of quasi-signal, APC clock, AFC clock
Screen position between the input and output of the frame delay line even if there is a shift
, The color subcarriers have the opposite phase relationship.
However, in case of non-standard signal
When the memory is driven, the relationship in which the phase of the color subcarrier is reversed is maintained.
However, the screen position between the input and output of the frame delay line is shifted.
As a result, the motion cannot be detected. Also, AFC clock
When operating with a lock, reverse the procedure to enter the complaint delay line.
The screen positions between the outputs match, but the phase of the color subcarrier is reversed
Since the relationship of phase is not established, the processing of frame comb shape
Can not. From the above, according to this embodiment, the input
When the signal is a non-standard signal, the non-standard detection signal 114
By using the AFC clock as the system clock, movement
It is possible to prevent malfunction of the detection circuit,
Can be realized. Next, a signal processing system using the detection circuit of the present invention
A second embodiment of the control means will be described with reference to FIG. 801 is a line comb filter, 802
803 is a switch circuit. If the input signal is a standard signal, the switch
Switch circuits 802 and 803 select the input terminal 101 side respectively
However, the switch circuits 709 and 728 are respectively connected to the mixer 7
08, 726 output side is selected, the switch circuit 742
Non-standard detection signal to select APC clock 104
114 to control the same signal processing as in the previous embodiment.
To do. If the input is a non-standard signal,
The non-standard detection signal 114 causes the switch circuit 802 to
Luminance signal separated by line comb filter 801
The switch circuit 803 causes the line comb filter 801
Switch circuit 709 A / D the color signals separated by
The switch output 728 outputs the converter output to the multiplexer.
Switch circuit 742 selects AFC clock 262.
Control to select. According to this embodiment,
Similarly, motion adaptive scanning line interpolation can be realized and
In / comb filter 801 allows Y / C separation
Therefore, cross color and dot interference can be reduced. What
This line comb filter 801 is an analog circuit.
A digital clock that is always driven by the APC clock
It may be configured with a circuit. Next, a signal processing system using the detection circuit of the present invention
A third embodiment of the control means will be described with reference to FIG. Reference numeral 901 is an A / D converter, and 902 is a bandpass converter.
Filter, 903 ACC circuit, 904 color demodulation circuit
Is. In this embodiment, the system clock is always APC.
It is a clock. The non-standard detection signal 114 is a motion detection signal.
The path 703 is controlled, and in the case of a standard signal, a motion detection circuit
Depending on the detection result of 703, the mixers 708, 712, 72
6 to control motion detection in the case of non-standard signals.
Regardless of the detection result of the output circuit 703, the
For processing in the time direction such as comb and field interpolation
The mixing ratio to 0, line comb, line interpolation, etc.
The mixing ratio for processing in space is set to 1. Therefore, in this embodiment, the processing in the time direction is performed.
The interference due to
Since the APC clock can be used for
Filter 902, ACC circuit 903, color demodulation circuit 90
4 can be digitally processed, and the entire signal processing
It can be digitalized. Next, the signal processing system using the detection circuit of the present invention will be described.
A fourth embodiment of the control means will be described with reference to FIG. 1001 is an A / D converter, and 1002 is a motion.
A detection circuit, 1003 is a frame comb filter, 100
4 is a line comb filter, 1006 and 1007 are mixed
Device, 1008 is an ACC circuit, 1009 is a color demodulation circuit, 1
Reference numeral 010 is a delay line. In this embodiment, the motion suitability in the previous embodiment is adjusted.
It has a configuration with one Y / C separation circuit.
The muc clock is always the APC clock and the non-standard detection signal 1
14 controls the motion detection circuit 1002. Frame comb
The filter 1003 shares a frame delay line, for example.
Separates the luminance signal from the sum between frames and the color signal from the difference
The line comb filter 1004 has a line delay line
Commonly used, for example, sum of lines to luminance signal, difference to color signal
Separate the issues. Separated luminance and color signals are mixed
Output from the motion detection circuit 1002 by the devices 1006 and 1007
Mixed at a mixing ratio determined by the control signal 1005
Will be output. Luminance signal separated in this way
Is the same as the previous embodiment.
That is, the color signal is sent to the color demodulation circuit via the ACC circuit 1008.
After color demodulation on path 1009, the space is restored as in the previous embodiment.
Scanning line interpolation processing is performed. The non-standard detection signal 114 is the same as in the previous embodiment.
Since the motion detection circuit 1002 is controlled like this,
Even in the case of time, interference in the time direction can be suppressed, and the entire signal processing system can be suppressed.
Digitization is possible. Further, in this embodiment, non-standard signal input
Switching to AFC clock at the time, motion adaptive processing of scanning line interpolation
To achieve, Y / C separation by frequency separation, for example,
For example, low pass filter for luminance signal, band pass filter
With a circuit to extract the color signal with
What can be done by switching is from the previous embodiment.
It can be easily analogized. [0064] According to the present invention, the color subcarrier frequency and water
A non-standard object that does not have a predetermined relationship with the flat and vertical scanning frequencies.
Quasi signals can be detected easily and correctly
Thus, optimal signal processing can be performed on non-standard signals.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing an embodiment of a synchronization reference signal generating means of the present invention. FIG. 3 is a block diagram showing an embodiment of a synchronization reference signal generating means of the present invention. FIG. 4 is a block diagram showing an embodiment of a synchronization reference signal generating means of the present invention. FIG. 5 is a block diagram showing an example of a detailed configuration of the present invention. FIG. 6 is a block diagram showing an example of a detailed configuration of the present invention. FIG. 7 is a block diagram showing an embodiment of the control means of the signal processing system by the nonstandard signal detection means of the present invention. FIG. 8 is a block diagram showing an embodiment of the control means of the signal processing system by the non-standard signal detection means of the present invention. FIG. 9 is a block diagram showing an embodiment of the control means of the signal processing system by the non-standard signal detection means of the present invention. FIG. 10 is a block diagram showing an embodiment of the control means of the signal processing system by the non-standard signal detection means of the present invention. FIG. 11 is a waveform chart showing an example of the operation of each unit of the present invention. FIG. 12 is a waveform chart showing an example of the operation of each unit of the present invention. FIG. 13 is a waveform diagram showing an example of the operation of each unit of the present invention. FIG. 14 is a circuit diagram of an integrating circuit. FIG. 15 is a circuit diagram of an integrating circuit. [Description of Reference Signs] 103 ... APC circuit, 105 ... Frequency divider, 107 ... Sync separation circuit, 110 ... Sync reference generator, 112 ... Comparator, 113 ... Integrator.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshinori Murata               292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Ceremony Company Home Appliance Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuo Nakagawa               292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Ceremony Company Home Appliance Research Laboratory, Hitachi, Ltd. (72) Inventor Akiha, Yasuhiko               1-280, Higashikoigakubo, Kokubunji, Tokyo               Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuo Ishikura               1-280, Higashikoigakubo, Kokubunji, Tokyo               Central Research Laboratory, Hitachi, Ltd.                (56) Reference JP-A-61-184082 (JP, A)                 JP 57-161558 (JP, A)

Claims (1)

(57) [Claims] 1. Means for separating a synchronizing signal from television signal input, a pulse generating means for generating a pulse of an integral multiple of the period of the vertical scanning period from the synchronization signal, the color burst signal of the television signal frequency f
means for generating a clock having a frequency of m times sc, and dividing the clock having a frequency of m times the frequency fsc of the color burst signal by an integer multiple of (455 × m) / 2,
Vertical scanning period equal to the pulse output by the pulse generator
A frequency dividing means for generating a pulse of an integral multiple of the period of a comparing means for periodically and the dividing unit of pulses the pulse generating means outputs to compare the period of the output pulse, said comparator means output And a non-standard signal judging means for judging whether the television signal is a standard signal or a non-standard signal.