JP2557405B2 - Oscillator circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an oscillator circuit.

[Conventional technology]

Conventionally, a plurality of logic inversion circuits such as an inverter, a NAND gate and a NOR gate are used, and a high level value H and a low level value L are used.
There is a simple oscillation circuit that utilizes a parasitic oscillating voltage generated in the circuit when switching the circuit that outputs the binary value.

FIG. 5 is a block diagram of an example of a conventional oscillation circuit, and FIGS. 6 (a) and 6 (b) are voltage waveform diagrams of respective parts for explaining the operation of the circuit of FIG.

The first inverter 1, the capacitor C, and the second inverter 12 constitute a closed circuit in series, and the resistor R is connected in parallel between the input and output ends of the second inverter 12.

If a 5V as a circuit supply voltage V _DD, a first logic threshold voltage V _T1 of the inverter 1 difference is small between the logic threshold voltage V _T2 of the second inverter 12, for example in the case of less than 10mV , Parasitic oscillating voltage of 50 mV is generated at the time of switching current of about 10 mA due to the parasitic inductance of the power source such as wiring reactance of the printed circuit board connected to the circuit, and it is superimposed on the input voltage v ₂ of the input terminal of the second inverter 2. Since the threshold voltage V _T2 is inevitably exceeded, a stable rectangular wave output voltage v ₀ is obtained at the output end T ₀ .

The oscillation time constant (τ ₁ + τ ₂ ) is determined by the time constant of the value r of the resistor R and the capacitance c of the capacitor C.

The oscillating frequency of the circuit can be obtained from the equation (1).

= 1 / (τ ₁ + τ ₂ ) ≈1 / (2.2 × c · r) (1) The logical threshold voltages V _T1 and V _T2 are 1.0 to 3.5 V when the power supply voltage V _DD is 5 V. However, the difference between two threshold voltages in the same IC is generally about 10 mV.

[Problems to be solved by the invention]

FIGS. 7 (a) to 7 (c) are voltage waveform diagrams of respective parts for explaining the problems of the circuit of FIG.

As shown in FIG. 7 (b), the parasitic oscillation voltage v _n is superimposed on the input voltage v ₂ during switching, but the threshold voltage V _T2 of the second inverter is the threshold voltage of the first inverter. When it is larger than the value voltage V _T1, the peak value at the time of falling of the input voltage v ₁ does not reach the threshold voltage V _T1 and the oscillation stops.

FIG. 7 (c) shows the waveform of the output voltage v ₀ .

The above-described conventional oscillation circuit has an operating principle that the threshold voltage difference between the two logic inversion circuits is small, for example, 10 mV or less, and the circuit parasitic oscillation voltage during switching is large, 10 mV or more. There is a problem that the oscillation operation is unstable due to uncertain factors such as parasitic vibration.

An object of the present invention is to provide a stable oscillation circuit that does not depend on an unstable circuit parasitic oscillation voltage as an operating principle.

[Means for solving problems]

The oscillator circuit of the present invention constitutes a closed circuit in series including a first logic inverting circuit, a capacitor and a second logic inverting circuit, and has a resistor in parallel between the input and output terminals of the second logic inverting circuit. , The threshold voltage V _{T1 of} one of the two logic inverting circuits and the logic threshold voltage at the time of rising of the input voltage of the input terminal of the other logic inverting circuit.
The relationship between V _T2 and the logic threshold voltage V _T2D when the input voltage falls is configured to satisfy V _T2D > V _T1 > V _T2R .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of an embodiment of the present invention.

The oscillator circuit is the same as the conventional oscillator circuit except that the circuit function of the second inverter 2 is different from that of the second inverter 12 shown in FIG.

FIG. 2 is a characteristic diagram showing the relationship of each logic threshold voltage of each inverter for explaining the operation of the circuit of FIG.

Logic threshold voltage V _T1 at the input terminal of the first inverter 1
And the logical threshold voltage V _T2R when the input voltage _rises at the input terminal of the second inverter 2 and the logical threshold voltage V _T2D when the input voltage falls, as shown in the equation (2). Have a relationship.

V _T2D > V _T1 > V _T2R (2) FIGS. 3 (a) and 3 (b) are voltage waveform diagrams of various parts for explaining the operation of the circuit of FIG. As shown in FIG. 3 (a), the input voltage v ₂ of the second inverter becomes equal to V _T2D at the time point t ₂ at the time of the fall, and is inverted, and then becomes equal to V _T2R at the time point t ₃ at the time of the rise. And then flip.

In either case, the falling and rising waveforms are the threshold voltage V
_Since it is surely inverted before reaching _T1 , it is possible to obtain a stable rectangular wave output voltage v ₀ of the high level value H and the low level value L at the output terminal T ₀ .

FIG. 4 is a detailed circuit diagram of the second inverter 2 of FIG.

The second inverter 2 has an input terminal connected to the input terminal T ₁₂ , an output terminal connected to the input terminal of another inverter 4, and an inverter 3 _R having a logical threshold voltage V _T2R , and an input terminal connected to the input terminal. An inverter 3 _D connected to the terminal T _I2 and having a logical threshold voltage V _T2D ; an AND circuit for inputting the two signals of the output signal v _{R of the} inverter 4 and the output signal V _D of the inverter 3 _D ; FF circuit 5 of two NAND circuits 5 _a and 5 _b , and AND circuit signals v _a and F
It is composed of an exclusive OR circuit EX-OR which inputs the F signal v ₅ and supplies the signal voltage v ₁ to the output terminal T _I1 .

The circuit function operates as a second inverter having a rising logic threshold voltage V _T2R and a falling logic threshold voltage V _T2D .

An example of the numerical value (volt) of the formula (2) when the power supply voltage V _DD is 5V is shown in the formula (3).

V _T2D = 2.7> V _T1 = 2.5> V _T2R = 2.3 (3) In the above-mentioned embodiment, the two logical threshold voltages V _T2R and V _{T2D for} the second inverter when rising and falling. However, even if the logical threshold voltage of the second inverter is set to V _T1 and the two logical threshold voltages V _T2R and V _T2D are set to the first inverter, the circuit output voltage waveform v ₀ The circuit operation is exactly the same except that the high and low levels are inverted.

〔The invention's effect〕

As described above, the present invention has an effect that a stable oscillation circuit can be obtained by satisfying the expression (2) between the logical threshold voltages of the two logical inversion circuits.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3A and FIG. 3B are characteristic diagrams showing the relationship between the logical threshold voltages of the respective inverters for explaining the operation of the circuit shown in FIG. 3, and FIGS. 3A and 3B are parts for explaining the operation of the circuit of FIG. Voltage waveform diagram of FIG. 4, FIG. 4 is a detailed circuit diagram of the second inverter of FIG. 1, FIG. 5 is a block diagram of an example of a conventional oscillator circuit,
FIGS. 6 (a) and 6 (b) are voltage waveform diagrams of respective parts for explaining the operation of the circuit of FIG. 5, and FIGS. 7 (a) to 7 (c) are explanations of problems of the circuit of FIG. FIG. 3 is a voltage waveform diagram of each part for doing so. 1 ... 1st inverter, 2 ... 2nd inverter, _3D
...... Falling inverter, 3 _R …… Rising inverter, C…
… Capacitor, R… Resistor, V _T1 …… Threshold voltage of the first inverter, V _T2D …… Threshold voltage of the second inverter when _falling , V _T2R …… _{Rise of} the second inverter Hour threshold voltage.

Claims (1)

(57) [Claims] 1. A closed circuit is formed by including a first logic inverting circuit, a second logic inverting circuit and a capacitor in series, and a resistor is connected between the input and output ends of the second logic inverting circuit. in the oscillation circuit comprising Te, when the logical threshold voltage V _T2R and the input voltage standing under the time of input riser of one logic threshold V _T1 and the other logic inversion circuits of said first and second logic inversion circuit The oscillator circuit is characterized in that the relationship with the logic threshold voltage V _T2D of the above satisfies V _T2D > V _T1 > V _T2R .