JP2556495B2 - Code processor - Google Patents

Description

The present invention relates to the field of error correction, and also relates to a technique for performing parallel processing in signal processing with a symmetrical communication path.

The present invention relates to a method for performing syndrome generation, GCD (greatest common divisor) generation, error correction and erasure error correction in BCH code encoding and decoding.

 In particular, it relates to a method for performing the following operations.

1) y = r _n-1 · x ^n-1 + r _n-2 · x ^n-2 ＋ …… ＋ r ₁ · x + r ₀ 2) y = GCD (A, B) where y is the maximum of polynomials A and B Promise polynomial 3) y = A · B where A = a _n · x ⁿ + a _n-1 · x ^n-1 + a ₁ · x + a ₀ B = b _n · x ⁿ + b _n-1 · x ^n-1 + b ₁ X + b ₀ 4) y = A mod B [Prior art and its problems] In recent years, as a measure for improving the reliability of various digital systems such as memory systems, error detection / error correction codes (hereinafter simply referred to as error correction codes) Application) is spreading.

There are various kinds of error correction codes according to the target system, but the most typical one is one class of linear codes called cyclic codes. This includes a BCH code suitable for random error correction, a fire code suitable for burst error correction, and a Reed-Solomon code (hereinafter, RS code), which is one type of BCH code and suitable for byte error correction. Be done. Among them, the RS code is a practically very important code that has the feature that the redundancy can be the lowest among the linear codes that have the same code length and correction capability, and is a sanitary communication, magnetic disk, compact. It is widely used for discs (hereinafter called CDs).

There are various decoding methods for this RS code, and there are 2 to 3
It is relatively easy to implement a decoder for a small correction capability. However, in order to obtain high reliability, it is necessary to increase the correction capability. In that case, there arises a problem that the scale and control of the apparatus become very complicated, and the calculation time required for the decoding process becomes long. Therefore, the current CD is CI
A type of double coding called RC is used, but there is a problem in a system that requires higher reliability or higher speed. In order to obtain high reliability, a multi-error correction code called Long Distance Code (LDC) has been proposed for magneto-optical disks and the like, but realization of high speed is a problem. In satellite communication, high reliability and high speed are required, but it has been extremely difficult to satisfy the above two conditions when considering deviceization.

Therefore, the “BCH encoding / decoding method” (filed on December 22, 1986), which the applicant of the present invention filed earlier, realized the following by taking advantage of the characteristics of the VLSI architecture.

1) High reliability (high capacity) 2) High speed 3) Regularity of internal structure 4) Large integration This makes it possible to realize an RS encoder / decoder having a processing speed of 10-20 Mwps = 80-160 Mbps or more. showed that.
Also, by increasing the PEs of the same configuration with respect to the correction capability in a linear function, it is possible to obtain arbitrary high reliability. This is very effective for systems requiring high reliability and high speed such as sanitary communication. Further, since the process of obtaining the error locator polynomial and the error value polynomial, which is the center of the decoding process, can be performed at 10-20 Mlps (codelength / sec), this is a very effective method for high-speed processing.

However, the transfer rate of data used in CDs or magnetic disks is often 10 Mbps or less, and there is a demand for miniaturization of hardware capacity, which is still a problem.

[Means for solving problems]

In view of the above points, the present invention provides the high speed condition of 2) while making the best use of the characteristics of the architecture of the RS coding / decoding system shown in the above “BCH coding / decoding system” filed by the applicant. We propose an architecture that can achieve the condition 4) by miniaturization by sacrificing it.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

The RS coding / decoding architecture described above is based on the concept of the systolic architecture.
A feature of the Cystoarchitecture is that one process is processed by the same network of the same PE. This is all processing elements (P
The processing performed in E) is the same, and the input / output relationship is the same. Therefore, one process
After performing at PE, the processing result is not sent to the next PE but is stored in the memory (register) part and is fed back to itself, so that processing can be performed without increasing the number of PEs. Therefore, the basic PE this time is set as shown in Fig. 1. In FIG. 1, 1-4 are the same as in FIG. 36,
The registers 5-7 are m-stage register trains or memory units. Considering GF (2 ⁸ ), the circuit scale of 1 selector is about 50 gates and the multiplier of 2 and 3 is 3rd.
In the configuration shown in FIG. 8, one is about 300 gates, four adders are about 50 gates in the configuration shown in FIG. 39, and one register of 5-7 is about 50 gates.

In addition, when paying attention to one PE, in the previous architecture, after processing once and outputting the processing result, that PE can receive the next input, so high-speed processing that maximizes the processing speed of 1PE is possible. It is possible, but the processing result is
If you feed back to yourself without sending it to the
The data transfer rate to PE is slow. However, the processing speed of the PE itself is 10-20 Mhz because it is determined by the processing unit of the PE consisting of 1-4 and its configuration does not change. Here, the processing speed of 1PE is 16 Mhz for convenience of later.

In the following, the processing of steps 1-4 is realized by using this PE as a basic model, but unnecessary parts are removed in each processing for the purpose of downsizing, and the PE is optimized in each processing.

Principle of RS code First, the principle of RS code will be described. The RS code is a practically very important code that has the characteristic that the redundancy can be the lowest among the linear codes that have the same code length and correction capability.

The RS code is a non-binary BCH code (Bose-Chavdhuri-Hocque
nghen code), which is a special case of finite field (hereinafter abbreviated as GF) GE (q). Where q is GF
It is the original number of (q). Using this q, various parameters that characterize the RS code are defined as follows.

・ Code length: n (number of symbols in one code) n ≦ q-1 (2-1) ・ Information symbol property: k (number of information symbols in one code) ・ Number of check symbols: n−k (in one code) No. of check symbols) n−k = dmin−1 (2-2) Correction capability: t (number of symbos that can be corrected in one code) ([X] Gaussian symbol .. The maximum integer that does not exceed x.) Here, dmin is called the minimum distance (Hamming distance).

Encoding Here, a polynomial expression of a code word or the like will be described.

For example, when the number of k information symbols to be encoded is I = (i ₀ , i ₁ , ..., I _k-1 ) (2-10), this is expressed by a polynomial as follows.

I (x) = i ₀ + i ₁ x + i ₁ x ² + ... + i _k-2 x ^k-2 + i _k-1 x
^k−1 (2-11) (n−k) check symbols C = (c ₀ , c ₁ , ..., C _nk−1 ) (2-12) similarly added are C (x) = c ₀ + c ₁ x + c ₂ x ² + ... c _nk-1 · x ^nk-1 (2-1
3) Further, a code word F F = (f ₀ , f ₁ , f ₂ , ..., f _n-1 ) (2-14) = (c ₀ , c ₁ ... c _nk-1 , i ₀ , i ₁ , i ₂ , ... i _k-1 ) (2-15) is F (x) = f ₀ + f ₁ x + f ₂ x ² + ... f _n-2 x ^n-2 + f _n-1 x ^n-1 (2
−16) is expressed as a polynomial.

By the way, the code word polynomial F (x) can be divided by the generator polynomial G (x) that generated it. However, (2
The generator polynomial of the −17) formula (see the next page) is α, α ² , ... α
^Since the code word polynomial F (x) has a root of ^nk , the following expression holds when this root is substituted.

F (α ⁱ ) = 0 (i = 1,2, ..., n−k) (2-21) When this (2-21) expression is expressed in matrix, it becomes as follows (F ^T is the transposed matrix of F ).

Here, the matrix H on the left side is called a check matrix and has an important meaning in decoding.

Decoding Method Since the RS code is a kind of BCH code as described above, decoding can be performed using a general BCH code decoding algorithm. However, in that case, handling of symbols such as addition and multiplication in the decoding process must be performed on the finite field GF (q) in which the RS code is defined.

Code length n = 2 ^m − defined on GF (2 ^m ) (m: positive integer)
Considering the RS code of 1, the symbol is represented by an m-bit binary number, and the operation is performed on GF (2 ^m ). The equation (2-17) is used for the generator polynomial, and the minimum distance of the code is set as dmin = 2t + 1 for simplicity.

g (x) = (x−α) (x−α ² ) ... (x−α ^nk ).
(2-17) However, α is a primitive element on the finite field GF (2 ^m ).
Similar to the case of the code, it is divided into the following four steps.

Step 1) Syndrome calculation.

Step 2) Calculation of error locator polynomial and error evaluation polynomial.

Step 3) Estimate error position and error value.

Step 4) Perform error correction.

Step 1) Syndrome calculation First, the transmitted code word is F: F = (f ₀ , f ₁ , ... f _n-1 ) and the error caused is E: E = (e ₀ , e ₁ , ... e _n-1 ) If the received word received is R: R = (r ₀ , r ₁ , ... r _n-1 ) = F + E = (f ₀ + e ₀ , f ₁ + e ₁ , ... f _n-1 + e _n-1 ) , The polynomial expression R (x) of the received word is as follows.

R (x) = F (x ) + E (x) = (f 0 + e 0) + (f 1 + e 1) x + ... · + (f n-1 + e n-1) x n-1 (2-23) However, the generator polynomial G (x) is added to the code polynomial F (x).
(F (α ¹ ) = 0) holds when the root α ⁱ (i = 1, ..., n−k) of (Equation (2-17)) is substituted, so that the received word polynomial R (x) is also obtained. Substituting α ⁱ (i = 1, ..., N−k), R (α ⁱ ) = F (α ⁱ ) + E (α ⁱ ) = 0 + E (α ⁱ ) = E (α ⁱ ) (2-24) Then, a value determined only by the error E is obtained.

This is called a syndrome, and S = (s ₀ , s ₁ , ..., s _nk-1 ) (2-25) siR (α ^{i + 1} ) = E (α ^{i + 1} ) (i = 0,1, …, _Nk-1 ) (2
−26). This syndrome contains all information about the error (error location and magnitude).

(Since the syndrome is 0 if there is no error, the presence or absence of the error can be detected.) Syndrome ((2-25), (2
The matrix expression of −26) is as follows.

S = H ・^RT ( ^RT : transpose of R) (2-28) Step 2) Calculation of error locator polynomial and error evaluator polynomial In step 2, an error locator polynomial and an error evaluator polynomial are calculated using the syndrome of the calculation result of step 1. First, here, the number of non-zero elements of the error E = (e ₀ , e ₁ ... E _n-1 ), that is, the number of errors is set as l (l ≦ t).
In addition, the position where the error occurs is ju (u = 1,2 ... l) (ju
= 0, 1 ... N-1), and the error at the position ju is e _ju . Further, the expressions (2-2) and (2-3) are set as nk = dmin-1 = 2t (2-30). Then, the syndrome and the syndrome polynomial of the expression (2-26) are expressed as follows.

Also newly Then, the following equation is obtained.

S (x) = [S _∞ (x)] mod x ^2t (2-35) Now, the error locator polynomial σ (x) is defined as follows. This polynomial is the error position ju (u = 1, 1 in the received word
GF (2 ^m ) corresponding to 2, ……, l) (ju = 0,1 …… n-1)
It is a polynomial whose root is the ^element α ^-ju of.

Next, the error evaluation polynomial ω (x) is defined as follows for σ (x) and S _∞ (x) described above.

Then, from the equations (2-34), (2-35), and (2-37), the following equation is established.

σ (x) · S (x) = [ω (x)] modx ^2t (2-38) Therefore, using an appropriate polynomial A (x), σ (x), S
The relationship between (x) and ω (x) is expressed as follows.

A (x) ・ x ^2t + σ (x) ・ S (x) = ω (x) (2-3
9) By the way, since the number l of errors is (l ≦ t), ω (x) and σ (x) satisfy degω (x) <degσ (x) ≦ t (2-40). Furthermore, since ω (x) and σ (x) are relatively prime (GCD polynomial is a constant) (2-39),
Ω (x) and σ (x) satisfying the equation (2-40) are uniquely determined except for the difference in constant coefficient. From the above, ω (x) and σ
(X) can be obtained in the process of Euclid's mutual division method for obtaining the greatest common divisor (GCD) polynomial of x ^2t and S (x). Here, we briefly describe the method for calculating the GCD polynomial using the Euclidean algorithm. First, the greatest common divisor polynomial of two polynomials A and B will be expressed as GCD [A, B]. Also, the following polynomials for A and B: ・ When degA ≧ dagB = A- [A ・ B ^-1 ] ・ B (2-41) = B (2-42) ・ degA ≧ dagB = A (2-43) = B- [B · A ⁻¹ ] · A (2-44) ([X · Y ⁻¹ ]: quotient obtained by dividing polynomial X by polynomial Y), GCD [A -B] and GCD [,] satisfy the following equation.

GCD [A, B] = GCD [,] (2-45) Therefore, the above and are replaced by A and B, and (2-41) and (2) according to the magnitude relation of the respective degrees degA and degB. −4
2) or the conversion of (2-43) and (2-44) is repeatedly executed, and when either A or B becomes a zero polynomial, the other non-zero polynomial becomes A or B. Obtained as the greatest common polynomial of. Note that obtaining the greatest common divisor polynomial of the polynomials A and B is no different from obtaining the following polynomials C and D. Note that deg is the order.

GCD [A, B] = C • A + D • B (2-46) Then, the above repeating step is executed and the order is i
In the process of finding the greatest common divisor polynomial of polynomials A and B expressed as = degA ≧ degB, polynomials C, D, W satisfying the following equations can be found.

The problem of finding such a polynomial is called the extended GCD problem.
Therefore, the error locator polynomial σ (x) and the error evaluation polynomial ω
(X) is obtained by solving the extended GCD problem when the polynomial A is x ^2t and the polynomial B is S (x) in the equation (2-47).

Basic Algorithm First, as described above, the derivation algorithm of σ (x) and ω (x) can be reduced to the extended GCD problem. That is, x ^2t is a polynomial A ₀ , and a syndrome polynomial S (x) ((2-32)
(Equation) as polynomial B ₀ (degA ₀ = 2t, degB ₀ = 2t−
1), in the process of obtaining GCD [A ₀ , B ₀ ] If polynomials D and W satisfying are obtained, D is an error locator polynomial σ
(X) and W represent the error evaluation polynomial ω (x), respectively. It is known that such σ (x) and ω (x) are uniquely determined except for the difference in constant coefficient. Therefore, A ₀
And B ₀ define the polynomials A, B, U, V, L, M as The initial value is U = M = 1; L = V = 0; (A = A ₀ , B = B ₀ )
Repeated steps shown in the figure are executed and degA (degB) <t
Then A (B) is ω (x) and L (M) is σ (x).
Each is obtained as.

In the method of FIG. 40, the highest-order coefficient α of the polynomial B and the highest-order coefficient β of the polynomial A are multiplied by A and B, respectively, so that division on GF in the iterative step is omitted. (Refer to formulas (2-41) and (2-43)) Even if it does in this way, an essential problem does not arise in the value of (sigma) (x) and (omega) (x).

40 will be described. First, in step 1, U = M = 1, L = V = 0, A = A ₀ , B = B _0, and initial values are set. In step 2, degA degB is judged,
In step 3, the highest coefficients β and α of the polynomials A and B are multiplied by A and B, respectively, to obtain equations (2-41) and (2-4
The division on GF in the repeating step of 3) is omitted.

When degA and degB are smaller than the predetermined orders in step 4, the process proceeds to steps 5 and 6, where ω (x) = A, σ
Calculate (x) = L, ω (x) = B, σ (x) = M.

In order to execute the repetitive step shown in FIG. 40, three execution modes corresponding to the orders of A and B are required, and they will be called as follows.

i) degA, degB ≧ t and degA ≧ degB… “reduceA” ii) degA, degB ≧ t and degA ≧ degB… “reduceB” iii) degA <t or degB <t… “nop” step 3) Error position and error In step 3, the error position and the error value are estimated from the error locator polynomial σ (x) and the error evaluator polynomial ω (x) obtained in step 2. First, the received word R = (r ₀ , r ₁ , ... r _ni )
GF according to the position i = 0,1 ... n-1 of the inside symbol
The element α ^-i of (2 ^m ) is successively substituted into the error locator polynomial σ (x). At this time, if σ (a ⁻ⁱ ) = 0 holds from the equation (2-36), i is α ⁻ⁱ = α ⁻ⁱ = α ^{−ju with respect} to the error position ju.
You can see that is established. (Ju = 0,1 ... n-1, u = 1,2
, 1, 1 ≤ t) Further, the value of the error evaluation polynomial ω (x) for such α ^-i = α ^-ju is as follows.

Furthermore, if σ ′ (x) is the derivative of σ (x), Is established. Therefore, from the equations (2-48) and (2-49), the error position e _{ju at the} error position ju can be obtained from the following equation.

As described above, in the decoding step 3), the error locator polynomial σ (x), the error evaluation polynomial ω (x), and the derivative σ ′ (x) of σ (x) obtained in step 2) are referred to as 3 ′.
Element α of GF (2 ^m ) whose RS code is defined in two polynomials
^It is necessary to successively substitute ^-j (j = n-1, ... 2,1,0) to obtain its value. (Here, the received symbols are input from the higher order terms of the received word polynomial. That is, rj is j = n.
It is assumed that the input is -1, ..., 2,1,0 in that order. Therefore, in the explanation of step 3), α ^-j (j = n−1, ..., 2,1,
It should be noted that the order of assignment of (0) is reversed. ) Here, the calculation specifically required is to simply substitute a variable in a polynomial and obtain its value, so the same algorithm as in Fig. 40 can be used. For example, a polynomial f of degree t
The calculation of (x) is developed as follows.

^{f (x) = ftx t +} ft-1x t-1 + ... + f 1 x + f 0 = {... [(ftx + ft-1) x + ft-2 ] _{x + ... + f 1} x} + f 0 where to assign each cell in syndrome calculation Have a power x in advance.

Step 4) Execution of error correction From the expression (2-9), the received symbol r _{ju at the} position ju in which an error has occurred is as follows from the error size e _ju with the symbol f _ju of the original codeword. Represented.

f _ju = r _ju −e _ju (2-51) Therefore, in step 4, the execution result σ (α
^-i ) = 0 at the position i (i = 0,1, ... n-1) where the received symbol r _i By subtracting (on GF (2 ^m )) f _i = r _i = e _i (2-53), the error correction at the position i is executed.

(Syndrome Generating Unit) Next, the configuration and operation of the BCH encoding / decoding device according to the embodiment of the present invention will be described in detail for each configuration unit.

In step 1, the reception sequence R = serially transmitted
Serialize the coefficients (S _2t-1 , S _2t-2 …, S ₁ , S ₀ ) of the syndrome polynomial required in step 2 from (r _n-1 , r _n-2 …, r ₁ , r ₀ ). Need to output. The following iterative algorithm is used for specific calculation of the coefficient of the syndrome polynomial.

S _j-1 = (... ((r _n-1 ^* α ^j + r _n-2 ) ^* α ^j + r _n-3 ) ^* α ^j + ... + r ₁ ) ^* α ^j + r ₀ Disassemble into.

Z ₀ = 0 Z _i = Z _i-1 ^* α ^j + r _ni (i = 1, ..., n) S _j-1 = Z _{n In} order to downsize the circuit, there is no meaning in the PE of FIG. 41. Delete the multiplier and the register of 5. by this,
The PE calculation unit has 400 gates. Here, paying attention to the movement of the received symbol in FIG. 42, one received symbol r _ni
Is sent from the PE of # 1 to the PE of # 2t without changing the value, and the term of Z _i-1 * α ^j to be added only changes.
Therefore, in the previous chapter, the PE of the syndrome generator is set to α ^j (j = 1,
,, 2t), but here, from α ^j input to α ^j
The values of (j−1, ..., 2t) are sequentially input, and the input of α ^j (j = 1, ..., m) is periodically repeated with j = 1 to m as one cycle. And the input of the received sequence is r _{i
Causes the} received symbol r _ni (i = 1, ..., N) to be input while the value of one received symbol is held for one cycle. By this, the register 7 can also be deleted, and the r _i input is directly input to the adder. However, since the register 6 needs to store the calculation result of Z _i for one cycle from the PE of # 1 to the PE of #m, m stages are required. The signal flow when m = 2t is shown in FIG.

At the beginning (i = 1), the selection signal S1,2 of the selector becomes S1,2 = 10 only when r _n-1 is input, and C from the X output.
This is the calculation result when the input 0 is output and i = 1.
Z ₁ = r _ni is sequentially input to the 2t stage register. After that (i = 2, ..., n), by setting S1,2 = 00, the A output is selected as the X output of the selector, and Z _i-1 which is the result of the previous operation is sequentially output from the X output. Every black CK α ^j (j =
1, ..., 2t) and added to r _ni to give Z
_i = Z _i-1 * α ^j + r _ni (j = 1, ..., 2t) is calculated and input to the rank register. Therefore, the 2t stage register is S _i-1
It is a memory unit for temporarily storing the intermediate result of the calculation of (j = 1, ..., 2t) and feeding back again. With this, the processing of 2t PEs can be realized by one PE, but the processing speed becomes (16 / 2t) Mwps because it is necessary to hold the input r _ni for the number of register stages.

Here, the multiplier 3 is removed to reduce the size of the circuit.
The register row of 7 and 7 is also omitted. Therefore, the PE circuit scale in Fig. 2 is (400 + m * 50) gates, and the processing speed is (16 / m) Mwps. m is the number of stages of the register, but when all processing is performed in 1 PE, m = 2t. As an example,
When the correction capability t = 8, the circuit scale of 1PE is 120 gates, and the processing speed is 1Mhz = 8Mbps.

Further, when the whole processing is not configured with one PE but is configured with a plurality of PEs, the PEs in FIG. 2 are connected as shown in FIG. At this time, a register controlled by CK2 (clock for each cycle) is required to delay the received symbol by one cycle for each PE. If the number of PEs is k, the whole process is (2t
/ k), the number of register stages required for 1PE is m = (2t / k). Therefore, the circuit scale of Fig. 4 is (2t
/ m) * (400k + m * 50) Gate. Two in FIG.
The signal flow when configured with PE is shown. In this case, the allocation of α ^j is that the PE of # 1 is α ^j (j = 1, ..., T) and the PE of # 2 is α ^j (j = t + 1, ..., 2t). In this case, since the number of register stages is m = t, the processing speed is 2Mhz = 16Mbps,
The circuit scale is 800 * 2 = 1600 gates.

When m = 1, the required number of PEs is k = 2t, and CK
Since 2 = CK, the register controlled by CK2 is register 7.
Is equivalent to, and the processing speed is 16Mwps. Therefore, this is a configuration in which the useless circuit of FIG. 42 is omitted. Also, using the fact that the B input of the selector is empty,
By inputting the S (x) output of the PE, the coefficients (S _2t-1 , S _2t-2 , ..., S ₁ , S ₀ ) of the syndrome polynomial are serially output as S ′ (x) from the last PE. be able to.

(GCD Generator (Error Location Polynomial and Error Value Polynomial Generation)) The derivation algorithm of the error location polynomial σ (x) and the error value polynomial ω (x) in Step 2 can be reduced to the extended GCD problem. In the circuit of Figure 43, each PE is a Proc
When the ess processing was completed, the output was passed to the next PE, and the processing itself was performed 2t times after receiving the next input. The process processing result of 2t times is not output to the next PE, is stored in its own register, and after the series of inputs of the syndrome polynomial S (x) and x ^2t is finished, the result stored in the register is fed back, Consider that all processing is performed by one PE.

The structure of PE at that time is shown in FIG. Similar to Figure 43
Circuit to set State and CK2 and CL to hold α and β
It is necessary to insert another stage register after the registers controlled by and the register rows 5 and 7 in order to realize a _i-1 and b _i-1 . Therefore, when the number of register stages in PE is m,
The circuit scale required for 1PE (excluding the state setting circuit is the control unit) is (700+ (3m + 4) * 5
0) It becomes a gate. (700 is the circuit scale of the arithmetic unit,
(3m + 4) is the total number of registers) When all processing is performed by one PE, m = 2t (because the order of the polynomial of the processing result does not exceed 2t)
FIG. 7 shows the first part of the signal flow when obtaining A (B) in the example shown in the figure, and FIG. 8 shows the first part of the signal flow when obtaining L (M). Switching of the selector selection signal and control of CK2 are performed by the basic clock CK every (m + 1), taking into account the inserted register, so that the operations in Fig. 44 and Fig. 45 are performed sequentially by one PE. I understand that

It should be noted that two process parts must be independently provided or one must be used twice for obtaining A (B) and L (M). Below, we will evaluate one Process process. If one Process part is used twice, the processing speed will be halved, and if two Process parts are independently provided, the number of PEs required will be doubled. Good.

Here, the syndrome polynomial S (x) (or M =
1) and x ^2t (or L = 0) only when the selector selection signal S1,2 = 11, the selector that outputs the D and E inputs to the X and Y outputs is used. (Shown in the table are the combinations of selector outputs.) When processing A (B) and L (M) in one Process section, use PE shown in FIG.
By controlling S1..4, A = x ^2t , B = S (x), L = 0,
You can also input M = 1. (The combinations of selector selection signals are shown in the table.) However, the PE of # 2t + 2 in FIG. 43 is meaningful only for the signal selection by the selector, so the PE of FIG. 9 is used.
The number of processing by PE is 2t + 1 times by using the W output of
(Also, in the PE of FIG. 6, the processing circuit is reduced to 2t + 1 times by providing a separate selector. Also, the signal input of # 2t + 2 is output from W by setting S4 = 1 when degB <t. Therefore, the processing speed here is (16 / 2t / m) Mlps because the processing of FIG. 43 is performed for every m number of register stages. As an example, when t = 8 and m = 2t, the circuit scale is 3300 gates and the processing speed is 1 / 16Mlps = n / 16Mwps.

Further, when the whole processing is not configured with one PE but is configured with a plurality of PEs, the PEs in FIG. 6 are connected as shown in FIG. At this time, in order to operate while circulating coefficient data in each PE, it is necessary to feed back the output of the last PE to the PE first. If the number of PEs is k, the total processing is (2t /
k), the number of register stages required for 1PE is m
= (2t / k). Therefore, the circuit scale of Fig. 11 is (2t /
m) * (700+ (3m + 4) * 50)

FIG. 12 shows the signal flow when it is configured with two PEs. In this case, since the number of register stages is m = t, the processing speed is 2/16 Mlps, and the circuit scale is 1950 * 2 = 3900 gates.

When m = 1, the number of PEs required is k = 2t, and the processing speed is 16 Mlps. In this configuration the last PE to the first
Since the feed back is performed to the PE, the number of PEs is 2t for 2t + 1 times of processing. If the number of PEs is set to 2t + 1 corresponding to the number of times of processing for a systolic connection, the signal does not need to be feedback-backed, and the same configuration as shown in FIG. 43 is obtained. (In this case, the PE of # 2t + 2 serves as a selector.) (Error position and error value generation unit) Step 3 can also use the following iterative algorithm and decomposition formula as in Step 1.

f = (x) = f _t-1 * x ^t-1 + f _t-2 * x ^t-2 ... + f ₁ * x + f ₀ = (... ((f _t-1 * x + f _t-2 ) * x + f _t-3 ) * X + ... + f ₁ ) * x + f ₀ ) Z ₀ = 0 Z _i = Z _i-1 * x + f _ti (j = 1, ..., t) f (x) = Z _{t In} addition, in order to miniaturize the circuit. As in step 1, the multiplier 3 and the register 5 are deleted. Further, in the circuit of FIG. 46, the input of α ^-1 (i = n-1, ..., 0) is the same as in step 1 #
It is only sent from the PE of 1 to the PE of #t without changing the value. Therefore, j ⁻¹ to m is one cycle and α ⁻¹
Α ⁻¹ (i = n−1, ..., 0) so that one value of
Enter

In addition, the coefficient of ft-i is f
The input of _ti (j = 1, ..., m) must be repeated. Considering the output from the GCD generator of step 2,
The coefficient f _ti (j = 1, ..., T) is output once, but is not repeatedly output periodically. Therefore, a PE is constructed as shown in FIG. 13 by using the selectors and the m-stage register array 7 which are output by the selection signals S1, 2 in a combination as shown in the table, and signals are sent as shown in FIG. From the GCD generator, the coefficient _ti (j = 1, ...,
t) is output, the selector selection signal is S1,2 = 1
By setting S1,2 = 01 from 1 (only when f _t-1 is input), the coefficients f _ti (j = 1, ..., t) are sequentially output from the Y output and input to the register row 7. To be done.

The output is B input feedback and the selector selection signal is changed from S1,2 = 10 (only when ft _-1 is input) to S.
By setting 1,1 = 00, the coefficient f _{ti is} again _calculated from the Y output.
(J = 1, ..., T) is output and input to the register train 7. After that, by repeating the operation, the coefficient f _ti (j
= 1, ..., t) periodic input is realized. As a result, the processing of m PEs can be realized by one PE as in step 1, but the processing speed is (16 / m) Mwps because it is necessary to hold the input α ^-1 for the number of register stages. (M is the number of register stages) Also, the circuit scale required for 1PE is (400 + (m + 1) * 50)
Become a gate.

Although m is the number of register stages, when all processing is performed in 1 PE, m = t. However, ω (x), σ (x), σ ′
3 sets of PE are required for the treatment of (x). As an example, when the correction capability t = 8, the circuit scale is 3 * 850 = 2.
It has 550 gates and the processing speed is 2Mwps.

Further, when the whole processing is not configured by one PE but is configured by being divided into a plurality of PEs, the PEs of FIG. 13 are connected as shown in FIG. At this time, in order to delay α ^-1 in 1 cycle units per 1 PE, CK2
A register controlled by (clock for each cycle) is required.

When the number of PEs is k, the entire processing is distributed to (t / k), so the number of register stages required for one PE is m = (t / k). Therefore, the circuit scale in Figure 15 is (t / m) * (400+ (m
+1) * 50) It becomes a gate. Fig. 16 shows the signal flow when it is configured with two PEs. In this case, since t = 8, m = (t / 2) = 4 and the circuit scale is 3 * 2 * 650 = 3900.
It becomes a gate and the processing speed becomes 4Mwps.

When m = 1, the required number of PEs is k = t, and CK2
= CK, so the register controlled by CK2 is register 5
It becomes the same as, and except the allocation part of f _ti , it has the same configuration as in Fig. 46, and the processing speed is 16 Mwps.

Further, FIG. 17 shows a PE when σ (x) and σ ′ (x) are processed by one PE, and FIG. 18 shows a signal flow. In Step 3, since one cycle is t, 1PE can be used twice, and the coefficient of σ ′ (x) uses the coefficient of σ (x). As a result, step 3 can be realized with a 2-set PE, and as shown in FIG. 18, σ (x), σ '
The operation of (x) is every 2t, and the output of ω (x) can also be operated every 2t by making it as shown in FIG. Here, the selector selection signal is set to S only when the Y output becomes 0 by using the selector whose output combination is as shown in the table.
1..3 = 001 should be set. In this case, the processing speed is 2Mwps / 2
= 1Mwps, and the required PE set is also 2 sets, so the circuit scale is 2 * 850 = 1700 gates.

(Erasure Position Polynomial Generation Unit) Here, S necessary for receiving the coefficient output S (x) of the syndrome polynomial from step 1 and performing erasure correction.
Generate (x) * λ (x).

First, consider generating the erasure position polynomial λ (x).

λ (x) = (1- Y 1 * x) * (1-Y 2 * x) ... (1-Y 5
* X), and decompose λ (x) as follows, as in the previous chapter.

Z ₀ = 1 Z _i = (1-Y _i * x) * Z _i-1 = Y _i * Z _i-1 * x + Z _i-1 (i = 1, ..., s) λ (x) = Z ₅ First , The multiplier 3 and the register 6 are removed in order to miniaturize the circuit. Here, it corresponds to the number of processing clocks or the number of register stages. Also, prepare one register to delay the Z _i-1 input by one clock. Therefore, the PE configuration is as shown in Fig. 22, and the circuit scale required for 1PE is (400+ (m +
1) * It becomes the gate of 50). (M is the number of register stages) 23rd
The signal flow is shown in the figure.

The number of register stages in one PE is m (here, m = 2t), and one cycle of Y _i is held so that Y _i (i =
Enter 1,…, s). First (when Y _{1 is} input), the selector selection signal is set to S1, 2 = 11 and the D input Z ₀ = 1 is input to X, the C input 0 is input to Y, and the operation result Y ₁ is input to the register row 6 at the next clock. To do. After that, S1,2 = 10 is set, C input 0 is input to X, A input is output by delaying Z ₀ by 1 clock to Y, and the operation result Z ₀ = 1 is input to the register train 6 at the next clock. Since the operation result is 0 after the next clock, 0 is input to the register sequence 6. One cycle later (when Y _{2 is} input), the pre-computation result Z ₁ = Y ₁ * x + 1 (where order x represents the order of signals) is output from the register string 6, so S1, 2 = 01 and pre-computation is performed on X. results of the highest order coefficient Y1 from the a input, and inputs the Y ₁ * Y ₂ outputs calculated results 0 C input to the register train 6 with clock in Y.
After that, S1,2 = 00 is selected, the coefficient 1 next to Z ₁ is input to X from A input, the highest coefficient Y ₁ of Z ₁ delayed by 1 clock to Y is selected from B input, and the calculation result Y ₁ + Y ₂ is selected. Input to the register string 6 at the next clock. At this time, 0 is output from X, the coefficient 1 next to Z ₁ is output from Y, the operation result 1 is input to the register sequence 6 at the next clock, and 0 is input since the operation result is 0 thereafter. By repeating the operation at the time of Y ₂ input after Y ₃ input, λ (x) is output from the higher order coefficient from the register array 6 after Y ₅ input.

Since s ≦ 2t, Y _i = 0 (i = s + 1, ..., 2t) may be input.

Therefore, the processing speed is (16 / 2t / m) Mlps. As an example, if t = 8 and all processing is performed with 1 PE, the circuit scale is 1250 gates and the processing speed is 1/16 Mlps.

Further, when the entire processing is not configured by one PE but is configured by being divided into a plurality of PEs, the PEs of FIG. 22 are connected as shown in FIG. At this time, in order to hold the value of Y _i for 2t clock, for each PE
You need a register to set Y _i . If the number of PEs is k, the entire processing is distributed to (2t / k), so the number of register stages required for one PE is m = (2t / k). Therefore, the circuit scale of FIG. 24 is (2t / m) * (400+ (m + 1) * 50) gates. Fig. 25 shows the signal flow when it is composed of two PEs. At this time, the circuit scale is 850 * 2 = 1700 gates, and the processing speed is 2/16 Mlps.

When m = 1, the required number of PEs is k = 2t, and the processing speed is (16 / 2t) Mlps, which is equivalent to the configuration of FIG.

Next, consider the multiplication circuit S (x) * λ (x). Multiplication C
The calculation of (x) = A (x) * B (x) is decomposed as follows as in the previous section.

When A (x) = a _m-1 * x ^m-1 + a _m-2 * x ^m-2 + ... + a ₁ * x + a ₀ C (x) = a _m-1 * B (x) * x ^{m -1} + a _m-2 * B (x) * x ^m-2 + ... + a ₁ * B (x) * x + a ₀ B (x), so Z ₀ = 0 Z _i = Z _i-1 * x + B (x ) * A _mi (j = 1, ..., m) C (x) = Z _m Therefore, while a (x) is input, hold a _mi and keep Z _i
= Z _i-1 * x + 8 (x) * a _mi is calculated and then register sequence 6
Then, after one cycle, the calculation result may be set as Z _i−1 and feedback may be performed. However, the inputs S (x) and λ (x)
Is only input at the transfer rate of once the basic clock CK from the syndrome generator of step 1 and the above-mentioned error locator polynomial generator. Therefore, repetitive input is realized by using the register rows 5 and 7, and the set value is held by using the register controlled by CK2. In addition, B from register row 7
Since the (x) output needs to be fed back one clock later than the Z _i-1 output from the register train 6, the PE configuration is as shown in FIG. B (x) = S (x), a _mi = λ
FIG. 27 shows the signal flow in the case of _2t-i (i = 0, ..., 2t). (The number of register stages in one PE is m-1 = 2t-1) First, λ (x) is set to F as the selector selection signal S1,2 = 01.
Input from the input to the register array 5 through the W output. At that time, the highest-order coefficient λ _2t of λ (x) is stored in the register controlled by CK2 and set to the input of the multiplier 3. Also S
Input (x) to E with one clock delay from λ (x),
It is output to Y and input to the register train 7. Meanwhile, X outputs C input 0. As a result, λ _2t * S (x) is calculated and input to the register train 6. At this time λ (x) * S
Since the highest-order coefficient λ _2t * S _2t-1 of (x) has been calculated, C
It is latched and output by KD. One cycle is m (here, m = 2t), and one cycle later the selector selection signal S1,2 = 00
And From B, S (x) fed back by the m-stage register train 7 is input, and again input from Y to the register train 7. From D, λ (x) with the highest-order coefficient deviated by the m-stage register train 5 is fed back and W
Is output to Therefore, in CK2, the coefficient λ next to λ (x) is
_2t-1 is stored and set in the multiplier 3. M-1 from A
The highest order coefficient of all the calculation results is shifted by the register row 6 of the stages and is fed back and is input in the form where the first order coefficient is shifted with respect to B (x) = S (x). This gives Z _i
= Z _i-1 * x + B (x) * a _mi is the register sequence 6
Is input to Thereafter, the same calculation is performed until λ ₀ is input to CK2 and the calculation is completed. However, the result of the calculation, which is the answer, will be misaligned when the input is fed back, so
It is output by CKD each time it is calculated. Also λ (x)
Since the coefficient of is also shifted when the input is fed back, the coefficient is decreased by each primary. Since the shifted coefficient is not necessary, the selector selection signal should be set when feeding back.
By setting S1,2 = 10, 0 is output to X and W.

Further, since the answer operation result remains in the register array 6 after completion of the operation, by repeating the same operation, the result in the register array 6 is shifted by one coefficient and output from CKD.

The circuit scale required for 1PE is the number of register stages in PE is m-1
(400 + 3m * 50) gate). Moreover, the processing speed is (16 / 4t / m) / 2 because it is necessary to consider from the end of calculation to the end of output. When all processing is performed in 1 PE, the number of register stages in PE is m = 2t, and correction capacity t = 8 as an example.
In this case, the circuit scale is 2800 gates and the processing speed is (1/32) Mlps.

Further, when the whole process is not configured by one PE but divided into a plurality of PEs, the PEs of FIG. 26 are connected as shown in FIG. 28. At this time, in order to hold the value of a _mi for 2t clock, a register for setting a _mi is required for each PE. If the number of PEs is k, the entire processing is distributed to (2t / k), so the number of register stages required for one PE is m = (2t / k). Therefore,
The circuit scale in Fig. 28 is (2t / m) * (400 + 3m * 50) gates. FIG. 29 shows a signal flow when two PEs are configured. At this time, the circuit scale is 1600 * 2 = 3200 gates,
The processing speed is (1/16) Mlps.

When m = 1, the number of PEs required is k = 2t, and the processing speed is (1/2) Mlps.

(Encoder) Encoding is performed from information I (x) = (I _k-1 , I _K-2 , ..., I ₀ ) to parity P (x) = (P ₂ t, P _2t-1 , ..., P _1). ) Is generated. Encoding means that the generator polynomial is g (x) = g _m * x ^m + g _m-1 * x ^m-1 + g _m-2 * x ^m-2 … + g ₁ * x + g ₀ P (x) = I ( x) * ^m mod g (x), and g '(x) = g _m-1 * x ^m-1 + g _m-2 * x ^m-2 ... + g ₁ * x + g ₀ It is decomposed as follows.

Z ₀ = I (x) Z _i = g _m * Z ′ _i−1 + Z _m * g ′ (x) (i = 1, ..., k) P (x) = Z _k where Z _m is a polynomial Z _{i -1 is} the highest coefficient and _Z'i-1 is Z
_It is a polynomial in which the highest-order coefficient is removed from _i-1 . Z _m is g ′
(X) Hold during input and calculate _Zm * g '(x). Here, PE is configured as shown in FIG. 30 with g _m = 1.

The coefficients g _m-1 to g _{0 of} g _i to g '(x) are periodically input to the multiplier 2 with m as one cycle. Also, by the register controlled by CK2 (clock for each cycle) and CL
Hold Z _m and input to A. Z ′ _i-1 is the previous calculation result Z _i-1
Is output by 1 clock earlier than the cycle. Therefore, the number of stages of the register array 6 is set to m-1, and feedback is applied to the B input. The information I (x) is input from C so that one value is held for one cycle.

FIG. 31 shows the state of encoding. First, consider the case of i = 1. In the initial state, the information symbol I _k-1 is held in the register controlled by CK2, the information I _km-1 is input from the C input, and the information symbols I _k-2 to I _{km are} stored in the register sequence 6. Think of if. In the calculation section, from the A input
Multiplying I _k-1 by g '(x), I _{k-2 to} I _km from the B input,
And I _km-1 from C input, and input to each register 6. (Switching of the B and C inputs to the Y output is performed by the selector selection signals S1,2, and when the B input is S1,2 = 00,
When C input, S1,2 ＝ 01) The calculation result is calculated from the higher-order terms of Z ₁ as I ′ _k-1 = I _k-1 * g
_mi + I _ki-1 (J = 1, ..., m) After i = 2, I ′
Encoding is performed by performing the same processing for _ki up to i = k.

Further, in order to realize the initial state, the process is performed as shown in FIG. 32 (when m = 4). Information is input so that the value is held for one cycle from I _{k-1 to} I ₀ . First, the selector selection signal S
With 1,2 = 01, the first received symbol I _k-1 is input from C and output to Y. C of register controlled by CK2 to A input
Input 0 by L and output X. Since the number of register stages in PE is m-1, I _k-1 is fed back to the B input one clock cycle before. Then S1,2 ＝ 00
Then, the B input is output to Y for only one clock, and the settings of S1 and S2 are restored. At this time, the next received symbol I _k-2 is input from C, so that I _k-1 is input to the register sequence 6 for one clock and then I _k-2 is input. During I _k-2 input, the deviation from the feed back input from the register train 6 is 2 clocks, so the selector selection signal S
1,2 = 00. At that time, I _{k- 2} is selected one clock after I _k-1 . By performing the above operation up to I _km , _{Ik-1 to} I _km are accumulated in the register train 6. When I _km-1 is input, I _k-1 overflows from the register row 6 but is latched in the register controlled by CK2, thereby realizing the initial state.

In addition, the information I (x) and the parity P (x) after the calculation is completed.
Switching is also performed using the Z output of the selector as shown in FIG. During the encoding operation described above, Z outputs the C input which is the input of the information symbol for each cycle. After completion of the calculation, the parity output is circulated through the register train 6. However, since the number of register stages in PE is m-1, the register controlled by CK2 outputs the parity deviated by one degree for each cycle of parity and feed back to the A input. To do. At that time, Z selects the A input and outputs it every one cycle of parity.

Therefore, the circuit scale and processing speed at this time are (400
+ M * 50) gate, and (16 / m) Mwps. The whole process
When configured with 1 PE, m = 2t. As an example, when the correction capability t = 8, the circuit scale of 1PE is 1200 gates, and the processing speed is 1Mwps = 8Mbps.

Further, when the entire processing is not configured with one PE but is configured with a plurality of PEs, the PEs in FIG. 30 are connected as shown in FIG. 34. PE
Since the total processing is distributed to (2t / k) where k is the number of, the number of register stages required for 1PE is m = (2t / k). Therefore, the circuit scale of Fig. 34 is (2t / m) * (400 + m
* 50) It becomes a gate. FIG. 35 shows the signal flow in the case of being configured with two PEs. In this case, the number of register stages is m = t
Therefore, the processing speed is 2Mwps = 16Mbps and the circuit scale is 800 * 2 = 1600 gates.

When m = 1, the required number of PEs is k = 2t, but #
Feed back from PE of k to PE of # 1, and I (x)
In this architecture, the encoder does not have a systolic configuration either, since the simultaneous inputs of the same are not changed.

(Error correction execution unit and system) The f (α ^-i ) output of step 3 is output by 1 CK every 2t when PE in FIG. 17 is used, but σ '(α ^-i ) and σ
(Α ^-i ), ω (α ^-i ) the timing is shifted by half a period, so σ '(α ^-i ) is latched by the register controlled by CK2 (clocks every 2t), and σ (σ ^-i ), ω (α ^-i ) is CK
Latch with 2 '(clock that is a half cycle of CK2), and
4th by latching with the register controlled by CK2
The error correction of step 4 similar to that of FIG. 8 is realized. (The timing is shown in Fig. 21. However, in the case where the process of A (B) and L (M) is used twice in the GCD generation unit, the coefficient of ω (x) comes first. Since it is sent, it is necessary to go through the buffer.) When the execution unit of the error correction of Step 4 is optimized, it becomes as shown in FIG. ω
The operation after the output timings of (α ^-i ) and σ (α ^-i , σ '(α ^-i ) are adjusted is the same as in the previous chapter.) Therefore, the circuit scale required in step 4 is buffer. For reciprocal generation
Excluding ROM, 450 + 5 * 50 = 700 gates. Since the error correction execution unit of Step 4 does not have a systolic structure, the circuit cannot be downsized even if the number of register stages is increased. Therefore, the optimum circuit may be simplified according to the situation. The same applies to the α ^-i (i = n−1, ..., 0) generation circuit.

As described above, each decoding step of the RS code can reduce the circuit size at the cost of high speed. In the decoder of FIG. 49, as an example,
The control of PE can operate the whole system only by the selector selection signal and CK2.

Step 1) SYNDROME: Fig. 2 Step 2) GCD: Fig. 6 Step 3) EVALUATE: Fig. 13 Step 4) CORRECT: Fig. 20 Erasure error correction of Fig. 50 when the encoder / decoder is considered as a system. For example, the following combination can be used to realize a miniaturized coding / decoding decoder.

1) SYNDROME: Figure 2 2) GCD: Figure 6 3) EVALUATE: Figure 13 4) CORRECT: Figure 20 5) ERASURE I: Figure 22 6) ERASURE II: Figure 26 This is shown in Step 4 ERASURE I and ERA to the decoder
SURE II is added. Further, the encoder shown in FIG. 30 may be added to the decoder shown in step 4 to form a coding / decoding device. (When encoding and decoding are not performed at the same time, the code change decoder is realized without changing the circuit scale in the circuit of FIG. 49 by making the PE connection and PE control variable by encoding and decoding. Yes) The circuit scale (gate unit) and processing speed (Mwps unit) in each process are as follows, as described above.
(Wps = word / sec) 1) (2t / m) * (400 + m * 50), 16 / m 2) (2t / m) * (700+ (3m + 4) * 50), n * (16 / 2t)
/ m) 3) 2 * (2t / m) * (400+ (m + 1) * 50), 16 / m 4) 700 5) (2t / m) * (400+ (m + 1) * 50), n * (16 / 2t
/ m) 6) (2t / m) * (400 * (3m + 2) * 50), n * (16/4
t) / m) 7) ENCODE: Fig. 30; (2t / m) * (400 + m * 50), 16 / m As an example, when the RS decoder has t = 8, the circuit scale and processing are as follows. Can be achieved at speed. (Code length n ≧ 4t, and m = 2t to realize with 1PE) 1200 + 3300 + 2500 + 700 = 7700gate 1Mwps = 8Mbps When t = 2, 600 + 1500 + 1300 + 700 + 3100gate 4Mwps = 32Mbps.

Although the basic configuration of PE is shown in FIG. 1, if the circuit scale of GF (2 ^m ) is M gates, the circuit scale of GF (2 ^{2 m} ) is about 4 M gates. However, considering that the structure of 1 word changes from m bits to 2 m bits, the processing speed per PE is 10 to 20 MWps (words / second), so m · (10 to 2
It will be doubled from 0) Mbps to 2m · (10 to 20) Mbps.
Therefore, assuming that the actual processing speed is bps, the PE having the same processing speed may have two PE register stages in FIG. Then, the required number of PEs is k = (2t / m), m =
Since it is 2, there are t pieces. Therefore, the Galois field composition is GF
When (2 ^M ) is changed to GF (2 2 ^M ), the increase in circuit size at the same processing speed doubles. Generally, when the Galois field structure is changed from GF (2 ^m ) to GF (2 ^am ), the increase in circuit scale is a times.

〔The invention's effect〕

As described above, according to the present invention, a part of a plurality of inputs from the outside is input to a code processing device that processes an error correction code defined on a finite field, and at least 2 is input according to a selection signal. A selector for selecting and outputting one and multiplying one of the outputs of the selector and one of the plurality of inputs 1
An adder for adding one or more multipliers, an output of the one multiplication, and an output of another one of the multipliers or the selectors, or one of the plurality of inputs; and an output of the adder, or A plurality of stages of registers for holding one or more outputs of the selector and then outputting the outputs to the outside, and one processing element for feedback-inputting the output of the registers as one of the inputs from the outside, Alternatively, a plurality of processing circuits connected in series may be provided, and a received word and a power of a primitive element of the finite field may be input to one of the processing circuits to generate a syndrome polynomial. To one of the processing circuits to generate the error locator polynomial and the error evaluator polynomial, and to the other one of the processing circuits, the error locator polynomial and a polynomial obtained by differentiating the polynomial, and the error evaluator. Input any one of the expressions and the power of the primitive element, execute the operation of substituting the power of the primitive element into each polynomial, and based on the result of the operation, the position and value of the error in the received word. So that each of the processing elements in each processing circuit is provided with a plurality of stages of registers,
By feeding back the output and processing it, the number of processing elements can be reduced, and the circuit scale can be reduced. If necessary, processing elements can be connected in series to speed up the processing, and an appropriate device can be realized in consideration of the balance between the processing speed and the circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram of a miniaturized processing element (PE) according to the present invention. FIG. 2 is an explanatory diagram of a syndrome generation circuit in which the PE of FIG. 1 is optimized according to the present invention. PE timing diagram of FIG. 4 is a connection diagram of PE of FIG. 2 according to the present invention. FIG. 5 is a timing diagram of a syndrome generation circuit using two PEs of FIG. 2 according to the present invention. FIG. 7 is an explanatory diagram of a GCD generation circuit using the PE of FIG. 7. FIG. 7 is a timing diagram of a GCD generation circuit using the PE of FIG. 1 according to the present invention. FIG. 8 is the PE of FIG. 1 according to the present invention. Timing diagram of GCD generation circuit FIG. 9 is an explanatory diagram of a GCD generation circuit using the PE of FIG. 1 according to the present invention. FIG. 10 is an input timing diagram of FIG. 9. FIG. 11 is a PE of FIG. 1 according to the present invention. FIG. 12 is an explanatory view of a GCD generation circuit with optimized GCD generation circuit using two PEs shown in FIG. 11 according to the present invention. Circuit Timing Diagram FIG. 13 is an explanatory diagram of an error evaluation circuit that optimizes the PE shown in FIG. 1 according to the present invention. FIG. 14 is a timing diagram of the PE shown in FIG. 13 according to the present invention. PE connection diagram of FIG. 16 is a timing diagram when two PEs of FIG. 13 according to the present invention are used. FIG. 17 is an explanatory diagram of an error evaluation circuit in which the PE of FIG. 13 is optimized according to the present invention. FIG. 18 is a timing chart of FIG. 17 according to the present invention. FIG. 19 is a timing chart of FIG. 17 according to the present invention. FIG. 20 is an optimized error correction execution unit according to the present invention. FIG. 21 is FIG. 20 according to the present invention. FIG. 22 is an explanatory diagram of an erasure position polynomial generating circuit that optimizes the PE of FIG. 1 according to the present invention. FIG. 23 is a timing diagram of PE of FIG. 22 according to the present invention. FIG. Fig. 22 PE connection diagram Fig. 25 is a timing diagram when two PEs of Fig. 22 are used according to the present invention. Fig. 26 is present invention. FIG. 27 is an explanatory diagram of a multiplier circuit that optimizes the PE shown in FIG. 1. FIG. 27 is a timing diagram of the PE shown in FIG. 26 according to the present invention. FIG. 28 is a connection diagram of the PE shown in FIG. 26 according to the present invention. Timing diagram when two PEs of FIG. 26 according to the invention are used. FIG. 30 is an explanatory diagram of an encoder in which the PE of FIG. 1 is optimized according to the present invention. FIG. 31 is of the PE of FIG. 30 according to the present invention. Timing diagram (in process) FIG. 32 is a timing diagram of PE of FIG. 30 according to the present invention (at initial input) FIG. 33 is a timing diagram of PE of FIG. 30 according to the present invention (at the time of numerical output) FIG. FIG. 30 is a connection diagram of PE according to the present invention. FIG. 35 is a timing diagram when two PEs according to the present invention are used. FIG. 36 is a configuration diagram of a conventional processing element (PE). FIG. 37 is a conventional processing.・ Element (PE) selector configuration diagram Figure 38 shows the configuration of a conventional processing element (PE) multiplier FIG. 39 is a block diagram of a conventional processing element (PE) adder. FIG. 40 is a diagram for explaining an algorithm for obtaining a GCD. FIG. 41 is a diagram for explaining a conventional PE for syndrome generation. Fig. 42 is a connection diagram of a conventional PE for syndrome generation. Fig. 43 is a connection diagram of a conventional PE for GCD generation. Fig. 44 is a diagram showing the operation timing of a conventional PE for GCD generation. Fig. 45 is a conventional GCD. Fig. 46 shows the operation timing of the PE for generation. Fig. 46 is a connection diagram of the conventional PE for error evaluation. Fig. 47 is a connection diagram of the PE for conventional erasure position polynomial generation. Fig. 48 is a description of the conventional PE for error correction execution. Fig. 49 is a block diagram of a conventional error correction decoder system. Fig. 50 is a diagram showing an example of an erasure error correction decoder. ...... Adder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 63-157525 (JP, A) JP 63-164624 (JP, A) JP 63-156430 (JP, A) IEICE technical research Report, Technical Report Vol. 86, no. 301, P. 15-22 (IT86-102, IT86-103)

Claims (3)

(57) [Claims] 1. A code processing device for processing an error correction code defined on a finite field, wherein a part of a plurality of inputs from the outside is input and at least two are selected according to a selection signal. A selector for outputting, one or more multipliers multiplying one of the outputs of the selector and one of the plurality of inputs, an output of the one multiplier, and another one of the multipliers or the selector An adder for adding an output or one of the plurality of inputs; and a plurality of stages of registers for holding the output of the adder or one or more outputs of the selector once and then outputting the output to the outside. , The output of the register is 1 of the input from the outside.
One processing element for feedback input as one, or a plurality of processing circuits having a plurality of serially connected processing elements, wherein one of the processing circuits inputs a received word and a power of a primitive element of the finite field, A syndrome polynomial is generated and the syndrome polynomial is input to another one of the processing circuits to generate an error locator polynomial and an error evaluation polynomial. A polynomial obtained by differentiating a polynomial, one of the error evaluation polynomials, and a power of the primitive element are input, an operation of substituting the power of the primitive element into each polynomial is performed, and based on the result of the operation, A code processing device which estimates and corrects the position and value of an error in a received word. 2. A received word is input to one of the processing circuits to generate a vanishing position polynomial, and the other vanishing position polynomial and the syndrome polynomial are input to another one of the processing circuits. The code processing device according to claim 1, wherein a product polynomial is generated and erasure correction is performed. 3. A code processing apparatus according to claim 1, wherein information and a generator polynomial are input to one of the processing circuits to generate a parity and the information is encoded. .