JPS63164625A - Gcd generating circuit - Google Patents

Abstract

PURPOSE:To attain large scale circuit integration with small size by connecting plural identical arithmetic circuits each comprising a multiplier on the Galois field, an adder, and m-stage of register arrays storing its addition output and selector output and using polynomials A, B to obtain its greatest common divisor polynomial GCD [A, B]. CONSTITUTION:In obtaining polynomials A, B and L, M, two independent Process sections are to be provided or one Process section is to be used twice. In using one Process section twice, the processing speed is halved and in providing two Process sections independently, number of required PEs is doubled. For example, the relation of selector selection signals S1, 2=11 is selected only at the input of syndrome polynomials Sx, x<21>, selectors outputting D, E inputs at the X, Y outputs are used. Moreover, in processing A, B and L, M by one processing section, the processing element PE shown in figure is used to control S1-S4 thereby inputting A=x<21>, B=Sx, L=0, M=1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of error correction, and also relates to a technique for performing parallel processing in signal processing targeting communication channels.

The present invention uses GCD (
Regarding the technology for generating (greatest common divisor).

[Prior art and its problems]

In recent years, the application of error detection and error correction codes (hereinafter simply referred to as error correction codes) has become widespread as a measure to improve the reliability of various digital systems including memory systems.

There are various types of error correction codes depending on the target system, but the most typical one is a class of linear codes called cyclic codes.

This includes BCI (code) suitable for random error correction.

Fire code suitable for burst error correction, and BCH
Reed- is a type of code and is suitable for byte error correction.
5olomon code (hereinafter referred to as R3 code). Among them, the R3 code is a code that is extremely important in practice because it has the lowest redundancy among linear codes with the same code length and correction ability, and is used in satellite communications, magnetic disks, and compact disks. (hereinafter referred to as CD), etc., is widely used.

There are various decoding methods for this R8 code, and there are 2 to 3 decoding methods.
It is relatively easy to implement a decoder for correction capabilities with small degrees of severity. However, in order to obtain high reliability, it is necessary to increase the correction ability.

In that case, problems arise in that the scale and control of the device becomes extremely complex, and the calculation time required for decoding processing also increases. For this reason, CDs currently use a type of double encoding called CIRC, but this poses a problem in systems that require higher reliability or higher speed. In addition, in order to obtain high reliability, magneto-optical disks use Long Di
A multiple error correction code called a stance code (hereinafter referred to as LDC) has been proposed, but the problem is how to achieve high speed.

Satellite communications require two things: high reliability and high speed, but when considering the development of equipment, it has been extremely difficult to satisfy the above two conditions.

Therefore, in "rBCH Encoding/Decoding System" (filed on December 22, 1985), which the present applicant previously applied for, the following was realized by taking advantage of the characteristics of the VLSI architecture.

l) High reliability (large capacity) 2) High speed 3) Regularity of internal structure 4) Large integration This allows 10-20Mwps = 80-1610-
We have shown that it is possible to realize an R3 encoder decoder with a processing speed of 20 or more. Also, for the correction ability, P of the same configuration
By increasing E in a linear manner, the configuration is such that arbitrary high reliability can be obtained. This is extremely effective for systems that require high reliability and high speed, such as satellite communications. In addition, the process of calculating the error locator polynomial and error value polynomial, which is the center of the decoding process, is performed using 10-210-2O (cod
This is a very effective method for high-speed processing because it can also be performed using length/5ec).

However, the data transfer rate used in CDs, magnetic disks, etc. is often less than 10 Mbps, and there is still a problem in this respect, as there is a demand for a smaller hardware capacity.

[Means for solving problems]

In view of the above points, the present invention makes use of the features of the architecture of the R3 encoding decoder shown in the above-mentioned rBCH encoding/decoding method previously filed by the applicant, while sacrificing the high speed condition in 2). [Embodiment] An architecture that can achieve the condition 4) with miniaturization by doing the following.Embodiments of the present invention will be described below based on the drawings.

The architecture of the R8 encoder decoder described above applies the idea of systolic architecture.

A feature of the systolic architecture is that one process is handled by the same network of the same PEs. This applies to all processing elements (P
This shows that the processing performed in E) is the same, and the input/output relationships are also the same. Therefore, after performing one process with one PE, the processing result is not sent to the next PH, but is stored in the memory (register) section and fed back to itself, allowing processing without increasing the number of PEs. I can do it. Therefore, we decided on the basic PE as shown in Figure 1. In FIG. 1, numerals 1-4 are the same as those in FIG. 36, but registers 5-7 form an m-stage register array or memory section.

Considering the circuit scale as GF (2"), the selector l is configured as shown in Fig. 37 with approximately 50 gates, and the multipliers 2 and 3 are connected to the third gate.
In the configuration shown in Figure 8, one gate has approximately 300 gates, and the 4 adders are the third gate.
With the configuration shown in FIG. 9, one register of 5-7 is calculated using about 50 gates.

Also, when focusing on one PE, in the previous architecture, after performing one process and outputting the processing result, that PE can receive and receive the next input, so high-speed processing that takes full advantage of IPE processing speed However, if the processing result is fed back to itself without sending it to the next PE, the receiver cannot receive the next input, so from an external perspective, the data transfer rate to one PE is slow. Become. however,
The processing speed of the PE itself is determined by the arithmetic unit of the PE consisting of 1-4, and its configuration remains unchanged, so the processing speed is 10-20 M h
It is z. Here, for later convenience, the IPH processing speed is assumed to be 16 MHz.

Hereinafter, the processing of steps 1-4 will be realized using this PE as a basic model, but for the purpose of miniaturization, unnecessary parts will be removed in each processing and the PE will be optimized in each processing.

First, the principle of the R3 code will be described. The R3 code is a code of great practical importance, having the characteristic of having the lowest redundancy among linear codes having the same code length and correction ability.

The R3 code is a non-dual BCH code (Bose-Chav
dhuri-Ilocquenghen code)
is a special case of finite field (hereinafter abbreviated as GF).
It is composed of elements of GF (q). Here, q is GF
It is the original number of (q).

Using this q, various parameters characterizing the R8 code are defined as follows.

・Code length: n (-number of symbols in the code) n≦q
-1 (2-1) ・Number of information symbols 2 k (-number of information symbols in code)
・Number of check symbols: n-k (-number of check symbols in the code) n- = dmin-1 (2-2) ・Correction ability: t (-number of symbols that can be corrected in the code)
([X] Gaussian symbol 6. The largest integer not exceeding x) where d m i n is what is called the minimum distance (Hamming distance)°.

Pressure L north Here, we will explain polynomial expressions such as code words.

For example, if you want to encode as many information symbols as I” (i
o+ 111...+ ih-+)
(210), this is expressed as a polynomial as follows.

I(x) = io+i, x+i, x”+...+
i, -, x'-"+1k-1x'-' (2-11)
Similarly, (n-k) check symbols C” (
cot c+,...,Cn-*-+)'
(212) is, C(x) = Co+C+ X+C2X"+ ・-・C
, - to -, xa- to -1 (2-13) Furthermore, the code word that combines these F F = (fo, f+, fzs・in-+)
(214):(Co,C+...'C,-h
−+ + Mt. L+! 2 , −ik−+ ) (
215) is F(x) = fo ten f + x ten f, x”+-f,,
−, x”-”+fn-+ x'-' (2-16) can be divided by the generator polynomial 〇(x) that generated it by α,
α2. ...Since it has a root α1, the code word polynomial F
By substituting this root into (x), the following equation holds true.

F(<2')=O(i=1,2.=・,n-k)
(2-21) Expression (2-21) is expressed as a matrix as follows (pT is the transposed matrix of F).

Here, the matrix H on the left side is called a parity check matrix and has an important meaning in decoding.

De2L method As already mentioned, since the R5 code is a type of BCH code, it can be decoded using a general RCH code decoding algorithm. However, in that case, handling of symbols such as addition and multiplication in the decoding process must be performed on the finite field GF (q) in which the R3 code is defined.

Considering the R3 code with code length n = 2″′-1 defined above, GF (2″′) (m: number of correct guesses),
The symbol is represented by an m-bit binary number, and the operation is GF(2
”). Also, equation (2-17) is used as the generator polynomial, and the minimum distance between codes is d min =
Let's put it as 2 t + 1.

g(x)=(x-αXx-a")-(x-a"-k)
(2-17) However, α is the primitive light on the finite field GF(2″′).The decoding procedure for such an R3 code consists of the following four steps, as in the case of a general CH code. It can be divided into

Step l) Syndrome calculation.

Step 2) Calculate error locator polynomial and error evaluation polynomial.

Step 3) Estimation of error location and error value.

Step 4) Execute error correction.

Step l Syndrome team: First, the transmitted codeword is F: F=(fo, f+, -
fn-+) error caused by E: E=(eo,
el,...en-1) R: R
= (ro, rl, "'rn-l) = F+E = (fo+eo, f++e+, -fn-++en
-+), the polynomial representation R(x') of the received word is as follows.

R(x) =F(x)+E(x)=(fo+e
o) + (f++e+) x+-...+ (fn-+
+en-1) x''-' (223) However, the code polynomial F (x) has the generator polynomial G (x) ((
By substituting the root a' (i=1.=-, n-k) of equation 2-17), (F(α') = O) holds, so we similarly set a to the received word polynomial R(x). i (i=1.-・-,
When substituting n-k), R(α')=F(α')+E(α')=O+E(α')
=E(αI), a value determined only by the error E is found.

This is called a syndrome, and once again S = (so, s+, --., -1 for Sn-)
(2-25) siR(α”') = E (α country)
(i=o11+・In−1) (2-26) Define. This syndrome contains all the information about the error (location and size of the error).

(Since the syndrome is 0 if there is no error, the presence or absence of an error can be detected.) Syndrome ((2-25).

Expression (2-26) is expressed as a matrix as follows.

S=HR” (R”: transposed matrix of R) (2-2
8) Step 2 In step 2 of f/e, the error locator polynomial and the error evaluation polynomial are calculated using the syndrome of the calculation result in step l. First, here, the number of non-zero elements of error E = (e,,el...el,), that is, the number of errors, is 1! (1≦t)too(.

Also, the position where the error occurs is ju (u=1゜2−=
1) (ju=o, 1-n-1), and the error at position ju is el. shall be. Furthermore, (2-2), (2-
3) Change the formula to n-=dmin-1=2t
(2-30). Then, the syndrome and syndrome polynomial of equation (2-26) are expressed as follows.

The following equation is obtained.

S (x) = [S-(x)] mod
x" (2-35) Now, the error location polynomial σ(X) is defined as follows. This polynomial is defined as the error location J u (u = 1 + 2S""'+
f ) (J u ” 0+1 +”...”n 1 )
It is a polynomial whose root is the element αK'' of GF(2'') corresponding to .

a (x) = (1-α”x) (1-αl2x)
・-(1-α”x) == IT (1-(!”X)U
f Next, the error evaluation polynomial ω(X) for σ(x) and 5-(x) described above is defined as follows.

Then, from equations (2-34), (2-35), and (2-37), the following equation holds true. .

a (x)・S (x) = [ω(x)] modx
” (2-38) Therefore, an appropriate polynomial A (
x) using σ(x), S(x).

The relationship of ω(x) is expressed as follows.

A (x)・x”+ a (x)・S (x) = ω(
x) (2-39) By the way, the number of errors l
Since (1≦t), ω(X) and σ(X) are deg (1) (X) < deg a (x)≦t
(2-40) is satisfied. Furthermore, since ω(X) steps (x) are relatively prime (the greatest common difference (GCD) polynomial is a constant) (2-39), ω(x) and a (x) that satisfy equation (2-40) are constant. Uniquely determined except for differences in coefficients. From the above, ω(x) and a (x) can be found through the process of Euclid's mutual division method to find the greatest common denominator (GCD) polynomial of X2' and S (x). Here, a method for calculating the greatest common difference (GCD) polynomial using Euclid's algorithm will be briefly described. First, let us represent the greatest common polynomial of two polynomials A and B as GCD [A, Bl. Also, for A and B, if the following polynomial λ and 100 degA≧degB, λ=A-[A-B-']-
B (2-41)B=B (2-4
2) *If degA≧degB, λ=A(2-43)B
= B-[B-A-']-A (2-44)(
[X-Y-']: quotient of polynomial
lt, satisfies the following formula.

GCD [A, Bl = GCD [λ, B]
(2-45) Therefore, the above-mentioned λ and n are rewritten as A and B, and according to the magnitude relationship of the respective orders degA and degB (2-41).

(2-42) or (2-43), (2-44
), and when either A or B becomes a zero polynomial, the other non-zero polynomial is obtained as the greatest common polynomial of A and B. In addition,
Finding the greatest common polynomial of polynomials A and B is no different from finding polynomials C and D as shown below. Note that deg refers to the order.

GCD, [A, I3 = C-A+D-B
(2-46) Then, the above repeating step is executed to form a polynomial A whose degree is expressed as i=degA≧degB.
In the process of finding the greatest common polynomial of

The problem of finding such a polynomial is called an extended GCD problem.

Therefore, the error locator polynomial σ(X) and the error evaluation polynomial ω(
X) is, in equation (2-47), polynomial A as X2',
It can be found by solving the extended GCD problem when polynomial B is set as S (x).

First, as mentioned above, the algorithm for deriving σ(X) and ω(X) can be reduced to an extended GCD problem. That is, X2
′ is a polynomial AO, syndrome polynomial S (x) ((2
-32) equation) as the polynomial BO (degAo=2
t.

degBo=2t-1), GCD [Ao, Bol is a polynomial that is satisfied during the calculation, and when W is found, D represents the error locator polynomial σ(X) and W represents the error evaluation polynomial ω(X), respectively. There is. It is known that such σ(x) and ω(X) are uniquely determined except for the difference in constant coefficients. Therefore, for AO and BO, the following polynomials A, B
, U, V, L, M and their initial values are U=M=1; L=V=0; (A=Ao, B=
Bo), repeat the steps in Figure 40, and when degA (degB) < t, A (B
) is found as ω(x), and L (M) is found as σ(X).

Note that in the method shown in Figure 40, the division on GF in the iterative step is omitted by multiplying A and H by the highest degree coefficient α of polynomial B and the highest degree coefficient β of polynomial A, respectively. . ((2-41).

(Refer to equation (2-74, 3)) Even if we do this, σ(X)
There is no essential problem with the values of and ω(X).

FIG. 40 will be explained. First, in step 1, U=M=1. L=V=O, A=Ao, B=Il
.

and set the initial value. In step 2, de
Determine gA>degB, and in step 3, multiply A and B by the highest order coefficients β and α of polynomials A and B, respectively, and use equations (2-41) and (2-43)
The division on GF in the repetition step is omitted.

If degA and degB become smaller than the predetermined order in step 4, proceed to step 5.6 and calculate ω(x
) = A, a (x) = L, (1) (x) =
B, (7(x) = M is calculated.

Note that in order to execute the iterative steps shown in FIG. 40, three execution modes are required depending on the orders of A and B, and these will be referred to as follows hereinafter.

i) degA, degB≧t and degA≧d
e g B ・-・“reduceA”ii) de
gA, degB≧t and degA≧d e g B-
・-“reduceB”1ii) degA<t or degB<t −, “nap” step 3
In step 3 of ``, the error position and error value are estimated from the error position polynomial σ(X) and error evaluation polynomial ω(X) obtained in step 2. , rl, -, rn-1) according to the symbol position i=0゜■...n-1)
2-) is successively assigned to the error locator polynomial σ(x). At this time, from equation (2-36), σ(a-') = 0
If i holds, then α1=α for the error position ju
It can be seen that -1u is established. (ju=0.1・
・-n-1, u=1.2・1. 1≦t) Furthermore, the value of the error evaluation polynomial ω(X) for such α−1=α−h is as follows.

Furthermore, if σ'(X) is the differential of σ(X), then the following holds true. Therefore, from equations (2-48) and (2-49), the error value e at position iju can be obtained from the following equation.

As mentioned above, in step 3) of decoding, step 2
GF(2”) whose R3 code is defined by three polynomials: the error locator polynomial σ(X) obtained from ), the error evaluation polynomial ω(X), and the differential σ′(X) of σ(x) It is necessary to calculate the value by sequentially substituting the element a-' (j=n-1, .multidot.2, 1.0). (Here, the received symbols are input from the higher-order terms of the received word polynomial. That is, it is assumed that rj is input in the order of j=n-1, ..., 2, 1.0. Therefore, step 3 ), it must be noted that the order of substitution for α4 (j=n-1, . . . , 2, 1.0) is reversed. ) You can use the same algorithm as Oni. For example, the degree polynomial 2f
The calculation of (x) is developed as follows.

f (x) = ftx' 10 ft lx' ” '
10...-+flx +f6,;
;= Loe = i-[(ftx+ft-1) x+ft-
2) x+-+f+l xffo #=;b However, in the syndrome calculation, each cell has a value of X to be substituted in advance, and a coefficient is given to each cell before step 4;
- From equation (2-9), the received symbol r at the position ju where the error occurs is expressed as follows from the symbol f2 of the original code word and the error size e2.

b+='=eh (2-5
1) Therefore, in step 4, the execution result σ(
Position i where α120 is established (i=0,1...n
−1), subtract from received symbol rl < (on GF(2'″)) f+=rt e
t (253) performs error correction at position i.

(Syndrome Generation Unit) Next, the configuration and operation of the BCH encoder/decoder according to the embodiment of the present invention will be described in detail for each configuration unit.

In step l, the received sequence R=
From (rn-1, rn-2...-, x, ro), the coefficients of the syndrome polynomial required in step 2 (S 21-1
, S21-2...

St, So) must be output serially.

The following iterative algorithm is used to specifically calculate the coefficients of the syndrome polynomial.

S+1==(・'-((r, l-, "α' + , ll
-, ) * (X' + rn-4) * (1' + ”・
+ rl) *α' + r.

Also, the above equation can be decomposed as follows.

z, =O Zt =Z+-+ *α' ten re-+
(i=1.-, n) St-+ = Zll In order to miniaturize the circuit, 3 multipliers and 5 registers which are meaningless in the PE of FIG. 41 are removed. As a result, the calculation section of the PE has 400 gates. Here, the 42nd
Paying attention to the movement of the received symbols in the figure, one received symbol rn-+ does not change its value (from PE #l to #2
It is sent to the PE of t, is added, and only the term gZ+-+*αj changes. Therefore, in the previous chapter, the PE of the syndrome generation unit was assigned to each αI (j=1f..., 2t), but here, from the αl input to α'(j=1°..., 2t)
The values of t) are input sequentially, and the input of α' (j=1..., m) is repeated periodically, with one cycle being from j=1 to m. And r, which is the input of the received sequence,
allows the received symbols rn-i (1=le...r n ) to be input while the value of one received symbol is held for one period. As a result, register 7 can also be omitted, and 11 manual inputs are directly input to the adder. However, the register 6 needs to store the calculation result of ZI for one cycle from PE #l to PE #m, so m stages are required. FIG. 3 shows the signal flow when m=2t.

At first (i=1), selector selection signal Sl, 2 is r
St, 2 = 10 only when n-1 is input, and O, which is the C input, is output from the X output, and Z (=rn-+ is the calculation result when i = 1 It is input to the register sequentially. After that (i=2...+n)
, St.

2;00, the X output of the selector selects the A input, and Zl-1, which is the result of the previous calculation, is sequentially output from the X output, and α'(J"11...
・, 2t) and added to r n-+, resulting in Z+=Z+-+* α'+ rn-1(j=l,
-, 2i) are calculated and sequentially input into the register. Therefore, the 2nd stage register is St-+(j=1...,
This is a memory section for temporarily storing the intermediate results of the calculations in step 2t) and feeding them back again. As a result, the processing of 2 PEs can be realized with one PE, but since it is necessary to hold the input r n-1 for the number of register stages, the processing speed becomes (16/2t) Mwps.

Here, in order to miniaturize the circuit, the multiplier 3 is removed and the register rows 5 and 7 are also omitted. Therefore, the circuit scale of the PE shown in FIG. 2 is (400+m*50) gates, and the processing speed is (16/m) Mwps. m is the number of register stages, and when all processing is performed by IPE, m=2t. As an example, if the correction capacity t = 8, the IPH circuit scale will be 120 gates, and the processing speed will be l M h
z = 8 Mbps.

Further, when all processing is not configured by IPE but divided into a plurality of PE', the PEs shown in FIG. 2 are connected as shown in FIG. 4. At this time, a register controlled by CK2 (clock per cycle) is required to delay the received symbol at a rate of one cycle for each IPE. If the number of PEs is k, the overall processing is distributed over (2t/k), so the number of register stages required for IPH is m=(2t/k). Therefore, the circuit scale in Fig. 4 is (2t/m)* (400+m*
50) Becomes a gate. FIG. 5 shows the signal flow when configured with two PEs.

In this case, the allocation of αj is such that PE #l is αI(j=1.・
....

t), PE of #2 is α' (j=t+1...., 2t
).

In this case, the number of register stages m = t, so the processing speed is 2 Mhz = 16 Mbps,
The circuit scale is 800*2=1600 gates.

When m = 1, the number of PEs required is 2t, and CK2 = CK, so the register controlled by CK2 is equivalent to register 7, and the processing speed is 16Mwps.
becomes. Therefore, this has a configuration in which unnecessary circuits shown in FIG. 42 are omitted. Also, by utilizing the fact that the B input of the selector is active, by inputting the S (x) output of the previous PE, the coefficients of the syndrome polynomial (S 2L-11821-21=・* S + +
S o ) can be serially output as S'(x).

The algorithm for deriving the error locator polynomial σ(X) and the error value polynomial ω(X) in step 2 can be reduced to the extended GCD problem. Fourth
In the circuit shown in Figure 3, each PE has one Process
When the s processing is completed, the output is passed to the next PE, and the PE itself receives the next input and performs the Process processing 21 times.

The second Process processing result is not output to the next PH and is stored in its own register using the syndrome polynomial S (
After completing one series of inputs of x) and

The configuration of PE at that time is shown in FIG. As in Fig. 43, a circuit for setting 5tate, a register controlled by CK2 and CL for holding α and β, and al-1°b+
In order to realize -+, it is necessary to insert one more stage of registers after register rows 5 and 7. Therefore, when the number of register stages in the PE is m, the required circuit size in the PE (the State setting circuit is the control section, so the division () is (700 + (3m + 4) * 50) gates. (700 is The circuit scale of the calculation section is (3m+4
) is the total number of registers) When all processing is performed with one PE, m = 2t (because the degree of the polynomial of the processing result is not greater than 2), and for the example shown in Figure 40, A (B ) is shown in FIG. 7, and FIG. 8 shows the beginning of the signal flow in the case of finding L (M). The switching of the selector selection signal and the control of CK2 are performed every (m + 1) basic clock CK, taking into consideration the inserted register, so that the operations shown in FIGS. 44 and 45 are sequentially performed in one P.
It can be seen that this is done in E.

Note that, when calculating A (B) and when calculating L (M), it is necessary to have two independent Process sections or use one Process section twice. Below, we will evaluate one Process process.
If used twice, reduce the processing speed by half and use two Processes.
If the ss section is provided independently, the number of required PHs may be doubled.

Here, the syndrome polynomial S (x) (or M
= 1) and x2I (or L20) input only selector selection signal Sl, 2 = 11 to X, Y output.

Use a selector that outputs the E input. (The combinations of selector outputs are shown in the table.) When A (B) and L (M) are processed by one Process section, using the PE shown in FIG. 9, 31. ．． By controlling 4, A=x'', B=S (x), L=O, M=1
You can also input. (The combinations of selector selection signals are shown in the table.) However, since the PE @2t+2 in Figure 43 has meaning only in signal selection by the selector, the PE in Figure 9
Using the W output of E, the number of processing times by PE is set to 2t+1 times. (Also, in the PE shown in Figure 6, by providing a separate selector, the number of processing circuits is reduced to 2t+1 times.
The signal selection at t+2 is determined by setting 54=1 when degB<t. Therefore, the processing speed here is as follows: The processing shown in FIG. 43 is performed every m register stages (16/ 2t/m) M
l p s. As an example, if t=8 and m=2
When t is the circuit scale, the circuit scale is 3300 gates, and the processing speed is 1/16M1ps=n/16Mwps.

Furthermore, when all processing is not configured by IPE but divided into a plurality of PHs, the PEs shown in FIG. 6 are connected as shown in FIG. 11. At this time, in order to operate while circulating the coefficient data in each PE, it is necessary to feed back the output of the last PH to the first PE. If the number of PHs is k, the entire processing is distributed over (2t/k), so the number of register stages required for IPE is m=(2t/k). Therefore, the circuit scale in Fig. 11 is (2t/m)* (700+
(3m+4)*50) gate.

FIG. 12 shows the signal flow when configured with two PEs. In this case, since the number of register stages m=t, the processing speed is 2/16 M 1 ps, and the circuit scale is 1950)k2=3900 gates.

When m = 1, the number of required PHs is 2t, and the processing speed is 16 M l ps. In this configuration, feedback is performed from the last PE to the first PE, so the number of PEs is only 2t for the number of processing times of 2t+1.

If the number of PEs is set to 2t+1 in correspondence with the number of processing times in order to establish a systolic connection, there will be no need to feed back signals, resulting in the same configuration as in FIG. 43. (In this case, PE #2t+2 becomes a selector.) f Step 3 can also use the following iterative algorithm and decomposition formula as in Step 1.

f = (x) = f t-+ * x'-' 10r l-2* x'-" = 10f + * x +
f a= (・-((ft-+*x+ft-2)*x
+ft-3) *x-1-+f+) *x+fo) Zo=O Z+=Z+-+*x+ft-+ (j=1...,
1) f(x)=Zt Also, in order to miniaturize the circuit, the multiplier 3 and register 5 are removed as in step 1. Also, in the circuit shown in Figure 46, the input α-' (i=n-1,..., 0) is simply sent from the PE #l to the PE #t without changing the value, as in step l. be. Therefore, α' is set so that one value of α-1 is held from j = 1 to
Input (i=n-1,...,o).

Also, as in step 1, the coefficient of ft-1 is
The inputs t-+ (J = 1, . . . + m) must be repeated. Considering the output from the GCD generator in step 2, the coefficient F + - t (j = 1.
. . , 1) is output once, but not periodically and repeatedly. Therefore, a PE is configured as shown in FIG. 13 using selectors output in combinations as shown in the table according to the selection signals Sl, 2 and an m-stage register array 7, and signals are sent as shown in FIG. 14. The coefficient ft-+(j=
1. ....

t) is output, the selector selection signal is set to Sl.

2=11 (given when ft-+ is input) to S
t.

By setting 2=O1, the coefficient ft-1 is obtained from the Y output.
(j=1...., 1) are output sequentially, and the register row 7
is input.

The output is fed back to the B input to select the selector,
By changing the signal from Sl, 2=IO (only when ft-+ is input) to Sl, 2=OO, the coefficient fr-i (J=',..., 1) is again calculated from the Y output. The signal is output and input to the register column 7. Thereafter, by repeating this operation, the coefficient rt-+(J=1....,1)
periodic input is realized. This allows step 1
Similarly, the processing of m PHs can be realized by one PE, but since it is necessary to hold the input α-1 for the number of register stages, the processing speed becomes (16/m) M w p s. (m is the number of register stages) Also, the circuit scale required for IPE is (400+ (m+1)
*50) Becomes a gate.

m is the number of register stages, and when all processing is performed by IPE, m==t. However, ω(X), σ(X).

Three sets of PEs are required to process σ'(X).

As an example, if the correction capacity t=8, the circuit scale is 3*
850 = 2550 gates, processing speed is 2 Mw
It becomes ps.

Further, when all processing is not configured by IPE but divided into a plurality of PEs, the PEs shown in FIG. 13 are connected as shown in FIG. 15. At this time, a register controlled by CK2 (clock for each cycle) is required to delay α-1 by one cycle for each IPE.

If the number of PEs is k, the entire processing is distributed over (t/k), so the number of register stages required for IPE is m = (t/k).
). Therefore, the circuit scale in Fig. 15 is (t/m)*
It becomes a (400+ (m+1)*50) gate. 1st
Figure 6 shows the signal flow when configured with two PEs.

In this case, since t=8, m=(t/2)=4, the circuit scale is 3*2*650=3900 gates, and the processing speed is 4 Mw ps.

When m = 1, the number of PEs required is = t, and CK
Since 2=CK, the register controlled by CK2 is equivalent to register 5, and the allocation of f t-+ has the same configuration as in Fig. 46 except for the part, and the processing speed is also l 6 M.
It becomes w p s.

Also, in Figure 17, σ(X) and σ'(X) are combined into one PR.
In the case of processing with PE, FIG. 18 shows the signal flow. Step 3 utilizes the fact that since one period is t, IPE can be used twice, and that the coefficient of σ'(X) is the coefficient of σ(X·). As a result, Step 3 can be realized with two sets of PEs, and as shown in Fig. 18, the operations of σ(X) and σ'(X) are every 2, and ω(x)
By making the output as shown in FIG. 19, it is possible to operate 2 every time.

Here, a selector whose output combinations are as shown in the table is used, and the selector selection signal is set to 51. only when the Y output becomes 0.
．． 3=OO1. In this case, the processing speed is 2M
wps/2 = IMwps, and the required set of PEs is also 2 sets, so the circuit scale is 2 * 850 = 170
It becomes 0 gate.

ゞ EroHere, we will explain the S required to perform erasure correction in response to the coefficient output S (x) of the syndrome polynomial from step l.
(x) *Generate λ(X').

First, consider generating the vanishing position polynomial λ(X).

λ(x) = (1-Y+*x)*(1-Y2*x)-(
1-Ys*x), and similarly to the previous chapter, λ(X) is decomposed as follows.

Zo=1 Z+= (1-Y+*x)*Z+-+==Y+*Z+
−1 *x+Zt−+ (i=1.−, s)λ (x)
=25 First, in order to miniaturize the circuit, multiplier 3 and register 6 are
Sharpen. Here, it is made to correspond to the number of processing clocks or the number of register stages. Also, one register is prepared for delaying the Zl-+ input by one clock. Therefore, the PE configuration is as shown in Figure 22, and the circuit scale required for IPH is (40
0+(m+1)*50) gate. (m is the number of register stages) FIG. 23 shows the signal flow.

Number of register stages m in IPE (here m = 2t)
Y+ so that one value of Y is held for one period.
Input (i=1...ts). First, (at the time of Y+ input) the selector selection signal is S1, 2=11, the D input Zo=1 is input to X, the C input 0 is input to Y, and the operation result Y1 is input to the register column 6 at the next clock. Hereafter, Sl, 2
= IO as Xi:C input oSYl, :Outputs A human power which delayed Zo by 1 clock, and calculates the calculation result Zo = 1 as follows,
Input to register column 6 using the clock. Since the calculation result is 0 from the next clock onwards, 0 is manually entered into the register column 6. After one cycle (when Y2 is manually operated), the pre-calculation result Z+=Y+*x+1 (order X represents the order of the signals) is output from the register row 6, so Sl.

2=O1, the highest order coefficient Yl of the previous operation result is outputted to X from the A input, O of the C input is outputted to Y, and the operation result Y1*Y2 is inputted to the register column 6 at the next clock.

Hereafter, with Sl, 2 = 00, the next coefficient 1 of Zl is input to X from 6 inputs, and the highest order coefficient Y of Zl delayed by 1 clock to Y
1 is selected from the B input, and the operation result Y + + Y 2 is input to the register column 6 at the next clock. At this time, 0 is output from X, and the coefficient 1 next to Zl is output from Y. At the next clock, the calculation result 1 is input to the register array 6, and since the calculation result is 0, 0 is input thereafter.

By repeating the operation during Y2 manual power after Y3 manual power, λ(x) is outputted from the register row 6 from the higher-order coefficient after Y5 manual power.

Since S≦2t, Y+=0 (i=s+ 1.-.
2t).

Therefore, the processing speed is (16/2t/m) Mlps h
Become. As an example, if t=8 and all processing is performed by IPE, the circuit scale will be 1250 gates and the processing speed will be 1/16 M I ps.

Furthermore, when all processing is not configured by IPE but divided into a plurality of PEs, the PEs shown in FIG. 22 are connected as shown in FIG. 24. At this time, in order to hold the value of Y for 2t clocks, a register for setting Yl is required for each PE.

If the number of PEs is k, the entire processing is distributed over (2t/k), so the number of register stages required for IPH is m = (2t/k).
/k). Therefore, the circuit scale in Fig. 24 is (2t/
m) * (400+ (m+1)*50) gate. FIG. 25 shows the signal flow when configured with two PEs. The circuit scale at this time is 850*2=1700 gates, and the processing speed is 2/16 M 1 ps.

When m=1, the number of PEs required is 2t, and the processing speed is (16/2t) M 1 ps, which is equivalent to the configuration shown in FIG. 47.

Next, consider the multiplication circuit S (x) *λ(X). The calculation of multiplication C,'(X) =A (x) *B (x) is decomposed as follows in the same way as in the previous chapter.

A(x) = am-1*X"-'+am-2*X"-"
+"'+al*X+aO, then C(x) = am-1* B(x)* x--' +
am-2* B(x)* x"-2+ -+a+*B
(x)*x+aoB(x), so Zo=O Z+=Z+-+*x+B(x)*am-+ (j=1
．． =-, m) C(x) = Z m Therefore, while B (x) is input, hold a□-1 and after calculating Z+ = Z + - + *x + B (x) *am-+ register It is sufficient to insert it into column 6 and feed back the calculation result as Z+-1 after one cycle. However, the inputs S (x) and λ<x> are only input once from the syndrome generating section in step l and the above-mentioned error locator polynomial generating section at the transfer rate of the basic clock CK. Therefore, register arrays 5 and 7 are used to realize repeated input, and a register controlled by CK2 is used to hold set values. Furthermore, since the B(x) output from register row 7 needs to be fed back one clock later than the Z+-+ output from register row 6, the configuration of PE is as shown in FIG. 26. B (x) = S (x).

am-i"λzt-+ (i = 0, -, 2 t
) is shown in FIG. 27. (IP
(The number of register stages in E is m −1 = 2 t −1.) First, as the selector selection signal Sl, 2 = 01, λ(x)
is input to the register column 5 from the F input through the W output.

At that time, the highest order coefficient λ2t of λ(x) is stored in a register controlled by CK 2 and set to the input of the multiplier 3. Further, S (x) is delayed by one clock from λ(X), inputted to E, outputted to Y, and inputted to the register array 7. Meanwhile, X outputs C input 0.

As a result, λ2. *5(x) is calculated and input to register column 6. At this time, since the highest order coefficient λ21 * S 2t-+ of λ(X) *S (X) has been calculated, it is latched by CKD and output. One period is m(
Here, it is assumed that m = 2 t ), and the selector selection signal Sl, 2 = OO after one cycle. From B, 5(x) fed back by the m-stage register row 7 is input, and again from Y, it is input to the register row 7. From D, λ(X
) is fed back and output to W.

Therefore, in CK 2, the coefficient λ21-1 next to λ(X) is stored and set in the multiplier 3. From A, the shifted highest order coefficient of all the calculation results is fed back by the m-1 stage register array 6, and is input to B (x) = S (x) in the form of a shifted first order coefficient. With this, Z
+=Z+-+*x+B (x) *am-i is calculated and input to the register column 6. Thereafter, λ0 is input to CK2, and calculations are performed in the same manner until the calculations are completed. However, since the calculation result that becomes the answer shifts when fed back to the input, it is output by CKD every time the calculation is performed. Furthermore, the coefficient of λ(x) also shifts when fed back to the input, so the coefficient decreases by one order. Since the shifted coefficient is not necessary, when it is fed back, by setting the selector selection signal to St, 2=IO,
Outputs O to IW.

Furthermore, since the result of the answer operation remains in the register column 6 after the operation is completed, by repeating the same operation, the result in the register column 6 is shifted by one coefficient and output from CKD.

The circuit scale required for IPH is the number of register stages in PE as m-
1, it becomes (400+3m*50) gates).

Further, the processing speed is (16/4t/m)/2 because it is necessary to consider the period from the end of calculation to the end of output.

When all processing is performed by IPE, the number of register stages in PE is m = 2
As an example, if the correction capacity is t = 8, the circuit scale will be 2800 gates and the processing speed will be (1/32).
Becomes Mlps.

Further, when all processing is not configured by IPE but divided into a plurality of PEs, the PEs shown in FIG. 26 are connected as shown in FIG. 28. At this time, in order to hold the value of am-+ for 2t clocks, a register for setting am-+ is required for each PE. If the number of PEs is k, the overall processing is (2t/k
), the number of register stages required for IPH is m
=(2t/k). Therefore, the circuit scale in FIG. 28 is (2t/m)*(400+3m*50) gates. FIG. 29 shows the flow of signals when configured with two PEs. Circuit scale at this time 1600*2=3200
gate, and the processing speed is (1/16) M I p s
becomes.

When m=1, the number of required PHs is 2t, and the processing speed is also (1/2) Mlps.

U encoding is information I (x) = (Ik-+, -2 in summer,
−, I o ) to parity P (x ) = (P
2 t , P 21-1 , ..., Pl). Encoding means generating polynomial g (X) = g m * X-+ g m-1 *
X111-' 10g m-2* XIN'...10g
1* x + g.

Then, P (x) = I (x) *xl+mod g (
x), g' (x) :gm-1*x'''-'10gm-2*x
”-...+g+ *x 10g.

Then This equation can be decomposed as follows.

Zo=l(x) Z+=gm *z' i-1+2m *g' (X)
(+= L”'+k)P(x)=Zk Here, 2□ is the highest order coefficient of polynomial Z1-1, and Z"+
-1 is a polynomial obtained by removing the highest order coefficient from Z, -1.

Hold Zm while inputting g' (x), z m * g'
(x) is calculated. Here, g m = 1 and the PE is configured as shown in FIG. 30.

g, to the coefficient gm-1 of g' (x) so that go makes m 1
The signal is periodically input to the multiplier 2 as a period. Also CK2
ZIT+ is held by a register controlled by (clock for each cycle) and CL, and is input to A.

Z' +-1 is realized by outputting the pre-operation result Z+-+ one clock earlier than the period. Therefore, the number of stages of the register array 6 is set to m-1 and is fed back to the B input. Information 1 (x ) is input from C and is 1 for one period.
input so that one value is retained.

FIG. 31 shows the encoding process. First, consider the case when i=1. As an initial state, the information symbol Ik-1 is held in the register controlled by CK2, and the information symbol Ik-1 is held from the C input.
Let us consider the case where k-□-1 is input and information symbols from Ik, z to Ik-□ are stored in the register column 6.

The arithmetic unit multiplies Ik-+ from the A input by g' (x) and calculates 1. Ik-+ to Ik-□ from the B input and Ik-m-+ from the C input are added and input to the register column 6.

(Switching between B and C inputs for Y output is performed by selector selection signals Sl and 2, and when B input is selected, Sl.

When 2 = OOSC input, Sl, 2 = 01) The calculation result is calculated from the 21 higher-order terms as I' k-+ = I k-
+ *g m−i + I k−i−1. (j
= 1, -, m) After i = 2, encoding is performed by performing the same processing for 11 until i = k.

Further, in order to realize the initial state, it is as shown in FIG. 32 (in the case of m=4). Information is input so that one cycle of open chain is maintained from Ik-+ to IO. First, the selector selection signal Sl,2=01, and the first received symbol I
Input k-1 from C and output to Y. CK2 to A input
0 is input by CL of the register controlled by , and output is made to X. Since the number of register stages in the PE is m-1, Ik-+ is fed back to the B input one clock cycle before. At that time Sl.

2 = 00, output the B input to Y for 72 minutes of Sl
, restore the settings in step 2. At this time, the next received symbol Ii+-2 is input from C, so register column 6 contains ■,
After inputting -1 for one clock, I k-2 is manually input. I k-2 manual input from register row 6
Since the deviation from the feedback input is two clocks, the selector selection signal is set to St,2=00 accordingly. At that time, Ik-2 is selected by one lock after Ik-+. By proceeding with the above operation Ik-□, 1 to 1 to Ih-m are stored in the register column 6. When inputting Ib-m'-+, Ib-+ protrudes from the register array 6, but is latched into the register controlled by CR2, thereby achieving an initial state.

Also, information I (x) and parity P (x
) is also performed as shown in FIG. 33 using the Z output of the selector. During the above-mentioned encoding operation, 2 inputs and outputs C' which is an input of information symbols for each period. After the operation is completed, the parity output is circulated through the register row 6.
Since the number of register stages in PE is m -1, the register controlled by CR2 outputs parity shifted by one order for each cycle of parity and feeds back to the A input. At that time, Z selects the input to and outputs parity every cycle.

Therefore, the circuit scale and processing speed at this time are (400
+m * 50) gates, and (16/m) Mwps. When all processing is configured with IPE, m = 2 t
becomes. As an example, if the correction ability t=8, IPE
The circuit scale is 1200 gates, and the processing speed is IM
w p s = 8 M b p s.

Furthermore, when all processing is not configured by IPE but divided into a plurality of PEs, the PEs shown in FIG. 30 are connected as shown in FIG. 34. If the number of PEs is k, the total processing is (2t/k)
Therefore, the number of register stages required for IPE is m
=(2t/k). Therefore, the circuit scale in Fig. 34 is (2t/m) * (400 + m * 50
) becomes a gate. FIG. 35 shows the signal flow when configured with two PEs. In this case, the number of register stages is m =
t, so the processing speed is 2 M w p s = 1
6 Mbps, and the circuit scale is 800*2=1
There will be 600 gates.

When m == 1, the number of PEs required is = 2t, but the feedback from PE # to PE #l,
Since the simultaneous inputs of and 1 (x) remain unchanged, the encoder is still not systolic in this architecture.

;:'-1 and the 1 (α-°) output of system step 3 are output by IcK every 2 when using the PE shown in Fig. 17, but σ'(α-°)
1) Since the timing is shifted by half a cycle at jump (α-1) and ω (α-I), σ'(α-') is latched by a register controlled by CR2 (2 is every clock), and σ (α -1
).

By latching ω(α-I) with CK2' (a clock shifted by half a cycle from CR2) and further latching it with a register controlled by CR2, error correction in step 4 similar to that shown in FIG. 48 is realized. (The timing is shown in FIG. 21. However, in the GCD generation section, A (B).

(If one Process unit is used twice to process L(M), the coefficients of ω(x) are sent first, so they must be passed through a buffer). After optimization, the result will be as shown in Fig. 20.

ω(α-1), σ(α-ri, σ'(α) The operation after adjusting the timing of one output is the same as in the previous chapter. Therefore, the circuit size required in step 4 is the buffer and reciprocal. Excluding the generation ROM, there are 450 + 5 * 50 = 700 gates.The error correction execution unit in step 4 does not have a systolic structure, so the circuit cannot be made smaller even if the number of register stages is increased. .

Therefore, it is only necessary to simplify the circuit optimally depending on the situation. The same applies to the α-' (i=n-1, . . . , O) generation circuit.

As described above, each decoding ladder of the R5 code can reduce the size of the circuit in exchange for high speed.

As an example, in the decoder of FIG. 49, the control of each PE is controlled by the selector selection signal and the CR2
You can run the entire system with just one.

Step 1) SYNDROME: Figure 62 Step 2)
GCD: Figure 69 Step 3) EVALUAT
EC Figure 77 Step 4) CORRECT: When considering the encoder/decoder in Figure 80 as a system, taking the decoder for erasure error correction in Figure 50 as an example, it can be miniaturized by making the following combinations. It can be implemented as an encoder/decoder.

1) SYNDROME: Figure 622) GCD
: Figure 69 3) EVALUATE : Figure 774) CORRE
CT: Figure 80 5) ERASURE I: Figure 826) ERAS
URE II: In FIG. 8, ERASURE ■ and ERASURE II are added to the decoder shown in step 4. Furthermore, the encoder shown in FIG. 30 can be added to the decoder shown in step 4 to form a coding decoder. (If encoding and decoding are not performed simultaneously, PH
By making the connection of As mentioned above, the processing speed (in M w ps) is as follows. (wps=word/5ec)1) (2t
/m)*(4(10+m+50), 16/m2) (
2t/m) * (700+ (3m+4) +50),
n*(16/2t/m)3) 2*(2t/m)*(
400+(m+1) +50), 16/m5) (
2t/m)*(400+(m+1)+50), n*(1
6/2t/m)6) (2t/m) * (400*
(3m+2) +50), n* (16/4t)
/m)7) ENCODE:Figure 89; (2t
/m)*(4004m+50), 16/m1 As an example, when the R3 decoder assumes t=8, it can be realized with the following circuit scale and processing speed. (Code length n≧4t, and m=2t to implement with IPE) 1200 + 3300 + 2500 + 700
= 7700 gatel M w p s = 8
M b p s and when t=2, 600 + 1500 + 1300 + 700 +
3100gate4 M w p s = 32 M
If the circuit scale of b p s (2”) is M gate,
The circuit scale of GF(2') is approximately 4M gates. However, considering that the structure of one word is from m bits to 2m bits, the processing speed per IPE is 10 to 20 M bits.
Since w p s (word 7 seconds), m-, (10~2
0) Mbps becomes 2m·(lO~20) Mbps, doubling.

The number of stages may be two. Then, the number of PEs required is
Since k=(2t/m) and m=2, there are t pieces. Therefore, we can change the structure of the Galois field from GF(2M) to GF(22M).
In this case, the circuit scale increases twice at the same processing speed. Generally speaking, the structure of the Galois field is from GF(2″′) to G
When F (2°-'''), the increase in circuit scale is a times.

〔Effect of the invention〕

As explained above, the PE used in the previous R3 encoding decoder
We demonstrated an architecture that can reduce the circuit scale by simply increasing the number of register stages.

As a result, the circuit scale (gate unit) and processing speed (1
Mwps unit) can be expressed functionally by the correction capability t and the number of register stages m, and any processing power and processing speed can be achieved with a realizable circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a miniaturized processing element (PE) according to the present invention. FIG. 2 is an explanatory diagram of a syndrome generation circuit that optimizes the PE of FIG. 1 according to the present invention. FIG. 3 is a diagram showing a second diagram according to the present invention. PE timing diagram 4th
5 is a timing diagram of a syndrome generation circuit using two PEs shown in FIG. 2 according to the present invention. FIG. 6 is a diagram using the PEs shown in FIG. 1 according to the present invention. 7 is a timing diagram of a GCD generation circuit using the PE shown in FIG. 1 according to the present invention. FIG. 8 is a timing diagram of a GCD generation circuit using the PE shown in FIG. 1 according to the present invention. FIG. 9 is an explanatory diagram of a GCD generation circuit using the PE of FIG. 1 according to the present invention. FIG. 10 is an input timing diagram of FIG. 9. FIG. 11 is a GC using the PE of FIG. 1 according to the present invention.
FIG. 12 is an explanatory diagram of the D generation circuit.
13 is a timing diagram of the CD generation circuit. FIG. 13 is an explanatory diagram of an error evaluation circuit that optimizes the PE of FIG. 1 according to the present invention. FIG. 14 is a timing diagram of the PE of FIG. 13 according to the present invention. FIG. 15 is according to the present invention. PH connection diagram No. 16 in Fig. 13
The figure is a timing diagram when two PEs shown in FIG. 13 according to the present invention are used. FIG. 17 is an explanatory diagram of an error evaluation circuit that optimizes the PE shown in FIG. 13 according to the present invention. Timing diagram No. 19 in Figure
20 is an optimized error correction execution unit according to the present invention. FIG. 21 is a timing diagram of FIG. 20 according to the present invention. FIG. 22 is a timing diagram of FIG. 1 according to the present invention. An explanatory diagram of a vanishing one-position polynomial generation circuit with optimized PE. FIG. 23 is a timing diagram of the PE of FIG. 22 according to the present invention. FIG. 24 is a connection diagram of the PE of FIG. 22 according to the present invention.
The figure is a timing diagram when two PEs shown in FIG. 22 are used according to the present invention. FIG. 26 is an explanatory diagram of a multiplication circuit that is an optimized PE of FIG. 28 is a PH timing diagram of FIG. 26 according to the present invention, and FIG. 29 is a PH timing diagram of FIG.
The figure is a timing diagram when two PEs shown in FIG. 26 are used according to the present invention. FIG. 30 is an explanatory diagram of an encoder that optimizes the PE shown in FIG. 1 according to the present invention. Fig. 32 is a timing diagram of the PE of Fig. 30 according to the present invention (during initial input) Fig. 33 is a timing diagram of the PH of Fig. 30 according to the present invention (during numerical output) Figure 34 is a connection diagram of the PH of Figure 30 according to the present invention.
The figure is a timing diagram when two PEs according to the present invention are used. Figure 36 is a conventional processing element (PE).
Figure 37 shows the conventional processing element (PE).
Figure 38 shows the configuration of the selector of the conventional processing element (PE).
Figure 39 is a block diagram of the multiplier of the conventional processing element (PE).
Figure 40 is a diagram for explaining the algorithm for determining GCD. Figure 41 is a diagram for explaining the conventional PE for syndrome generation. Figure 42 is the connection of the conventional PH for syndrome generation. Figure 4
Figure 3 is a connection diagram of a conventional GCD'CD PE; Figure 44 is a diagram showing the operation timing of a conventional GCD generation PE; Figure 45 is a diagram showing the operation timing of a conventional GCD generation PE; and Figure 46 is a diagram showing the operation timing of a conventional GCD generation PE. FIG. 47 is a connection diagram of a conventional PH for error evaluation. FIG. 48 is a diagram for explaining a conventional PE for error correction. FIG. 49 is a diagram for explaining a conventional error correction PE. Figure 50 is a diagram illustrating the configuration of a decoder system. Figure 50 shows an example of an erasure error correction decoder.
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... Adder patent applicant Canon Co., Ltd. No. 22 G to 1 1 +-11+ 1 +- Figure 6 C11 Male IO diagram 1 \ \ Kudzu o9 C to 11 aJ-) --- 11 ・-- Figure 21 ~ Kura ma ko = ° sa

Yiman 4q diagram

Claims (1)

[Claims] (1) A multiplier on a Galois field that has a multiple-input multiple-output or multiple-input-output selector and at least one of its selector outputs as inputs, and an addition on a Galois field that has at least one input as the output of the multiplier The polynomial A
, B, a GCD generation circuit that obtains the greatest common denominator polynomial GCD[A,B].