JPS63164627A - Missing location polynomial generating circuit - Google Patents

Abstract

PURPOSE:To attain large scale circuit integration with small sized hardware capacity by connecting plural number of identical arithmetic circuits each consisting of a multiplier on Galois field, an adder and m-set of register arrays storing its addition output and selector output so as to obtain the multiplication of a specific missing location polynomial and polynomials Ax, Bx. CONSTITUTION:The missing location polynomial lambdax is generated by equation I. At first, a selector section signal is set as S1,2=11 at first at the input of Y1, D input Z0=1 is inputted to X, a C input 0 is inputted to Y and the Y1 being the result of arithmetic operation is inputted to a register string 6. The with the relation of S1, 2=10, the C input 0 is outputted to X, the A input retarding the Z0 by one clock is outputted to Y and the result of arithmetic operation, Z0=1 is inputted to the register array 6 by the next clock. Since the result of operation is 0 on and after the enxt clock, 0 is inputted to the register array 6. After one period, the result of preceding arithmetic operation Z1=Y1*x+1 is outputted from the register array 6. The operation at the input of Y2 is repeated even after the input of Y3 to output the lambdax from the register array 6 from the high order coefficient after the input of Y5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of error correction, and also relates to a technique for performing parallel processing in signal processing targeting communication channels.

The present invention relates to a technique for performing erasure error correction in encoding and decoding BCH codes.

[Prior art and its problems]

In recent years, the application of error detection and error correction codes (hereinafter simply referred to as error correction codes) has become widespread as a measure to improve the reliability of various digital systems including memory systems.

There are various types of error correction codes depending on the target system, but the most typical one is a class of linear codes called cyclic codes.

For this, a BCH code suitable for random error correction is used.

Fire code suitable for burst error correction, and BCH
Reed- is a type of code and is suitable for byte error correction.
3olomon code (hereinafter referred to as R3 code). Among them, the R3 code has the lowest redundancy among linear codes with the same code length and correction ability, and is a very important code in practice. It is widely used in disk drives (hereinafter referred to as CDs), etc.

There are various decoding methods for this R3 code.
It is relatively easy to implement a decoder for a small degree of correction capability. However, in order to obtain high reliability, it is necessary to increase the correction ability.

In that case, problems arise in that the scale and control of the device becomes extremely complex, and the calculation time required for decoding processing also increases. For this reason, CDs currently use a type of double encoding called CIRC, but this poses a problem in systems that require higher reliability or higher speed. In addition, in order to obtain high reliability, magneto-optical disks use Long Di
A multiple error correction code called a stance code (hereinafter referred to as LDC) has been proposed, but the problem is how to achieve high speed.

Satellite communications require two things: high reliability and high speed, but when considering the development of equipment, it has been extremely difficult to satisfy the above two conditions.

Therefore, by taking advantage of the features of the rBCH encoding/decoding system (filed on December 22, 1986) t'1tVLsI architecture, which the present applicant had previously applied for, the following was achieved.

■) High reliability (large capacity) 2) High speed 3) Regularity of internal structure 4) Large integration As a result, 10-20Mwps = 80-1610-
We have shown that it is possible to realize an R8 encoder/decoder with a processing speed of 20 or more. Also, for the correction ability, P of the same configuration
By increasing E in a linear manner, the configuration is such that arbitrary high reliability can be obtained. This is extremely effective for systems that require high reliability and high speed, such as satellite communications. In addition, the process of calculating the error locator polynomial and error value polynomial, which is the center of the decoding process, is performed using 10-210-2O (cod
This is a very effective method for high-speed processing because it can also be performed using length/5ec). - However, the data transfer rate used in CDs, magnetic disks, etc. is often less than 10 Mbps, and there is still a problem in this regard, as there is a demand for smaller hardware capacity.

[Means for solving problems]

In view of the above points, the present invention utilizes the characteristics of the architecture of the R3 encoding/decoding system shown in the above rBC) I encoding/decoding method previously filed by the present applicant, thereby achieving the high-speed conditions of 2). We propose an architecture that can achieve condition 4) with miniaturization by sacrificing .

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

The architecture of the R5 encoder decoder described above applies the idea of systolic architecture.

A feature of the systolic architecture is that one process is handled by the same network of the same PH. This applies to all processing elements (P
This shows that the processing performed in E) is the same, and the input/output relationships are also the same. Therefore, after performing one process with one PE, the processing result is not sent to the next PH, but is stored in the memory (register) section and fed back to itself, allowing processing without increasing the number of PEs. I can do it. Therefore, I'E, which will be the basis of this study, is defined as shown in Figure 1. In FIG. 1, numerals 1-4 are the same as those in FIG. 36, but registers 5-7 form an m-stage register array or memory section.

Considering GF(2'), the circuit scale is approximately 50 gates with the configuration shown in Figure 37 for the l selector, and the 3rd multiplier for 2.3.
In the configuration shown in Figure 8, one gate has approximately 300 gates, and the 4 adders are the third gate.
The configuration shown in FIG. 9 requires approximately 50 gates, and one register 5-7 requires approximately 50 gates.

Also, when focusing on one PE, in the previous architecture, after performing one process and outputting the processing result, that PE can receive and receive the next input, so high-speed processing that takes full advantage of IPE processing speed However, if the processing result is not sent to the next PE but fed back to itself, the next input cannot be received, so from an external perspective, the data transfer rate to one PE is slow. (It becomes. However,
The processing speed of the PE itself is determined by the calculation unit of the PE consisting of 1-4 units, and its configuration remains unchanged, so the processing speed is 10-20 M h
It is z. Here, for later convenience, the processing speed of IPE is assumed to be l 6 Mhz.

Hereinafter, the processing of steps 1-4 will be realized using this PE as a basic model, but for the purpose of miniaturization, unnecessary parts will be removed in each processing and the PE will be optimized in each processing.

First, the principle of the R3 code will be described. The R3 code is a code of great practical importance, having the characteristic of having the lowest redundancy among linear codes having the same code length and correction ability.

The R5 code is a non-dual BCH code (Bose-Chavd
This is a special case of finite field (hereinafter abbreviated as GF) GF.
It is composed of (q). Here, q is GF (q
) is the original number of

Using this q, various parameters characterizing the R3 code are defined as follows.

・Code length: n (-number of symbols in the code) n≦q
-1 (2-1) ・Number of information symbols 2 k (-number of information symbols in code)
・Number of check symbols: n-k (-number of check symbols in the code) n- = dmin-1 (2-2) ・Correction ability: t (-number of symbols that can be corrected in the code)
([X] Gaussian symbol 9. The largest integer not exceeding x) Here, d m i n is what is called the minimum distance (/Hemming distance).

Here, polynomial expressions such as code words will be explained.

For example, if you want to encode as many information symbols as "" (1
o+ 11+...+ Ik-+)
(210), this is expressed as a polynomial as follows.

I(x) = i, +i, x+i+ x"+...-+
ih, xk-2+i, -1x"-' (2=11)
(n-k) check symbols C= (
C0,C,...+Co-h-+)
(212) is C(x) = co+c+ X+C2X"+-...C,
, -m-1"X--' (2-13) Furthermore, the code word F = (fo, L, fz, -f, -+) that summarizes these
(214)=(c,,c,...-1 to Cn-
+ to I I+ mountain, ... ib-+) (21
5) is F(x) = fo+f + x+fz x”10'・f
n-2 '-'+fn-I X'-' (2-16)
can be divided by the generator polynomial G(x) that generated it.
, α2. . . . Since it has a root C1, when this root is substituted into the code word polynomial F (x), the following equation is established.

F(α')=0(i=1,2.-・,n-k) (
2-21) Expression (2-21) is expressed as a matrix as follows (vT is the transposed matrix of F).

Here, the matrix H on the left side is called a parity check matrix and has an important meaning in decoding.

Salt 4L Method As already mentioned, since the R3 code is a type of BCH code, it can be decoded using a general RICH code decoding algorithm. However, in that case, handling of symbols such as addition and squaring in the decoding process must be performed on the finite field GF (q) in which the R3 code is defined.

Code length n defined on GF(2''') (m: positive integer)
Considering an R3 code with = 2'''-1, the symbol is represented by an m-bit binary number, and the operation is GF(2''')
done above. Further, equation (2-17) is used as the generating polynomial, and the minimum distance between codes is set to dmin=2t+1 for simplicity.

g(x)−(x −α)(x−a”) −・−(x−a
"-") (2-17) However, α is a finite field GF (2
'') The decoding procedure for such an R3 code is divided into the following four steps, as in the case of a general CH code.

Step 1) Syndrome calculation.

Step 2) Calculate error locator polynomial and error evaluation polynomial.

Step 3) Estimation of error location and error value.

Step 4) Execute error correction.

Step l Syndrome 8 - First, the transmitted codeword is F: F=(fo+fl,
``'fn +) The error that occurred is E: E=(eo
, el, "'en-1) R the received word:
R = (ro, x, -=rn-1) = F+E = (fo+eo, f++e+, -fn-++en-
+), the polynomial representation R(x) of the received word is as follows.

R(x) =F(x)+E(x)=(fo+e
o) + (f++e+) x+-・+ (fn-++
en-+) X'-' (2-23) However,
The generator polynomial G (x) ((2-
If we substitute the root a' (i=1.-, n-k) of Equation 17), (F(α') = O) holds, so we similarly set a i (i =1.-”, n-k)
Substituting R(α')=F(α・)+E(α')=O+E(α')
A value determined only by the error E is found, such as =E(α').

This is called a syndrome, and it is called S” (Son S+, ..., -1 for Sn-)
(225) s i R(a”s=E (a”
' ) (1=0 + 1 + ...+ -1 to n-
) (226). This syndrome contains all the information about the error (location and size of the error).

(Since the syndrome is 0 if there is no error, the presence or absence of an error can be detected.) Syndrome ((2-25).

Expression (2-26) is expressed as a matrix as follows.

5=HR” (R”: transposed matrix of R) (2-
28) In Step 2 of Stella 2 TE P l Effort - Effort, the error locator polynomial and error evaluation polynomial are calculated using the syndrome of the calculation result of Step 1.

First, let f(i!≦t) be the number of nonzero elements of error E=(eo, el...enl), that is, the number of errors. Also, let the position where the error occurs be ju (u=1゜2・-1) (ju=o, l・−n−1), and the position ju
Let the error in be elu. Furthermore, (2-2), (
2-3) Expression to n-=dmin-1=2t
(2-30). Then, the syndrome and syndrome polynomial of equation (2-26) are expressed as follows.

(and the following equation is obtained.

S (x) = [S - (x)] mod
x” (2-35)Now, we define the error location polynomial σ(X) as follows.This polynomial is defined as the error location in the received word, ju Cu=1.2.−・−・−・,
I! ) Cju=0,1. It is a polynomial whose root is element α-1'' of GF(2'') corresponding to . . . n-1).

a (x)=(1-a”x) (1-a”x) −”
(1-a'"x) = n (1-a"x)m1 Next, define the error evaluation polynomial ω(X) for σ(x), S, , (x) described above as follows. do.

Then, from equations (2-34), (2-35), and (2-37), the following equation holds true.

σ(x)+13 (x) = [ω(x)] modx
” (2-38) Therefore, an appropriate polynomial A (
x) using σ(X), S(X).

The relationship of ω(X) is expressed as follows.

A (x)-x"+a (x)・S (x) = ω(x
) (2-39) By the way, since the number of errors l is (1≦t), ω(x) and σ(X) are deg (IIJ (x) < deg cy (x)
≦t(2-40) is satisfied. Furthermore, ω(X) and σ(X)
are relatively prime (the greatest common difference (GCD) polynomial is a constant), (2-39), so ω(X
) and σ(X) are uniquely determined except for the difference in constant coefficients.

From the above, ω(x) and a (x) can be found through the process of Euclid's mutual division method to find the greatest common denominator (GCD) polynomial of X21 and S (x). Here, we will discuss how to calculate the greatest common denominator (GCD) polynomial using Euclid's algorithm.

I will briefly discuss this. First, two polynomials A, ! : The greatest common denominator polynomial of B will be expressed as GCD [A, B]. Also, for A and B, if the following polynomial λ and n a degA≧degB, λ=A-[A-B']-
B (2-41)B=B (2-4
2) If −degA≧degB, λ=A
(2-43) if = B-[B-A-']-A
(2-44) ([X-Y-']: quotient of polynomial X divided by polynomial Y) Definition Surto, GCD [A, B] (
! :GCD Eλ, B] C, the following formula is satisfied.

GCD [A, B] = GCD [λ, B]
(2-45) Therefore, the above-mentioned X and 100 are rewritten as A and B, and according to the magnitude relationship of the respective degrees degA and degB (2-41).

(2-42) or (2-43), (2-44
), and when either A or B becomes a zero polynomial, the other non-zero polynomial is obtained as the greatest common polynomial of A and B. In addition,
Finding the greatest common polynomial of polynomials A and B is no different from finding polynomials C and D as shown below. Note that deg refers to the order.

GCD [A, I3] =CφA+D −B
(2-46) Then, in the process of executing the above repeating steps and finding the greatest common polynomial of polynomials A and B whose degree is expressed as i=degA≧degB, polynomials 〇, D, and W that satisfy the following equations are obtained. You can ask for it.

The problem of finding such a polynomial is called an extended GCD problem.

Therefore, the error locator polynomial σ(X) and the error evaluation polynomial ω(
x) in equation (2-47), polynomial A is
It can be found by solving the extended GCD problem when polynomial 2B is set as S (x).

First, as mentioned above, the algorithm for deriving σ(x) and ω(x) can be reduced to an extended GCD problem. That is, x
21 as polynomial AO, syndrome polynomial S (x) ((
When we set Equation 2-32) as the polynomial Bo, (degAo=
2t.

degI3o=2t-1), the polynomial that satisfies the process of finding GCD [Ao, Bo] is: Once W is found, D represents the error locator polynomial σ(x) and W represents the error evaluation polynomial ω(X), respectively. ing. It is known that such σ(x) and ω(X) are uniquely determined except for the difference in constant coefficients. Therefore, for An and Bo, the following polynomials A, B,
Define U, V, L, and M and set their initial values as U = M = 1; L = V = 0; (A = A
o, B = Bo), repeat the steps in Figure 40, and when degA (degB) < t, A (B) becomes ω(x) and L (M) becomes σ(X). Find each.

In addition, in the method shown in Figure 40, the division on GF in the iterative step is omitted by multiplying A and B by the highest degree coefficient α of polynomial B and the highest degree coefficient β of polynomial A, respectively. . ((2-41).

(See equation (2-43)) Even if we do this, σ(x) and ω
There is no essential problem with the value of (x).

FIG. 40 will be explained. First, in step l, U=M=1. L=V=O, A=Ao, B=B.

and set the initial value. In step 2, de
Determine whether gA≧degD, and in step 3, multiply A and B by the highest order coefficients β and α of polynomials A and H, respectively, and calculate GF in the repeating steps of equations (2-41) and (2-43). The above division is omitted.

If degA and degB become smaller than the predetermined order in step 4, proceed to step 5.6, and ω(x)
=A, a (x) =L, ω(x) =B, a
Calculate (x)=M.

Note that in order to execute the iterative steps shown in FIG. 40, three execution modes are required depending on the orders of A and B, and these will be referred to as follows hereinafter.

i) degA, degB≧t and degA≧de
gB...'reduceA'if) degA, deg
B≧t and degA≧degB・”“reduceB”
1ii) degA<t or degB<t
...-'nop'' Step 3 =; In Step 3, the error position and error value are estimated from the error locator polynomial σ(X) and the error evaluation polynomial ω(X) obtained in Step 2. First, the received word R= (ro,
symbol position i20 in r+, .-., rn-+).

■...The element α-1 of GF(2") corresponding to n-1 is successively substituted into the error locator polynomial σ(X). At this time, (2-3
From equation 6), if σ(a-')=0 holds true, it can be seen that α-1=α-j' holds true for i at the error position ju. (j u = 0, 1 = -n -1,
u = 1, 2...1, 1≦t) Also, the error evaluation polynomial ω(X) for such α−1=α−I′
The value of is as follows.

(For k-1.≠U) Furthermore, if σ'(X) is the differential of σ(x), then the following holds true. Therefore, from equations (2-48) and (2-49), the error value eju at the error position ju can be obtained from the following equation.

As mentioned above, in step 3) of decoding, step 2
), the R8 code is defined in three polynomials: the error locator polynomial σ(X), the error evaluation polynomial ω(X), and the differential σ'(X) of σ(X).

Element a-' (j=n-1,-2,1,0
) is required to calculate the value by sequentially substituting (
Here, the received symbols are input from higher-order terms of the received word polynomial. That is, rj is j=n-1,...,2,1
．． It is assumed that the numbers are input in the order of 0. Therefore, in the explanation of step 3), α−' (j=n 1 , . . .
・, 2, l * O) must be noted that the order of assignment is reversed. ) You can use the same algorithm as at the end. For example, the calculation of the degree polynomial "(X)" is expanded as follows.

f (x) = ftx'10ft-1x'-'+-+
f 1x+fo arrow;=stomach main=h
((ftx 10ft-1) x+ft-2) x+-
=+f+l
- From equation (2-9), the received symbol r at the position ju where the error occurs can be expressed from the original code word symbols f and the error size el, as follows.

flu = r, ue),,
(2-51) Therefore, in step 4, the position i (i
= 0, 1, ... -n -1), subtract from received symbol r1 < (on GF(2")) f, = rl -e
, (2-53) perform error correction at position i.

(Syndrome Generation Unit) Next, the configuration and operation of the BCH encoder/decoder according to the embodiment of the present invention will be described in detail for each configuration unit.

In step l, the received sequence R=
From (rn-+, rn-2+++, l, ro), the coefficients of the syndrome polynomial required in step 2 (S21
-1, S21-2...

It is necessary to output S+, So) serially.

The following iterative algorithm is used to specifically calculate the coefficients of the syndrome polynomial.

S+-+ =(”'((rn-1 tree α'+r, -z)*
α'+rn-n)'a'+・+r+) tree α' + r
e Also, decompose the above equation as follows.

Za"O Zl "Zl-1*α' + rn-+
(t = 1 + ... + n) S, -, =
Z.

In order to miniaturize the circuit, 3 multipliers and 5 registers which are meaningless in the PH of FIG. 41 are removed. As a result, the calculation section of the PE has 400 gates. Here, the 42nd
Paying attention to the movement of the received symbols in the figure, one received symbol r n-1 does not change value (from PE #1 to #
Only the term ZI-+*αj that is sent and added to the 2t PE changes. Therefore, in the previous chapter, the PE of the syndrome generation unit was assigned to each αI (j=1.., 2t), but here, from αj large input to α' (j=1゜...,
2t) are input sequentially, and the input of α' (j=:1...rm) is repeated periodically, with one cycle being from j=1 to m. Then, r+, which is the input of the received sequence, is held for a period of one month corresponding to the value of one received symbol, while receiving symbols rn-+ (i=1...rn) are input. As a result, the register 7 can also be omitted, and the rI large input is directly input to the adder. However, since the register 6 needs to store the ZI operation result for one cycle from PE #1 to PE #m, m stages are required. The signal flow when m = 2 t is expressed as the third
As shown in the figure.

Initially (i=1), selector selection signal St, 2 is r
Only when n-1 is input, Sl, 2 = IO, and O, which is the C input, is output from the are input sequentially. After that (i = 2,...+
n), Sl.

By setting 2=00, the X output of the selector selects eight power, and Zt-1, which is the result of the previous calculation, is sequentially output from the X output, and αj (j=1°...
, 2t) and added to rn-1, resulting in Z+=Z+-1*α'+rn-+ (J= L""+
2t) is calculated and sequentially input to the register. Therefore, the register for stage 2 is 5t-I (J=1+..., 2t
) is a memory section that temporarily stores the intermediate results of calculations and feeds them back again. With this, 2
The processing of PEs can be realized with one PE, but the input r is the same as the number of register stages. Since it is necessary to hold -1,
The processing speed is (16/2t) Mwps.

Here, in order to miniaturize the circuit, the multiplier 3 is removed and the register rows 5 and 7 are also omitted. Therefore, the circuit scale of the PE shown in FIG. 2 is (400+m*50) gates, and the processing speed is (16/m) Mwps. m is the number of register stages, and when all processing is performed by IPE, m=2t. As an example, if the correction capacity t = 8, the IPH circuit scale will be 120 gates, and the processing speed will be I M h
z = 8 Mbps.

Further, when all processing is not configured by IPE but divided into a plurality of PEs, the PEs shown in FIG. 2 are connected as shown in FIG. 4. At this time, a register controlled by CR2 (clock for each cycle) is required to delay the received symbol by one cycle for each IPE. If the number of PEs is k, the overall processing is distributed over (2t/k), so the number of register stages required for IPH is m=(2t/k). Therefore, the circuit scale in Fig. 4 is (2t/m) * (400+
m*50) gate. FIG. 5 shows the signal flow when configured with two PEs.

In this case, the assignment of αJ is as follows: PE of #l is α'(j=L...
・.

t), PE of #2 is α' (j=t+1...., 2t
).

In this case, the number of register stages m=t, so the processing speed is 2
Mhz = 16 Mbps, and the circuit scale is 800*2=1600 gates.

When m = 1, the number of required PHs is 2t, and CK2 = CK, so the register controlled by CR2 is equivalent to register 7, and the processing speed is 16Mwps.
becomes. Therefore, this has a configuration in which unnecessary circuits shown in FIG. 42 are omitted. Also, by utilizing the fact that the B input of the selector is vacant, by inputting the S (x) output of the previous PE, the coefficients of the syndrome polynomial (S 21-11321-2 , - , S + +
S o ) can be serially output as S'(x).

GCD/, , i, eW
workman .

The algorithm for deriving the error locator polynomial σ(X) and the error numeric polynomial ω(X) in step 2 can be reduced to an extended GCD problem. In the circuit shown in FIG. 43, each PE passes the output to the next PR after completing one Process process, and receives and receives the next input and performs two Process processes. Part 2: Do not output the Process processing result to the next PH, but store it in its own register, and after completing one series of inputs of the syndrome polynomials S (x) and xl, feed back the result stored in the register, Consider performing all processing with one PE.

The configuration of the PH at that time is shown in FIG. Similarly to FIG. 43, a circuit for setting 5tate, a register controlled by CR2 and CL for holding α and β, and at-1°b
To realize +-+, it is necessary to insert one more stage of registers after register row 5.7. Therefore, when the number of register stages in the PE is m, the circuit scale required in the IPE (the State setting circuit is the control section, so the division () is (700 + (3m + 4) $50) gates. (700 is The circuit scale of the calculation section is (3
(m+4) is the total number of registers) When performing all processing with one PE, m = 2t (because the degree of the polynomial of the processing result cannot exceed 2), and for the example shown in Fig. 40, A ( FIG. 7 shows the beginning of the signal flow when determining B), and FIG. 8 shows the beginning of the signal flow when determining L (M). The switching of the selector selection signal and the control of CR2 are performed every (m + 1) basic clock CK, taking into consideration the inserted register, so that the operations shown in FIGS. 44 and 45 can be performed sequentially on one PE. You can see that it is done in

Note that, when calculating A (B) and when calculating L (M), it is necessary to have two independent Process sections or use one Process section twice. Below, we will evaluate one Process process.
If used twice, reduce the processing speed by half and use two Processes.
If the ss section is provided independently, the number of required PEs may be doubled.

Here, the syndrome polynomial S (x) (or M
= 1) and xh (or L-〇) input selector selection signal Sl, 2 = 11 for x, y output.

Use a selector that outputs the E input. (The table shows the combinations of selector outputs) Also, A (B) and L (M)
When processing 31. as shown in FIG. 10 using the PE shown in FIG. ．． By controlling 4, A=x″, B=S (x), L=0.M=
You can also input 1. (The combinations of selector selection signals are shown in the table.) However, since the PE of lt+2 in Fig. 43 has meaning only for signal selection by the selector, the PE of Fig. 9
Using the W output of E, the number of processing times by PE is set to 2t+1 times. (Also, in the PE shown in Figure 6, by providing a separate selector, the number of processing circuits is reduced to 2t+1 times.
The signal selection at t+2 is determined by setting 54=1 when degB<t. Therefore, the processing speed here is as follows: The processing shown in FIG. 43 is performed every m register stages (16/ 2t/m) M
l p s. As an example, if t=8 and m=2
When t is the circuit scale, the circuit scale is 3300 gates, and the processing speed is 1/16M1ps=n/16Mwps.

Furthermore, when all processing is not configured by IPE but divided into a plurality of PHs, the PEs shown in FIG. 6 are connected as shown in FIG. 11. At this time, in order to operate while circulating the coefficient data in each PE, it is necessary to feed back the output of the last PH to the first PH. If the number of PHs is k, the entire processing is distributed over (2t/k), so the number of register stages required for IPH is m=(2t/k). Therefore,
The circuit scale in Figure 11 is (2t/m) * (700+
(3m+4) *50) It becomes a gate.

FIG. 12 shows the signal flow when configured with two PEs. In this case, the number of register stages m = t, so the processing speed is 2/16M1ps, and the circuit scale is 1950
*2=3900 gates.

When m = 1, the required number of PEs is 2t, and the processing speed is 16 M l ps. In this configuration, feedback is provided from the last 1)E to the first PE, so the number of PEs is only 2t for 2t+1 processing times.

In order to establish a systolic connection, if the number of PHs is set to 2t+1 in correspondence with the number of processing times, there is no need to feed back the signal, resulting in the same configuration as in FIG. 43. (In this case, the PE of #2t+2 becomes a selector.) : As in step 3, the following iterative algorithm and decomposition formula can be used as in step 1.

f = (x) = f +-+ * x'-'
+ f L-2* x'-' -+ f + * x
+f.

= i・((ft-+*x ft-z) *x+ft-
3) *x+-+f+) *x+fo) Zo=O Z1=Z+-+*x+ft-+ (j=t+...
+t)f(x)=Zt Also, in order to miniaturize the circuit, the multiplier 3 and the register 5 are removed as in step 1. In addition, in the circuit shown in Fig. 46, the input of α-' (i=n-1,..., 0)
Similarly, the value is simply sent from PE #1 to PE #t without changing the value. Therefore, from j=1 to m is 1
α−' so that one value of α−1 is held as the period
Input (i=n-1,...,0).

Also, the coefficient of ft-1 is f
The input of r−+(j=1..,m) must be repeated. Considering the output from the GCD generator in step 2, the coefficient f + - + (j = 1..., 1) is 1
It is output once, but it is not repeatedly output periodically. Therefore, the first
The PE is configured as shown in Figure 3, and signals are sent as shown in Figure 14. From the GCD generation unit, the coefficient ft-+(j=L...

t) is output, the selector selection signal is set to Sl.

2=11 (only when ft-+ is input) to S
l.

By setting 2=O1, the coefficient f I-
+(j=1. . . , 1) are sequentially output and input to the register column 7.

By feeding back the output to the B input and changing the selector selection signal from Sl, 2 = 10 (only when ft-+ is input) to Sl, 2 = OO, the coefficient f + - + ( j=L..., 1) is output and input to the register column 7. Thereafter, by repeating this operation, the coefficient ft-4 (j = 1..., 1)
periodic input is realized. This allows step l
Similarly, the processing of m PEs can be realized by one PE, but since it is necessary to hold the input α-1 for the number of register stages, the processing speed becomes (16/m) Mwps. (m is the number of register stages) Also, the circuit scale required for IPH is (400+ (m+1)
*50) Becomes a gate.

m is the number of register stages, and when all processing is performed by IPE, m = t. However, ω(X), σ(X).

Three sets of PEs are required to process σ'(X).

As an example, if the correction capacity t=8, the circuit scale is 3*
850 = 2550 gates, processing speed is 2 Mw
It becomes ps.

Furthermore, when all processing is not configured by IPE but divided into a plurality of PHs, the PEs shown in FIG. 13 are connected as shown in FIG. 15. At this time, a register controlled by CK2 (clock for each cycle) is required to delay α1 by one cycle for each IPE.

If the number of PEs is k, the entire processing is distributed over (t/k), so the number of register stages required for IPH is m = (t/k).
). Therefore, the circuit scale in Fig. 15 is (i/m)*
(400+(m+1)+50) gates. 16th
The figure shows the signal flow when configured with two PEs. In this case, since t=8, mmi(t/2)=4, the circuit scale is 3*2*650=3900 gates, and the processing speed is 4 Mw ps.

When m = 1, the number of PRs required is = t, and CK
Since 2=CK, the register controlled by CK2 is equivalent to register 5, and the allocation of f+-+ has the same configuration as in Figure 46 except for the part, and the processing speed is also 6 M
It becomes w p s.

Also, in Fig. 17, a (x) and σ'(x) are expressed as one P
When processing with E, PE is shown, and FIG. 18 shows the signal flow. In step 3, since one period is t, IPE can be used twice, and the coefficient of σ'(X) uses the coefficient of σ(X). As a result, Step 3 can be realized with two sets of PEs, and as shown in Fig. 18, the operations of σ(X) and σ'(X) are every 2, and ω(x)
2 can be operated every time by making the appearance as shown in FIG. 19.

Here, it is sufficient to use a selector whose output combinations are as shown in the table, and to set the selector selection signal to 81°, 3=001 only when the Y output is 0. In this case, the processing speed is 2
M w p s / 2 = I M w p s, and the required set of PEs is also 2 cents, so the circuit scale is 2*850=1700 gates.

Here, the S required to perform erasure correction in response to the coefficient output S (x) of the syndrome polynomial from step l
(x) *Generate λ(X).

First, consider generating the vanishing position polynomial λ(x). Two λ(x) = (1-Y+*x)*(1-Yz*x)-
”(1-Ya*x), and similarly to the previous chapter, λ(X) is decomposed as follows.

Zo=1 Z+= (1-'/+ * x ) * Z+-+
=Y+*Z+-1*x +Z;-+ (+=1...
, s)λ (x)=Zs First, in order to miniaturize the circuit, the multiplier 3 and the register 6 are
Sharpen. Here, it is made to correspond to the number of processing clocks or the number of register stages. Also, one register is prepared for delaying the Z +-+ input by l clock. Therefore, the configuration of PH is as shown in Figure 22, and the circuit scale required for IPH is (4
00+ (m+1)$50) gate. (m is the number of register stages) FIG. 23 shows the signal flow.

Number of register stages m in IPE (here m = 2t)
Yl is set so that one value of Yl is held as one period.
Input (i=1..,s). First, (at the time of Y+ input) the selector selection signal is S1, 2=11, the D input Za=1 is input to X, the C input O is input to Y, and the operation result Y1 is input to the register column 6 at the next clock. Hereafter, Sl,
Assuming that 2=10, outputs the eight power output by delaying Xl, :C input 0SYi, :Zo by one clock, and inputs the calculation result Zo=1 to the register column 6 at the next clock. From the next clock onwards, since the calculation result is 0, 0 is input to the register column 6. After one cycle, the pre-computation result Z + = Y I * x + 1 (order X represents the order of the signals) is output from the register array 6 (Y2 8-man power), so Sl.

2=01, the highest order coefficient Yl of the previous calculation result is outputted to X, 0 of the C input is outputted to Y, and the calculation result YI*Y2 is inputted to the register column 6 at the next clock.

Hereafter, as 81.2=OO, the next coefficient l of zI is set to X from the eight power, and Y is the highest coefficient Y of zl delayed by 1 clock.
+ is selected from the B input, and the operation result Y1+Y2 is input to the register column 6 at the next clock. At this time, from X
The coefficient 1 next to zl is output from Y, and the calculation result l is input to the register array 6 at the next clock. Since the calculation result is 0, 0 is input thereafter.

By repeating the operation of the Y2 eight-manpower operation after the Y3-manpower operation, λ(x) is outputted from the register row 6 from the higher-order coefficient after the Y6 manpower.

Since S≦21, Y+=O(i=s+1.-.2t
).

Therefore, the processing speed is (16/2 t/m) M
l p s. As an example, if t=8 and all processing is performed by IPE, the circuit scale will be 1250 gates and the processing speed will be 1/16M1ps.

Furthermore, when all processing is not configured by IPE but divided into a plurality of PHs, the PEs shown in FIG. 22 are connected as shown in FIG. 24. At this time, in order to hold the value of Yl for 2t clocks, a register for setting Yl is required for each PE.

If the number of PEs is k, the whole process is (,2t/k
), the number of register stages required for IPE is m
=(2t/k). Therefore, the circuit scale in FIG. 24 is (2t/m)*(400+(m+1)*50) gates. FIG. 25 shows the signal flow when configured with two PEs. The circuit scale at this time is 850*2=1
700 gates, processing speed 2/16 Ml
ps.

When m = 1, the required number of PEs is 2t, and the processing speed is (16/2t) Mlps, which is equivalent to the configuration shown in FIG. 47.

Next, consider the multiplication circuit S (x) *λ(X). The calculation of the multiplication C(x) = A (x) *B (x) is decomposed as follows in the same way as in the previous chapter.

A(x) = am-1*x""+am-z*x'-"+
-+a+*x+a.

Then C(x) = am-+ * l3(x) * x″'-'
+am-2* B(x)* x'''-1, +, ・+a
+*B(x)*x+aoB(x), so Z o = O Z+=Z+-+*x+B(x)*am-+ (j=1
1-1m) C(x) = Zm Therefore, while B (x) is input, a□-1 is held and after calculating Z+ = Z+-+*x+B (X) *am-+, register column 6 It is sufficient to insert the calculation result into 21-1 after one cycle and feed it back as 21-1. However, the inputs S (x) and λ(X) are only input once from the syndrome generating section in step l and the above-mentioned error locator polynomial generating section at the transfer rate of the basic clock CK. Therefore, register arrays 5 and 7 are used to realize repeated input, and a register controlled by CK2 is used to hold set values. Furthermore, since the B (x) output from register row 7 needs to be fed back one clock later than the 21-1 output from register row 6, the configuration of PE is as shown in FIG. 26. B (x) = S ('x).

Figure 27 shows the signal flow when am-i''λ2l-1 (i = O, -, 2t). (The number of register stages in the IPE is m-1 = 2t-1.) First, selector selection λ(X) as signal St, 2=01
is input to the register column 5 from the F input through the W output.

At that time, the highest order coefficient λ2t of λ(x) is stored in a register controlled by CK2 and set as an input to the multiplier 3. Also, if S (x) is delayed by one clock from λ(X), E
It is input to Y, outputted to Y, and inputted to register column 7. Meanwhile, X outputs C input O.

As a result, λ2. *5(x) is calculated and input to register column 6. At this time, the highest order coefficient λ2L*521-1 of λ(x)*S (x) has been calculated, so CKD
is latched and output. Let one period be m (here, m = 2 t ), and after one period, the selector selection signal Sl, 2 = 00. S (x) fed back by the m-stage register array 7 is input from B, and is inputted again from Y to the register array 7. From D, λ(x) with the highest order coefficient shifted is fed back by the m-stage register array 5 and output to W.

Therefore, in CK2, the coefficient λ2t-1 next to λ(X) is stored and set in the multiplier 3. From A, the shifted highest order coefficient of all the calculation results is fed back by the m-1 stage register array 6, and is input to B (x) = S (x) in the form of a shifted first order coefficient. This allows Zl
=Z+-+ *x+B (x) *am-i is calculated and input to the register column 6. Thereafter, λ0 is input to CK2, and calculations are performed in the same manner until the calculations are completed. However, since the calculation result that becomes the answer shifts when fed back to the input, it is output by CKD every time the calculation is performed. Furthermore, the coefficient of λ(X) also shifts when fed back to the input, so the coefficient decreases by one order. Since the shifted coefficients are not needed, 0 is output to X and W by setting the selector selection signal to Sl,2=10 when fed back.

Furthermore, since the answer operation result remains in the register column 6 after the operation is completed, by repeating the same operation, the result in the register column 6 is shifted by one coefficient and output from CKD.

The circuit scale required for IPE is the number of register stages in PE as m-
1, it becomes (400+3m*50) gates).

Further, the processing speed is (16/4t/m)/2 because it is necessary to consider the period from the end of calculation to the end of output.

When all processing is performed by IPE, the number of register stages in PE is m = 2
As an example, if the correction capacity is t = 8, the circuit scale will be 2800 gates and the processing speed will be (1/32).
Becomes Mlps.

Further, when all processing is not configured by IPE but divided into a plurality of PHs, the PEs shown in FIG. 26 are connected as shown in FIG. 28. At this time, in order to hold the value of am-i for 2t clocks, a register for setting am-1 is required for each PE. If the number of PHs is k, the whole process is (2t/k
), the number of register stages required for IPH is m
=(2t/k). Therefore, the circuit scale in FIG. 28 is (2t/m)*(400+3m*50) gates. FIG. 29 shows the signal flow when configured with two PEs. At this time, the circuit scale is 1600*2=3200 gates, and the processing speed is (1/+6) M l ps.

When m=1, the number of PEs required is 2t, and the processing speed is also (1/2) Mlps.

The encoding is information 1 (x) = (Ik-+, Ik-2.
・=, Io) to parity P (x) = (P2t,
P2t-1,..., Pl) are generated. Encoding means generating polynomial g (X) = gm * x" + gm-+ *x'"-'
10g IT+-2*x”-2...10g1*x+g.

Then, P (x) = I (x) *x” mod g
(x), g' (x) = gm-+*x'''-'+gm-2*x
′″-”-10g+*x+g.

Then This formula can be decomposed as follows.

Zo=I(x) Z+=gm*Z'+-++Zm*g' (x)
(i=L-+k)P(x) =Zk Here, Zm is the highest degree coefficient of the polynomial Z,-1, and Z'
=1 is a polynomial obtained by removing the highest order coefficient from Zt-+.

Hold Zrn while inputting g'(X), and Zm*g'(x)
Perform the calculation. Here, g m = 1 and the 30th
Configure PE as shown.

From gl to the coefficient gm-1 of g' (x), go sets m to 1
The signal is periodically input to the multiplier 2 as a period. Also CK2
Zm is held by a register controlled by (clock for each cycle) and CL, and is input to A.

Z'i-1 is realized by outputting the previous operation result Zl-1 l clocks earlier than the period. Therefore, the number of stages of the register array 6 is set to m-1 and is fed back to the B input. Information 1 (x ) is input from C and is input so that one value is held for one cycle.

FIG. 31 shows the encoding process. First, consider the case when i=1. As an initial state, the information symbol Ik-+ is held in the register controlled by CK2, and information 1 is input from the C input.
Consider the case where 1□-1 is input to , and information symbols from Ik-2 to Ik-□ are stored in register column 6. In the arithmetic unit, Ik-+ from the A input is multiplied by g' (x), added to To-z~Ik-□ from the B input, and Ik-m-1 from the C input, and the result is the register column 6. Enter.

(Switching between B and C inputs for Y output is performed by selector selection signals Sl and 2, and when B input is selected, Sl.

2=00, Sl for C input, 2=01) The result of the operation is calculated from the 21 higher-order terms as I' k-+ = I k-
1*gm, +Ih−+−1. (j=l+”・
+m) After t=2, encoding is performed by performing the same processing on 1' h-t up to i=k.

Further, in order to realize the initial state, it is as shown in FIG. 32 (in the case of m=4). Information is input so that one cycle of open chain is maintained until Ih-+-Io. First, the selector selection signal St,2=01, and the first received symbol Ib-
Input + from C and output to Y. To the manual input, 0 is input by register CL controlled by CK2, and output is made to X. Since the number of register stages in PE is m-1, B
Ik-+ is fed back to the input one clock cycle before the cycle. At that time Sl.

2=00, output the B input to Y for l clocks, and
, restore the settings in step 2. At this time, the next received symbol Ii+-2 is input from C, so register row 6 contains I
After inputting k-1 for one clock, Ik-2 is inputted. During Ik-z manual input, the deviation from the feedback input from register row 6 is two clocks, so the selector selection signal is set to Sl, 2=OO
shall be. At that time, Ik-z is 1 after Ik-1.
The lock is selected. By performing the above operations in rows up to Ik-ffl, n+-+ to Ih-□ are stored in the register column 6. When inputting I k-m-l, Ik
-+ protrudes from the register row 6, but is latched into the register controlled by CK2, thereby achieving an initial state.

Also, information I (x) and parity P (x
) is also performed as shown in FIG. 33 using the two outputs of the selector. During the above-mentioned encoding operation, 2 outputs the C input which is the input of information symbols for each cycle. After the operation is completed, the parity output is circulated through the register row 6.
Since the number of register stages in the PE is m -1, the register controlled by CK2 outputs parity shifted by one order for each cycle of parity and feeds it back to the A input. At that time, Z selects the A input and outputs parity every cycle.

Therefore, the circuit scale and processing speed at this time are (400
+m*50) gate, and (16/m) M w
ps. When all processing is configured with IPE, m =
It becomes 2t. As an example, when the correction capacity t=8, the circuit scale of the IPE is 1200 gates, and the processing speed is I M w p s = 8 M b p s.

Furthermore, when all processing is not configured by IPE but divided into a plurality of PEs, the PEs shown in FIG. 30 are connected as shown in FIG. 34. If the number of PHs is k, the total processing is (2t/k)
Therefore, the number of register stages required for IPE is m
=(2t/k). Therefore, the circuit scale in Fig. 34 is (2t/m) * (400+m * 50)
It becomes a gate. FIG. 35 shows the signal flow when configured with two PEs. In this case, the number of register stages is m =
t, so the processing speed is 2 M w p s = f
6 Mbps, and the circuit scale is 800*2=1
There will be 600 gates.

When m = 1, the number of PHs required is = 2t, but
Feedback from PE in # to PE in #l, and 1
Since the simultaneous inputs of (x) remain the same, the encoder is still not systolic in this architecture.

5F'-'-0 and f(α-') output of system step 3 are output by I CK every 2 when using the PE shown in FIG. 17, but σ'(α
-'), σ(αI), and ω(σ') have a half-cycle timing difference, so σ'(α-') is latched by a register controlled by CK2 (2 every clock), and σ(α- 1
).

ω(α-I) is latched by CK2' (a clock shifted by half a cycle from CK2), and further latched by a register controlled by CK2, resulting in step 4 similar to that shown in FIG.
error correction is realized. (The timing is shown in FIG. 21. However, in the GCD generation section, A (B).

If one Process unit is used twice to process L(M), the coefficients of ω(X) are sent first (so they need to go through a buffer) to the error correction execution unit in step 4. When optimized, it becomes as shown in Fig. 20.

The operation after synchronizing the output timings of ω(α−1), σ(α−1), and σ′(α−′) is the same as in the previous chapter. Therefore, the circuit size required in step 4 is 450 + 5 * 50 = 700, excluding the buffer and reciprocal generation ROM.
It becomes a gate. Since the error correction execution unit in step 4 does not have a systolic structure, the circuit cannot be made smaller even if the number of register stages is increased.

Therefore, it is only necessary to simplify the circuit optimally depending on the situation. The same applies to the α-' (i=n-1, . . . , 0) generation circuit.

As described above, each RS code decoding stamp can reduce the size of the circuit in exchange for high speed.

As an example, in the decoder of FIG. 49, the control of each PE is controlled by the selector selection signal and the CK
You can run the entire system with only 2.

Step 1) SYNDROME: Figure 62 Step 2)
GCD, Figure 69 Step 3) EVALUAT
E, Figure 77 Step 4) CORRECT: When the encoder/decoder in Figure 80 is considered as a system, the decoder for erasure error correction in Figure 50 is taken as an example, and it is miniaturized by the following combination. It can be implemented as an encoder/decoder.

1) SYNDROME: Figure 622) GCD
:Figure 693) EVALUATE
: Figure 774) CORRECT : Figure 805) E
RASURE I: Figure 826) ERASURE
II: In FIG. 8, ERASURE ■ and ERASURE II are added to the decoder shown in step 4. Also, the 30th decoder shown in step 4
The encoder shown in the figure can also be added to form an encoder/decoder.

(If encoding and decoding are not performed at the same time, by making PE connections and PH control variable between encoding and decoding, an encoding/decoding device can be realized using the circuit shown in Figure 49 without changing the circuit scale.) As described above, the circuit scale (in gate units) and processing speed (in M w ps units) for each process are as follows. (wps=word/5ec)1) (2t
/m)*(400+m+50), 16/m2) (2
t/m)*(700+ (3m+4) +50), n
*(16/2t/m)3) 2*(2t/m)*(4
00+ (m+1) +50), 16/m5) (
2t/m)*(400+(m+1)+50), n*(1
6/2t/m)6) (2t/m)*(400*(3
m+2)+50), n*(16/4t)/m)7)
ENCODE: Figure 89; (2t/m)*(
400+m+50), 16/m1 As an example, when the R5 decoder has t=8, it can be realized with the following circuit scale and processing speed. (Code length n≧4t, and m = 2t to implement with IPE) 1200 + 3300 + 2500 + 700
= 7700 gateI M w p s = 8
M b p s and when t=2, 600 +1500 + 1300 + 700 +
3100gate4 M w p s = 32 M
b p s (2'') (7) If the circuit scale is M gates, the circuit scale of GF (2'') is approximately 4M gates. However, considering that the structure of l word changes from m bits to 2m bits, the processing speed per IPE is lO~20
Since M w p s (word 7 seconds), m ・(10
~20) Mbps becomes 2m/(10-20) Mbps, doubling.

The number of stages may be two. Then, the number of PEs required is
Since k=(2t/m) and m=2, there are t pieces. Therefore, we can change the structure of the Galois field from GF(2M) to GF(22M).
In this case, the circuit scale increases twice at the same processing speed. In general, the structure of a Galois field is changed from GF (2″) to GF
(2''-'), the circuit scale increases by a times.

〔Effect of the invention〕

As explained above, the PE used in the previous R3 encoding decoder
We demonstrated an architecture that can reduce the circuit scale by simply increasing the number of register stages.

As a result, the circuit scale (gate unit) and processing speed (M
(w p s units) can be expressed functionally by the correction capability t and the number of register stages m, and any processing power and processing speed can be achieved with a realizable circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a miniaturized processing element (PE) according to the present invention. FIG. 2 is an explanatory diagram of a syndrome generation circuit that optimizes the PE of FIG. 1 according to the present invention. FIG. 3 is a diagram showing a second diagram according to the present invention. PE timing diagram 4th
5 is a timing diagram of a syndrome generation circuit using two PEs shown in FIG. 2 according to the present invention. FIG. 6 is a diagram using the PEs shown in FIG. 1 according to the present invention. FIG. 7 is a timing diagram of a GCD generation circuit using the PE of FIG. 1 according to the present invention. FIG. 8 is a timing diagram of a GCD generation circuit using the I'E of FIG. 1 according to the present invention. 9 is an explanatory diagram of a GCD generation circuit using the PE of FIG. 1 according to the present invention. FIG. 10 is an input timing diagram of FIG. 9. FIG. 11 is a GC using the PE of FIG.
FIG. 12 is an explanatory diagram of the D generation circuit.
13 is a timing diagram of the CD generation circuit. FIG. 13 is an explanatory diagram of an error evaluation circuit that optimizes the PE of FIG. 1 according to the present invention. FIG. 14 is a timing diagram of the PE of FIG. 13 according to the present invention. FIG. 15 is according to the present invention. PH connection diagram No. 16 in Fig. 13
The figure is a timing diagram when two PEs shown in FIG. 13 according to the present invention are used. FIG. 17 is an explanatory diagram of an error evaluation circuit that optimizes the PE shown in FIG. 13 according to the present invention. Timing diagram No. 19 in Figure
20 is an optimized error correction execution unit according to the present invention. FIG. 21 is a timing diagram of FIG. 20 according to the present invention. FIG. 22 is a timing diagram of FIG. 1 according to the present invention. An explanatory diagram of an erasure position polynomial generation circuit that optimizes PE. FIG. 23 is a timing diagram of the PH of FIG. 22 according to the present invention. FIG. 24 is a connection diagram of the PE of FIG. 22 according to the present invention.
The figure is a timing diagram when two PEs shown in FIG. 22 are used according to the present invention. FIG. 26 is an explanatory diagram of a multiplication circuit that is an optimized version of the PE shown in FIG. 1 according to the present invention. 28 is a PH timing diagram of FIG. 26 according to the present invention, and FIG. 29 is a PH timing diagram of FIG.
The figure is a timing diagram when two PEs of FIG. 26 are used according to the present invention. FIG. 30 is an explanatory diagram of an encoder that optimizes the PE of FIG. 1 according to the present invention. FIG. 32 is a timing diagram of the PH of FIG. 30 according to the present invention (during initial input). FIG. 33 is a timing diagram of the PH of FIG. 30 according to the present invention (during numerical output). Figure 34 is a connection diagram of the PH of Figure 30 according to the present invention.
The figure is a timing diagram when two PEs according to the present invention are used. Figure 36 is a conventional processing element (PE).
Figure 37 shows the conventional processing element (PE).
Figure 38 shows the configuration of the selector of the conventional processing element (PE).
Figure 39 is a block diagram of the multiplier of the conventional processing element (PE).
Figure 40 is a diagram for explaining the algorithm for determining GCD. Figure 41 is a diagram for explaining the conventional PE for syndrome generation. Figure 42 is the connection of the conventional PH for syndrome generation. Figure 4
3 is a connection diagram of a conventional PE for GCD generation. FIG. 44 is a diagram showing the operation timing of a conventional PH for GCD generation. FIG. 45 is a diagram showing the operation timing of a conventional PE for GCD generation. FIG. 47 is a connection diagram of a conventional PE for error evaluation. FIG. 48 is a diagram for explaining a conventional PE for error correction. FIG. 49 is a diagram of a conventional error correction decoder. System configuration diagram Figure 50 is a diagram showing an example of an erasure error correction decoder.
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・・・・・・・・・Multiplier■ ・・・・・・・・・・・・
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...Adder patent applicant Canon Co., Ltd. No. 22 c-t t t---t t I t t
---Ban 6 Diagram C11 躬10 ward kudzu oAx No. 4318 ″, (GQ χ こ ;°2 Tame moxibustion-6・髫oto

Claims (1)

[Claims] (1) A multiplier on a Galois field that has a multi-input, multiple-output or multi-input and one-output selector and at least one of its selector outputs as an input, and an addition on a Galois field that has at least one input as the multiplier output. The vanishing position polynomial λ(x)=(1-Y_1・x)・(1- Y_2・
x)...(1-Y_sx) for Y_i (i=1,...,s), and the multiplication of polynomials A(x) and B(x) (of A(x) and B(x) (order is arbitrary) Vanishing position polynomial generation circuit that calculates C(x)=A(x)・B(x).