JP2556128B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2556128B2
JP2556128B2 JP1047015A JP4701589A JP2556128B2 JP 2556128 B2 JP2556128 B2 JP 2556128B2 JP 1047015 A JP1047015 A JP 1047015A JP 4701589 A JP4701589 A JP 4701589A JP 2556128 B2 JP2556128 B2 JP 2556128B2
Authority
JP
Japan
Prior art keywords
film
oxide film
polycrystalline silicon
deep groove
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1047015A
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Japanese (ja)
Other versions
JPH02226742A (en
Inventor
核太郎 須田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP1047015A priority Critical patent/JP2556128B2/en
Publication of JPH02226742A publication Critical patent/JPH02226742A/en
Application granted granted Critical
Publication of JP2556128B2 publication Critical patent/JP2556128B2/en
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Expired - Fee Related legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、素子間分離のために溝形分離構造を用い
た半導体装置の製造方法に関し、さらに詳しくは、溝形
分離のための深溝を埋め込んだ後の表面平担化方法の改
良に係るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a groove type isolation structure for element isolation, and more specifically, a deep groove for groove type isolation is formed. It relates to an improvement in the surface flattening method after embedding.

〔従来の技術〕[Conventional technology]

従来例でのこの種の素子間分離のための深溝による溝
形分離構造を用いた半導体装置において、その溝形分離
構造の主要な製造工程の概要を第2図(a)ないし
(e)に示す。
2 (a) to 2 (e), an outline of the main manufacturing steps of the groove type isolation structure in the semiconductor device using the groove type isolation structure with deep grooves for element isolation in the conventional example is shown in FIGS. Show.

すなわち,これらの第2図(a)ないし(e)に示す
従来例方法において、深溝による溝形分離構造を用いた
半導体装置は、まず、半導体基板1の主面上に第1の酸
化膜2aを形成した上で、溝形分離領域に対応する部分の
酸化膜2aを選択的にパターニング除去して開口させ、か
つこのパターニングされた第1の酸化膜2aをマスクに用
い、半導体基板1に異方性エッチングを施して所定深さ
の深溝ZG1を形成する(第2図(a))。
That is, in the conventional method shown in FIGS. 2 (a) to 2 (e), the semiconductor device using the groove-shaped isolation structure by the deep groove is formed by first forming the first oxide film 2a on the main surface of the semiconductor substrate 1. Then, the oxide film 2a in the portion corresponding to the trench-shaped isolation region is selectively patterned and removed to make an opening, and the patterned first oxide film 2a is used as a mask to make the semiconductor substrate 1 different. Isotropic etching is performed to form a deep groove ZG 1 having a predetermined depth (FIG. 2 (a)).

ついで、前記マスクに用いた第1の酸化膜2aを除去し
た後、前記深溝G1の内壁面,内底面を含む半導体基板1
の表面に第2の酸化膜2bと窒化膜3とを順次に形成し、
さらに、これらの上に多結晶シリコン膜4を堆積させ
て、各膜2b,3で覆われた深溝G1内を充分に埋め込むが、
このとき、深溝G1の中心部に該当する多結晶シリコン膜
4の表面部にあつては、くぼみG2が残存することになる
(同図(b)) 次に、前記くぼみG2の部分を一旦,平坦化させるため
に、このくぼみG2の部分を含む多結晶シリコン膜4上に
フォトレジストなどの膜を形成するが、くぼみG2の横幅
が充分に狭い限りにおいては、このくぼみG2上でのフォ
トレジスト膜5が平坦に塗布される(同図(c))もの
であり、仍つて、くぼみG2の横幅を狭くするために、前
記多結晶シリコン膜4の堆積膜厚は、これを厚くするほ
ど好ましいと云える。
Then, after removing the first oxide film 2a used for the mask, the semiconductor substrate 1 including the inner wall surface and the inner bottom surface of the deep groove G 1 is removed.
A second oxide film 2b and a nitride film 3 are sequentially formed on the surface of
Further, a polycrystalline silicon film 4 is deposited on these to sufficiently fill the deep groove G 1 covered with the films 2b and 3,
At this time, the depression G 2 remains at the surface portion of the polycrystalline silicon film 4 corresponding to the center of the deep groove G 1 (FIG. 7B). Next, the portion of the depression G 2 A film such as a photoresist is formed on the polycrystalline silicon film 4 including the recess G 2 in order to planarize the recess G 2. However, as long as the width of the recess G 2 is sufficiently narrow, The photoresist film 5 on 2 is applied evenly ((c) in the figure). In order to narrow the lateral width of the depression G 2 , the deposited film thickness of the polycrystalline silicon film 4 is It can be said that the thicker it is, the better.

続いて、前記フォトレジスト膜5と多結晶シリコン膜
4とのそれぞれを、共にエッチング速度のほゞ等しいガ
スを用い、その多結晶シリコン膜4の高さ位置が、前記
半導体基板1の表面以下になる深さまでエッチバックす
るが、このエッチバック操作によれば、上層側のフォト
レジスト膜5での表面形状が充分に反映されて、可及的
に平坦性を保持したまゝで、このフォトレジスト膜5と
共々に下層側の多結晶シリコン膜4を所定の深さにエッ
チング除去し得るのであり、この結果,前記第2の酸化
膜2bと窒化膜3とで覆われた深溝G1内は、上部に所定深
さの空間部6を残して、表面7が平坦な多結晶シリコン
膜4で充填された状態になる(同図(d))。
Then, the photoresist film 5 and the polycrystal silicon film 4 are each made to have a height position of the polycrystal silicon film 4 below the surface of the semiconductor substrate 1 by using a gas having an etching rate substantially equal to each other. Etch back to a certain depth, but this etching back operation sufficiently reflects the surface shape of the photoresist film 5 on the upper layer side and maintains the flatness as much as possible. The lower polycrystalline silicon film 4 together with the film 5 can be removed by etching to a predetermined depth. As a result, the inside of the deep groove G 1 covered with the second oxide film 2b and the nitride film 3 is removed. , The surface 7 is filled with the flat polycrystalline silicon film 4 while leaving the space 6 having a predetermined depth in the upper portion (FIG. 7 (d)).

最後に、前記深溝G1内に上部の空間部6を残して充填
された多結晶シリコン膜4の表面7部を選択酸化処理す
ることにより、こゝでは、上部に残された空間部6が第
3の酸化膜2cによつてキャッピングされるもので、この
とき、前記窒化膜3がこの第3の酸化膜2cの形成時の応
力を緩和するための役割を果たすことになるもので(同
図(e))、以上の各工程を経て、所期通りの深溝によ
る溝形分離構造を製造し得るのである。
Finally, by selectively oxidizing the surface portion 7 of the polycrystalline silicon film 4 filled in the deep groove G1 while leaving the upper space portion 6 left, the space portion 6 left in the upper portion of the polycrystalline silicon film 4 is first oxidized. 3 is capped by the oxide film 2c, and at this time, the nitride film 3 plays a role of relieving the stress at the time of forming the third oxide film 2c (see FIG. (E)) Through the above steps, it is possible to manufacture a groove-shaped separation structure with deep grooves as expected.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

こゝで、深溝による溝形分離構造を得るための従来例
方法においては、前記したように、深溝を埋め込む多結
晶シリコン膜にあつて、その表面に残存するくぼみを可
及的に平坦化させるために、エッチバック法を用いてい
るが、このエッチバック法においては、フォトレジスト
膜と多結晶シリコン膜とのエッチング速度をほゞ等しく
させるべく、エッチングガスとしての酸素および弗素系
ガスの混合比などの各エッチング条件を設定するのに手
間がかゝると云う不利があり、また、一方では同多結晶
シリコン膜の堆積膜厚を充分に厚くする必要があるなど
の問題点があつた。
Here, in the conventional example method for obtaining the groove-shaped separation structure by the deep groove, as described above, the depressions remaining on the surface of the polycrystalline silicon film filling the deep groove are flattened as much as possible. For this reason, the etch back method is used. In this etch back method, in order to make the etching rates of the photoresist film and the polycrystalline silicon film almost equal, the mixing ratio of oxygen and fluorine-based gas as etching gas is used. However, there is a disadvantage that it takes a lot of time to set each etching condition such as, and on the other hand, there is a problem that it is necessary to sufficiently increase the deposited film thickness of the polycrystalline silicon film.

この発明は、従来のこのような問題点を解消するため
になされたもので、その目的とするところは、酸化膜と
窒化膜とで覆われた深溝内を埋め込む多結晶シリコン膜
に対し、その表面平担化のためのエッチング手段とし
て、従来方法でのようなエッチバック法を用いずに、こ
れと同等,もしくは、それ以上の効果を得られるように
した,この種の半導体装置の製造方法,こゝでは、半導
体装置における溝形分離構造を得るための製造方法を提
供することである。
The present invention has been made in order to solve such a conventional problem, and an object of the present invention is to provide a polycrystalline silicon film filling a deep groove covered with an oxide film and a nitride film with A method for manufacturing a semiconductor device of this kind, which is capable of obtaining an effect equal to or higher than the etching back method as in the conventional method as an etching means for surface flattening The purpose of the present invention is to provide a manufacturing method for obtaining a groove-shaped isolation structure in a semiconductor device.

〔課題を解決するための手段〕[Means for solving the problem]

前記目的を達成するために、この発明に係る半導体装
置の製造方法は、酸化膜と窒化膜とで覆われた深溝内を
埋め込む多結晶シリコン膜に対し、その平担化のための
手段として、従来方法でのようなエッチバック法に替
え、選択酸化法を適用することで、同様に溝形分離構造
を得られるようにしたものである。
In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention provides a method for flattening a polycrystalline silicon film filling a deep groove covered with an oxide film and a nitride film, By applying a selective oxidation method instead of the etchback method as in the conventional method, a groove-shaped isolation structure can be obtained in the same manner.

すなわち,この発明は、素子間分離のために溝形分離
構造を用いた半導体装置の製造方法であつて、半導体基
板の主面上に、溝形分離領域に対応する部分を除いて第
1の酸化膜を形成し、かつこの第1の酸化膜をマスクに
して、半導体基板に所定深さの深溝を形成する工程と、
前記第1の酸化膜の除去後、前記深溝の内壁面,内底面
および半導体基板の表面に、第2の酸化膜および窒化膜
を順次に形成し、かつこれらの酸化膜および窒化膜で覆
われた深溝内にあつて、中心部表面に残存するくぼみの
下端部が、前記窒化膜の表面以上に位置する厚さに、多
結晶シリコン膜を堆積させて埋め込む工程と、前記多結
晶シリコン膜を半導体基板の表面以下の深さまで選択酸
化処理して、未酸化の多結晶シリコン膜との界面を平坦
にさせた第3の酸化膜を形成する工程と、前記第3の酸
化膜を除去し、前記第2の酸化膜および窒化膜で覆われ
た深溝内な上部に所定深さの空間部を残して、前記多結
晶シリコン膜の平坦にされた表面を露出させる工程と
を、少なくとも含むことを特徴とする半導体装置の製造
方法である。
That is, the present invention is a method of manufacturing a semiconductor device using a groove-shaped isolation structure for element isolation, which is the first method except for the portion corresponding to the groove-shaped isolation region on the main surface of the semiconductor substrate. Forming an oxide film and using the first oxide film as a mask to form a deep groove of a predetermined depth in the semiconductor substrate;
After removing the first oxide film, a second oxide film and a nitride film are sequentially formed on the inner wall surface, the inner bottom surface of the deep groove and the surface of the semiconductor substrate, and the second oxide film and the nitride film are covered with the oxide film and the nitride film. In the deep groove, the step of depositing and embedding a polycrystalline silicon film in a thickness such that the lower end of the recess remaining on the surface of the central portion is located above the surface of the nitride film; A step of selectively oxidizing the semiconductor substrate to a depth below the surface to form a third oxide film having a flat interface with an unoxidized polycrystalline silicon film, and removing the third oxide film, Exposing a flattened surface of the polycrystalline silicon film, leaving a space of a predetermined depth in an upper part inside the deep groove covered with the second oxide film and the nitride film. A method for manufacturing a characteristic semiconductor device.

〔作用〕[Action]

従つて、この発明方法においては、酸化膜と窒化膜と
で覆われた深溝内を埋め込む多結晶シリコン膜の堆積厚
さを、深溝の中心部表面に残存するくぼみの下端部が、
窒化膜の表面以上に位置する程度に設定しておき、この
状態で、多結晶シリコン膜を半導体基板の表面以下の深
さまで選択酸化処理するようにしたから、未酸化の多結
晶シリコン膜との界面を平坦にでき、かつまた、こゝで
の酸化部分を除去することによつて、この平坦にされた
表面を、深溝内の上部に所定深さの空間部を残して露出
できるのであり、このようにして、深溝内を埋め込む多
結晶シリコン膜の表面を平担化させ得るのである。
Therefore, in the method of the present invention, the deposited thickness of the polycrystalline silicon film filling the deep groove covered with the oxide film and the nitride film is determined by the lower end portion of the recess remaining on the surface of the central portion of the deep groove.
Since the polycrystalline silicon film is set so as to be positioned above the surface of the nitride film and the polycrystalline silicon film is selectively oxidized to a depth below the surface of the semiconductor substrate in this state, the polycrystalline silicon film is not oxidized with the unoxidized polycrystalline silicon film. The interface can be flattened, and by removing the oxidized portion here, the flattened surface can be exposed leaving a space of a predetermined depth in the upper part of the deep groove, In this way, the surface of the polycrystalline silicon film filling the deep trench can be made flat.

〔実 施 例〕〔Example〕

以下、この発明に係る半導体装置の製造方法の一実施
例につき、第1図を参照して詳細に説明する。
An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIG.

第1図(a)ないし(e)はこの実施例方法を適用し
た深溝による溝形分離構造を用いた半導体装置の主要な
製造工程の概要を順次模式的に示すそそれぞれに断面図
である。
FIGS. 1 (a) to 1 (e) are cross-sectional views each schematically showing the outline of main manufacturing steps of a semiconductor device using a groove-shaped isolation structure with deep grooves to which the method of this embodiment is applied.

すなわち,これらの第1図(a)ないし(e)に示す
実施例方法において、深溝による溝形分離構造を用いた
半導体装置は、まず、前記した従来例方法の場合と同様
に、半導体基板11の主面上に第1の酸化膜12aを形成し
た上で、溝形分離領域に第1の酸化膜12aを形成した上
で、溝形分離領域に対応する部分の酸化膜12aを選択的
にパターニング除去して開口させ、かつこのパターニン
グされた第1の酸化膜12aをマスクに用い、半導体基板1
1に異方性エッチングを施して所定深さの深溝G1を形成
する(第1図(a))。
That is, in the method of the embodiment shown in FIGS. 1A to 1E, the semiconductor device using the groove-shaped isolation structure by the deep groove is firstly processed by the semiconductor substrate 11 as in the case of the conventional method. Forming a first oxide film 12a on the main surface of the first oxide film 12a, forming a first oxide film 12a on the trench isolation region, and selectively removing a portion of the oxide film 12a corresponding to the trench isolation region. The semiconductor substrate 1 is removed by patterning to make openings and using the patterned first oxide film 12a as a mask.
1 is anisotropically etched to form a deep groove G 1 having a predetermined depth (FIG. 1 (a)).

ついで、前記マスクに用いた第1の酸化膜12aを除去
した後、前記深溝G1の内壁面,内底面を含む半導体基板
11の表面にあつて、同様に第2の酸化膜12bと窒化膜13
とを順次に形成し、さらに、これらの上に多結晶シリコ
ン膜14を堆積させて、これらの各膜12b,13で覆われた深
溝G1内を充分に埋め込むが、この場合,前記した従来例
方法においては、多結晶シリコン膜の堆積膜厚を厚くす
るほど,つまり、深溝G1の中心部表面に残存するくぼみ
G2が小さいほど好ましいものであつたが、この実施例方
法では、くぼみG2の下端部が前記窒化膜13の表面以上に
位置する程度の堆積厚さであれば充分である(同図
(b))。
Then, after removing the first oxide film 12a used for the mask, the semiconductor substrate including the inner wall surface and the inner bottom surface of the deep groove G 1 is removed.
Similarly, on the surface of 11, the second oxide film 12b and the nitride film 13 are formed.
Are sequentially formed, and a polycrystalline silicon film 14 is further deposited thereon to sufficiently fill the deep groove G 1 covered with each of the films 12b and 13. In the example method, the thicker the deposited thickness of the polycrystalline silicon film is, that is, the dent remaining on the surface of the central portion of the deep groove G 1.
The smaller G 2 is, the more preferable it is. However, in the method of this embodiment, it is sufficient if the deposition thickness is such that the lower end portion of the depression G 2 is located above the surface of the nitride film 13 (FIG. b)).

次に、前記多結晶シリコン膜14を半導体基板11の表面
以下になる深さまで選択的に酸化処理することによつ
て、第3の酸化膜12cを形成する(同図(c))。こゝ
で、この選択酸化処理に際し、前記半導体基板11に対し
ては、先にその表面を覆つている窒化膜13がマスクとし
て作用することになるもので、またこのとき、第3の酸
化膜12cの表面には、前記くぼみG2の形状を反映したく
ぼみG3が形成されることになるが、この第3の酸化膜12
cと未酸化の多結晶シリコン膜14との界面15aについて
は、これが平坦になる。
Next, the third oxide film 12c is formed by selectively oxidizing the polycrystalline silicon film 14 to a depth below the surface of the semiconductor substrate 11 (FIG. 7C). Here, in the selective oxidation treatment, the nitride film 13 covering the surface of the semiconductor substrate 11 first acts as a mask, and at this time, the third oxide film A depression G 3 reflecting the shape of the depression G 2 is formed on the surface of 12c. The third oxide film 12
The interface 15a between c and the unoxidized polycrystalline silicon film 14 becomes flat.

続いて、前記第3の酸化膜12cを適宜にエッチング除
去することにより、前記第2の酸化膜12bと窒化膜13と
で覆われた深溝G1内は、上部に所定深さの空間部16を残
して、露出された表面15bが平坦な多結晶シリコン膜14
によつて充填された状態になる(同図(d))。そし
て、このエッチングに際してもまた、前記第2の酸化膜
12bに対して、これを覆う窒化膜13がマスクとして作用
することになる。
Then, the third oxide film 12c is appropriately removed by etching, so that the inside of the deep groove G 1 covered with the second oxide film 12b and the nitride film 13 has a space 16 at a predetermined depth above. The exposed polycrystalline silicon film 14 has a flat exposed surface 15b.
Then, it is in a state of being filled (Fig. 4 (d)). Also, during this etching, the second oxide film is also formed.
The nitride film 13 that covers 12b acts as a mask.

最後に、前記と同様に、深溝G1内に上部の空間部16を
残して充填された多結晶シリコン膜14の表面15b部を選
択的に酸化処理することにより、こゝでは、上部に残さ
れた空間部16が第4の酸化膜12dによつてキャッピング
されるもので、このときにも、前記窒化膜13がこの第4
の酸化膜12dの形成時の応力を緩和するための役割を果
すものであり(同図(e))、以上の各工程を経て、所
期通りの深溝による溝形分離構造を製造し得るのであ
る。
Finally, similarly to the above, by selectively oxidizing the surface 15b portion of the polycrystalline silicon film 14 filled in the deep groove G 1 while leaving the upper space portion 16 left, the surface 15b portion is left in the upper portion. The formed space 16 is capped by the fourth oxide film 12d, and at this time, the nitride film 13 is also formed by the fourth oxide film 12d.
It plays a role of relieving the stress at the time of forming the oxide film 12d (FIG. 6 (e)), and the groove-shaped separation structure with the deep groove can be manufactured as desired through the above steps. is there.

従つて、この実施例方法の場合には、第2の酸化膜12
bと窒化膜13とで覆われた深溝G1内を埋め込む多結晶シ
リコン膜14の堆積厚さを、深溝G1の中心部表面に残存す
るくぼみG2の下端部が、窒化膜13の表面以上に位置する
程度に設定した状態で、この多結晶シリコン膜14を半導
体基板11の表面以下の深さまで選択的に酸化処理して、
第3の酸化膜12cを形成させるようにしたので、この第
3の酸化膜12cと未酸化の多結晶シリコン膜14との界面1
5aを極めて簡単に平坦にできるのであり、かつまた、こ
の第3の酸化膜12cを除去することによつて、この多結
晶シリコン膜14の平坦にされた表面15bを、深溝G1内の
上部に所定深さの空間部16を残して露出できるもので、
従来方法のように、エッチング条件などの設定に手間の
かゝるエッチバック法を用いることなく、これに替え
て、より一層簡単で手間のかゝらない既存の選択酸化法
により、こゝでの多結晶シリコン膜14の平担化を容易か
つ迅速に行なえるほか、この多結晶シリコン膜14の膜厚
自体も比較的薄くし得るのである。
Therefore, in the case of the method of this embodiment, the second oxide film 12
The deposition thickness of the polycrystalline silicon film 14 filling the inside of the deep groove G 1 covered with b and the nitride film 13 is set so that the lower end of the depression G 2 remaining on the surface of the central portion of the deep groove G 1 is In a state where the polycrystalline silicon film 14 is set to the above position, the polycrystalline silicon film 14 is selectively oxidized to a depth below the surface of the semiconductor substrate 11,
Since the third oxide film 12c is formed, the interface 1 between the third oxide film 12c and the unoxidized polycrystalline silicon film 14 is formed.
5a can be made extremely easy to be flat, and by removing the third oxide film 12c, the flattened surface 15b of the polycrystalline silicon film 14 can be moved to the upper part in the deep groove G 1 . It can be exposed leaving a space 16 of a predetermined depth,
Unlike the conventional method, it does not use a laborious etchback method for setting etching conditions, etc., but instead, it uses an existing selective oxidation method that is simpler and requires less labor, and can be used in many cases. In addition to flattening the crystalline silicon film 14 easily and quickly, the thickness of the polycrystalline silicon film 14 itself can be made relatively thin.

〔発明の効果〕〔The invention's effect〕

以上詳述したように、この発明によれば、素子間分離
のために溝形分離構造を用いた半導体装置の製造方法に
おいて、パターニングされた第1の酸化膜をマスクに、
半導体基板の溝形分離領域に対応する部分に深溝を選択
的に形成し、かつこの深溝を含む基板表面を第2の酸化
膜と窒化膜とで覆うと共に、これらの各膜で覆われた深
溝内を埋め込む多結晶シリコン膜の堆積厚さを、深溝の
中心部表面に残存するくぼみの下端部が、窒化膜の表面
以上に位置する程度に設定しておき、この状態で、多結
晶シリコン膜を半導体基板の表面以下の深さまで選択酸
化処理して、第3の酸化膜を形成させるようにしたの
で、この第3の酸化膜と未酸化の多結晶シリコン膜との
界面を平坦にでき、また、こゝでの第3の酸化膜部分を
除去することによつて、この平坦にされた表面を、深溝
内の上部に所定深さの空間部を残して露出できるもの
で、このようにして従来方法の場合のように、深溝内を
埋め込む多結晶シリコン膜の平担化手段としての,エッ
チング条件などの設定に手間のかゝるエッチバック法を
用いることなしに、これに替えて、より一層簡単な手段
である既存の選択酸化法により、この多結晶シリコン膜
の平担化を容易かつ迅速に行ない得られ、併せて、深溝
内への多結晶シリコン膜の堆積厚さについても、これを
薄くできて製造工程の簡略化が可能であるなどの優れた
特長を有するものである。
As described above in detail, according to the present invention, in the method of manufacturing a semiconductor device using the trench isolation structure for element isolation, the patterned first oxide film is used as a mask,
A deep groove is selectively formed in a portion corresponding to the groove-shaped isolation region of the semiconductor substrate, the substrate surface including the deep groove is covered with a second oxide film and a nitride film, and the deep groove covered with each of these films is formed. The thickness of the deposited polycrystalline silicon film is set so that the lower end of the recess remaining on the surface of the central portion of the deep groove is located above the surface of the nitride film. Is selectively oxidized to a depth below the surface of the semiconductor substrate to form a third oxide film, so that the interface between the third oxide film and the unoxidized polycrystalline silicon film can be made flat, Further, by removing the third oxide film portion here, the flattened surface can be exposed in the upper part of the deep groove leaving a space portion of a predetermined depth. As in the case of the conventional method, the poly-silicon Instead of using a complicated etching back method for setting etching conditions etc. as a flattening means for the film, instead of this, the existing selective oxidation method, which is a simpler means, is used to replace this polycrystal. The silicon film can be flattened easily and quickly, and the deposition thickness of the polycrystalline silicon film in the deep groove can be thinned to simplify the manufacturing process. It has the following features.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)ないし(e)はこの発明の一実施例方法を
適用した深溝による溝形分離構造を用いた半導体装置の
主要な製造工程の概要を順次摸式的に示すそれぞれに断
面図であり、また、第2図(a)ないし(e)は従来例
方法での同上深溝による溝形分離構造を用いた半導体装
置の主要な製造工程の概要を順次摸式的に示すそれぞれ
に断面図である。 11……半導体基板、12aないし12d……第1ないし第4の
酸化膜、13……窒化膜、14……多結晶シリコン膜、15a
……平坦にされた未酸化界面、15b……平坦にされた多
結晶シリコン膜表面、16……空間部。 G1……溝形分離のための深溝、G2……多結晶シリコン膜
表面のくぼみ部、G3……第3の酸化膜表面のくぼみ部。
FIGS. 1 (a) to 1 (e) are schematic cross-sectional views showing the outline of main manufacturing steps of a semiconductor device using a groove-shaped isolation structure with deep grooves to which the method of an embodiment of the present invention is applied. 2 (a) to 2 (e) are schematic sectional views showing the outline of main manufacturing steps of a semiconductor device using a groove-shaped separation structure with deep grooves in the conventional method. It is a figure. 11 ... Semiconductor substrate, 12a to 12d ... First to fourth oxide film, 13 ... Nitride film, 14 ... Polycrystalline silicon film, 15a
... flattened unoxidized interface, 15b ... flattened polycrystalline silicon film surface, 16 ... space. G 1 ...... Deep groove for groove shape separation, G 2 …… Dimple on the surface of polycrystalline silicon film, G 3 …… Dimple on the surface of third oxide film.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】素子間分離のために溝形分離構造を用いた
半導体装置の製造方法であつて、半導体基板の主面上
に、溝形分離領域に対応する部分を除いて第1の酸化膜
を形成し、かつこの第1の酸化膜をマスクにして、半導
体基板に所定深さの深溝を形成する工程と、前記第1の
酸化膜の除去後、前記深溝の内壁面,内底面および半導
体基板の表面に、第2の酸化膜および窒化膜を順次に形
成し、かつこれらの酸化膜および窒化膜で覆われた深溝
内にあつて、中心部表面に残存するくぼみの下端部が、
前記窒化膜の表面以上に位置する厚さに、多結晶シリコ
ン膜を堆積させて埋め込む工程と、前記多結晶シリコン
膜を半導体基板の表面以下の深さまで選択酸化処理し
て、未酸化の多結晶シリコン膜との界面を平坦にさせた
第3の酸化膜を形成する工程と、前記第3の酸化膜を除
去し、前記第2の酸化膜および窒化膜で覆われた深溝内
の上部に所定深さの空間部を残して、前記多結晶シリコ
ン膜の平坦にされた表面を露出させる工程とを、少なく
とも含むことを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device using a trench isolation structure for element isolation, comprising: a first oxide on a main surface of a semiconductor substrate except a portion corresponding to the trench isolation region; A step of forming a film and using the first oxide film as a mask to form a deep groove of a predetermined depth in the semiconductor substrate; and after removing the first oxide film, an inner wall surface, an inner bottom surface, and A second oxide film and a nitride film are sequentially formed on the surface of the semiconductor substrate, and the lower end portion of the recess remaining on the surface of the center portion in the deep groove covered with the oxide film and the nitride film is
A step of depositing and embedding a polycrystalline silicon film to a thickness located above the surface of the nitride film, and performing a selective oxidation treatment of the polycrystalline silicon film to a depth below the surface of the semiconductor substrate to obtain an unoxidized polycrystalline film Forming a third oxide film having a flat interface with the silicon film, removing the third oxide film, and providing a predetermined upper portion in the deep groove covered with the second oxide film and the nitride film. And a step of exposing the flattened surface of the polycrystalline silicon film while leaving a space of a depth, at least.
JP1047015A 1989-02-28 1989-02-28 Method for manufacturing semiconductor device Expired - Fee Related JP2556128B2 (en)

Priority Applications (1)

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JP1047015A JP2556128B2 (en) 1989-02-28 1989-02-28 Method for manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
JP1047015A JP2556128B2 (en) 1989-02-28 1989-02-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02226742A JPH02226742A (en) 1990-09-10
JP2556128B2 true JP2556128B2 (en) 1996-11-20

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JP (1) JP2556128B2 (en)

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JP5691074B2 (en) 2008-08-20 2015-04-01 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783045B2 (en) * 1985-04-02 1995-09-06 ソニー株式会社 Method for manufacturing semiconductor device
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