JP2555787Y2 - Digital storage oscilloscope - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention relates to a digital storage oscilloscope that sets a vertical axis position with one variable resistor.

(Prior art) Conventionally, in a digital oscilloscope, as a variable resistor for setting a vertical axis position of a display waveform, a vertical axis variable resistor for real display, and digitalized data of an input signal to be observed are used. A vertical axis variable resistor for setting the vertical axis position when reading and displaying the stored contents of the acquisition memory, and a vertical axis position when reading and displaying the contents of the reference memory storing the data stored in the acquisition memory Three variable resistors of a vertical axis variable resistor for setting are provided independently on the panel surface.

(Problems to be Solved by the Invention)) Therefore, since three variable resistors are provided on the panel surface, a large amount of space is required and the panel area is increased.

The present invention shares the vertical variable resistor,
An object of the present invention is to provide a digital storage oscilloscope that can reduce the panel area by using only one vertical axis variable resistor.

(Means for Solving the Problems) In the digital storage oscilloscope of the present invention, the acquisition storage means 1 for storing data corresponding to the input signal to be observed and the acquisition storage means 1 for data corresponding to the input signal to be observed. First instructing means 2 for instructing storage, reference storage means 3, second instructing means 4 for instructing transfer and storage of data stored in acquisition storage means 1 to reference storage means 3,
Display storage means 5, third instruction means 6 for instructing the storage data of the acquisition storage means 1 and the storage data of the reference storage means 3 to be stored in the display storage means 5, and a fourth instruction means for instructing real waveform display. A digital storage comprising an instruction means 7 and capable of selectively reading a real waveform display and a storage content of the display storage means 5 at a constant speed and selectively displaying a waveform corresponding to data stored in the display storage means 5 In the oscilloscope, one variable resistor 8 for setting a vertical axis position of a display waveform, and one variable resistor 8 for setting by the first indicating means 2, the second indicating means 4, the third indicating means 6, and the fourth indicating means 7 Variable resistor 8
Slider position information storage means 9 for individually storing the respective slider position information, and slide position information corresponding to each waveform display instruction in synchronization with the waveform display instruction when displaying a waveform. It is characterized by comprising reading means 10 for reading from the child position information storage means 9 and display position control means 11 for displaying a waveform at the vertical axis position associated with the read slider position information.

(Operation) According to the digital storage oscilloscope of the present invention configured as described above, when the storage instruction of the data corresponding to the input signal to be observed is stored in the acquisition storage unit 1, the data stored in the acquisition storage unit 1 is stored in the reference storage unit. 3 shows the position information of the slider of the variable resistor 8 at the time of a transfer storage instruction and at the time of an instruction to store the storage data of the acquisition storage means 1 and the storage data of the reference storage means 3 in the display storage means 5, respectively. The respective slider position information storage means 9 is stored separately in the slider position information storage means 9 and the slider position information corresponding to each waveform display instruction is read out from the slider position information storage means 9 in synchronization with the waveform display instruction at the time of waveform display. And the waveform is displayed at the vertical axis position associated with the read slider position information under the control of the display position control means 10. In order, a variable resistor for setting the vertical axis position will be requires only one.

(Examples) Hereinafter, the present invention will be described with reference to examples.

FIG. 2 is a block diagram showing the configuration of one embodiment of the present invention.

In FIG. 2, reference numeral 21 denotes a variable attenuator that receives an input signal to be observed, reference numeral 22 denotes a vertical axis preamplifier, and reference numeral 23 denotes a CR.
A vertical axis final stage amplifier for driving T24, a reference numeral 25 is a trigger amplifier for generating a horizontal axis synchronization signal, a reference numeral 26 is a sweep circuit for sweeping the horizontal axis, and a reference numeral 27 is a horizontal axis final stage for driving the CRT24. Reference numeral 28 denotes a buffer amplifier that amplifies the output of the vertical axis preamplifier 22, reference numeral 29 denotes an A / D converter that digitizes an input signal to be observed, and reference numeral 30 denotes digital data output from the A / D converter 29. An acquisition memory to store.

Reference numeral 31 ₁ instructs the one of the storage instruction to store the digital data from the real mode display and A / D converter 29 for real display by processing the observed input signal in an analog state into the acquisition memory 30 real / storage instruction switch, reference numeral 31 ₂ stores the contents of the hold instruction switch, reference numeral 31 ₃ acquisition memory 30 for holding digital data stored in the acquisition memory 30 stops the storage of digital data in the acquisition memory reference instruction switch for instructing to store the reference memory 40 _1, reference numeral 31 ₄ denotes a reference display instruction switch for instructing to the waveform display corresponding to the digital data stored in the reference memory 40 _1, respectively It is provided on the operation panel 31.

Reference numeral 32 denotes a variable resistor for setting a vertical axis position, which is provided on the operation panel 31. 33 is a variable resistor
This is an A / D converter that converts 32 outputs to digital data.

Reference numeral 34 denotes an input port for taking in outputs of switches provided on the operation panel 31 and digital data from the A / D converter 33, and reference numeral 35 denotes an input from the input port 34 and a program stored in the ROM 36. A CPU for calculating the waveform data and controlling the digital storage oscilloscope in accordance with
Reference numeral 37 denotes a RAM for storing data, and reference numeral 38 denotes an output port. The input port 34, the CPU 35, the ROM 36, the RAM 37, and the output port 38 constitute a microcomputer for controlling a digital storage oscilloscope.

Code 39 for display for displaying a waveform corresponding to the digital data stored in the acquisition memory 30 memory, 40 ₂ for displaying a waveform corresponding to the digital data stored in the reference memory 40 ₁ Reference waveform display memory, reference numeral 41 denotes display memory 39
Selector for selecting one of the stored contents of the storage contents and reference display memory 40 _2, reference numeral 42 is a D / A converter for converting the output of the selector 41 into an analog signal, reference numeral 43 is a D / A converter 42 Analog signal and analog switch 49 described later
The output from the adder 43 is supplied to the vertical axis preamplifier 22 to apply a bias to the output of the vertical axis preamplifier 22.

Reference numeral 44 denotes a D / A converter for converting data corresponding to the output of the variable resistor 32 output from the output port 38 into an analog signal, and reference numerals 46, 47, and 48 denote hold circuits, and the hold circuit 46 is a real circuit. / Resistor at run / 32
Hold circuit 47 holds the value corresponding to the setting data of the variable resistor 32 during storage hold, and the hold circuit 48 sets the variable resistor 32 during the reference display. This is a hold circuit that holds a value corresponding to data. Here, there is shown a case where the storage of the data in the acquisition memory 30 is not stopped during the run, and the waveform corresponding to the stored digital data is displayed without stopping.

Reference numeral 45 denotes an analog switch that time-divides the analog signal output from the D / A converter 44 and selectively supplies the analog signals to the hold circuits 46, 47, and 48. Reference numeral 49 denotes an output from the hold circuit 46 and the hold circuit 47. An analog switch that selects and outputs one of the output from the hold circuit 48 and the output from the hold circuit 48, the output from the analog switch 49 is supplied to the adder 43,
The output from the converter 42 is added.

The operation of the present embodiment configured as described above will be described with reference to the flowchart of FIG.

First, the state of the switches provided on the operation panel 31 is read and stored in the panel switch group data area formed in the RAM 37 (step S ₁ ). Step S ₁
Followed by the output of the variable resistor 32, that is, the output digital data from the A / D converter 33 is read and stored in the corresponding area of the vertical axis position data area formed in RAM 37 (step S ₂₎ . The vertical axis position data area of the RAM 37 is a real / storage / run area for storing the setting data of the variable resistor 32 at the time of real / storage / run, and the variable resistor 32 at the time of storage hold.
And a reference area for storing the setting data of the variable resistor 32 at the time of the reference display. Following step S _2, control of each part is performed under the control of the CPU, respectively (step S _3), followed by the step S ₁ is executed.

For Step S ₂ is described by Figure 4.

D / A converted slider position of the variable resistor 32 is read (step S _21), then real indicated by real / storage instruction switch 31 _1, that is, whether the real mode has been instructed is determined ( step S _22),
A Following step S ₂₂ when it is determined that real-mode
/ D output whether there is a change in digital data converter 33 is checked (step S _23). Check of step S ₂₃ is done by comparing the digital data stored in the real / Storage / run area of RAM 37.

When a change in the step S ₂₃ is judged that there is are summed to digital tool data stored variation data in real / Storage / run area of RAM 37 (step S _24), the addition result is RAM 37 Stored in the real / storage / run area, the contents of the real / storage / run area of the RAM 37 are updated (step
S _25).

Hold instruction switch 31 is followed to step S ₂₂ when it is judged not in real mode in step S _{22 1}
Hold instruction, that is, whether the hold mode is designated is checked by (step S _26).
If it is judged not in the hold mode in step S ₂₆ is the case of the run mode, step S ₂₃ is executed following step S _26. If it is determined that the hold mode in step S _26, after the specified hold mode following step S _26, the data capture is checked whether the first (Step S _27).

When it is determined that the first time in step S ₂₇ is set to a value corresponding to the tube surface central data storage hold area RAM37 after step S ₂₇ is CRT 24 (step S _28). When it is determined that the second time or more in step S _27, the reference indicated by the reference instruction switch 31 ₃ Following step S _27,
That is, whether the reference mode is specified is checked (step S _29). Step when it is determined that the reference mode in step S ₂₉
Following S ₂₉ whether or not there is a change in the output digital data of the A / D converter 33 is checked (step S _30). Check of step S ₃₀ is done by comparing the digital data stored in the reference area of the RAM 37.

When a change in the step S ₃₀ is judged that there is are summed in the digital data stored variation data in the reference area of the RAM 37 (step S
_31), the addition result is stored in the reference area of the RAM 37, the contents of the reference area of the RAM 37 is updated (step S _32).

If it is judged not in reference mode in step S ₂₉ whether there is a change subsequent to step S ₂₉ to output the digital data of the A / D converter 33 is checked (step S _33). Check of step S ₃₃ is done by comparing the digital tool data stored in the storage hold area of RAM 37.

When a change in the step S ₃₃ is judged that there is are summed in the digital data stored variation data storage hold area of RAM 37 (step S _34), the storage hold area of addition result RAM 37 is stored, the contents of the storage hold area RAM37 are updated (step S _35).

Therefore, obvious as hold mode in the following steps: Step S ₂₇ is when the first A / D conversion output uptake after holding the vertical axis are summed in the center position of the CRT surface, when the second vertical axis The position is changed from the center position, and from the third time on, the vertical axis position is changed from the previous vertical position,
The vertical axis position is stored in the storage hold area of the RAM 37.

In a mode other than the hold mode, when the vertical axis position designated by the variable resistor 32 is changed, the changed vertical axis position is stored in the corresponding area of the RAM 37.

Step S ₂₅ , Step S ₂₈ , Step S ₃₂ , Step S
When ₃₅ is executed, the control of each part of the step S ₃ is executed.

Next, the control of each unit will be described sequentially with respect to the control of the vertical axis position, the control of the analog switch, and the waveform output control according to the flowcharts of FIGS.

In the control of the vertical axis position, is checked whether the real mode has been instructed (step S _41), when it is determined that the real mode has been instructed in step S ₄₁ the real / Storage / run area RAM37 The stored data is converted to an analog signal by the D / A converter 44, and the converted analog signal is held by the hold circuit 46 via the analog switch 45 (step _S42 ). Therefore, the hold circuit 46 holds a signal of a level corresponding to the information stored in the real / storage / run area of the RAM 37.

When the real mode is judged to be not instructed in step S _41, or hold mode or not after step S ₄₁ is checked (step S _43), step S when it is determined that the hold mode _{After 43} , it is checked whether or not the mode is the reference display mode (step _S44 ). Step If it is not determined reference display mode in S _44, the hold mode is a followed by the data stored in the storage hold area RAM37 is D / A converter in step S ₄₄ 44
Is converted into an analog signal, and the converted analog signal is held by the hold circuit 47 via the analog switch 45 (step _S45 ). Therefore, hold circuit 4
7, the signal of the level corresponding to the information stored in the storage hold area of the RAM 37 is held.

When it is determined that the reference display mode in step S _44, after step S ₄₄ RAM
Data stored in 37 reference areas is D / A
The analog signal is converted by the converter 44 into an analog signal, and the converted analog signal is
Is held (step _S46 ). Therefore, the signal of the level corresponding to the information stored in the reference area of the RAM 37 is held in the hold circuit 48.

Next, in the control of the analog switch 49, it is checked whether or not the real mode is instructed (step
_S51 ) When it is determined that the real mode is instructed, the output of the hold circuit 46 is supplied to the adder 43 via the analog switch 49 (step _S52 ). Therefore, in this case, a signal of a level corresponding to the position of the slider of the variable resistor 32 in the real mode is supplied to the adder 43. Following step S _52, the process proceeds to the next waveform output control.

Whether the hold mode or subsequent to step S ₅₁ when the real mode is judged to be not instructed is checked in step S ₅₁ (step S _53). If it is judged not in the hold mode in step S ₅₃ is a run mode, step S following step S _53
52 is executed.

Whether the reference display mode Following step S ₅₃ when it is determined that the hold mode is checked in step S ₅₃ (step S _54).
If it is determined in step _S54 that the mode is not the reference display mode, the output of the hold circuit 47 is added to the adder through the analog switch 49 following step _S54 .
It is supplied to 43 (step _S55 ). Therefore, in this case, a signal of a level corresponding to the position of the slider of the variable resistor 32 during storage hold is supplied to the adder 43.

If it is determined in step _S54 that the display mode is the reference display mode, the analog switch 49 is switched in a time-division manner following step _S54 , so that the output of the hold circuit 47 and the output of the hold circuit 48 are alternately switched to analog. The signal is supplied to the adder 43 via the switch 49 (step
_S56 ). Therefore, in this case, the signal of the corresponding level of the slider position of the variable resistor 32 during the storage hold and the signal of the corresponding level of the slider position of the variable resistor 32 during the reference display are alternately switched and added. Table 43
This state is schematically shown as a pulse waveform b in FIG. 6 (b).

Step S _55, following the step S _56, the process proceeds to the next waveform output control.

Next, in the waveform output control, it is checked whether or not the mode is the real mode (step _S61 ). If it is determined in the step _S61 that the mode is the real mode, the storage mode is not entered and the real-time waveform display is displayed on the CRT screen. This is performed (step _S62 ). In this case, the D / A converter 42 does not generate an output, and the output of the hold circuit 46 is
The output of the hold circuit 46 is biased, and the vertical axis position is controlled to the level of the analog signal held by the hold circuit 46.

If it is determined in step _S61 that the current mode is not the real mode, the current mode is the storage mode, and the digital data converted by the A / D converter 29 is stored in the acquisition memory 30 (step _S63 ). Is checked (step _S64 ). If it is determined in step _S64 that the mode is not the hold mode, the mode is the run mode, the digital data is sequentially stored in the acquisition memory 30, and the digital data stored in the acquisition memory 30 is sequentially transferred to the display memory 39. Is performed (step _S65 ). The data stored in the display memory 39 is read at a constant speed, and the read data is supplied to a D / A converter 42 via a selector 41 and converted into an analog signal. The signal obtained by adding the output of the hold circuit 46 is supplied to the vertical axis preamplifier 22 and biased, and the waveform is displayed on the CRT screen with the amplified output of the vertical axis final stage amplifier 23. The display waveform in this case is a waveform obtained by digitizing the input signal to be observed once and converting it back to an analog signal, but is substantially the same as that in the real mode, and the vertical axis position of the display waveform is Corresponds to the level of the signal held in the hold circuit 46.

If it is determined in step _S64 that the current mode is the hold mode, the digital data display memory 39 stored in the acquisition memory 30 is continued after step _S64.
Is stopped (step _S66 ), and it is checked whether the reference display mode is instructed (step _S67 ). If it is determined in step _S67 that the reference display mode has not been instructed, the acquisition of the digital data into the acquisition memory 39 has been stopped, and the digital data stored in the acquisition memory 39 before the stop of the acquisition of the digital data. Is displayed on the CRT screen. The vertical axis position in this case is set by the output of the hold circuit 47 in step S _55. Step S
_If it is determined in ₆₇ that the reference display mode has been designated, the reference designation switch
31 ₃ whether the reference instruction has been checked by (step S _68). Transfer the digital data when the reference instruction is determined to have been made that are stored in the acquisition memory 30 following the step S ₆₈ in step S ₆₈ is in the reference memory 40 _1,
Is stored (step _S69 ), and then the reference memory 4
0 digital data stored in ₁ transfer the reference display memory 40 ₂ is stored (Step S _70). When the reference instruction is judged not performed step S ₇₀ subsequent to the step S ₆₈ is executed in step S _68. In step _S70 , reference display memory 4
0 ₂ content is read at a constant speed, it is alternately selected by the selector 41 is converted into an analog signal by the D / A converter 42. The output of the hold circuit 47 and the output of the hold circuit 48 are selected by the analog switch 49 in synchronization with the converted analog signal and the selection by the selector 41,
The signal is output, added by the adder 43, and supplied to the vertical axis preamplifier 22. Therefore, a waveform corresponding to the digital data on the screen of the CRT on which is stored in the waveform and the reference memory 40 ₁ corresponding to the digital data stored in the acquisition memory 39 is displayed. If this state is schematically shown, it is alternately displayed as shown by a waveform a in FIG. 6 (b). And vertical position of the waveform to the memory contents of the acquisition memory 30 in this case, the vertical axis position of the waveform relative to the stored contents of the reference memory 40 ₁ would be set by the outputs of the hold circuit 48 of the hold circuit 47 , Step
Each of which is set to each other in the waveform do not overlap easily seen in S ₂₇ ~ step S _35.

(Effects of the Invention) As described above, according to the present invention, one variable resistor for setting the vertical axis position is provided, and when the data storage instruction to the acquisition storage means is issued, the data storage instruction to the reference storage means is issued. Sometimes, when the data is stored in the display storage means, the position information of the slider of the variable resistor is separately stored, and the slider position information corresponding to the display instruction is synchronized with the waveform display instruction when displaying the waveform. Is read and the waveform is displayed at the vertical axis position associated with the read slider position information, so that only one variable resistor is required to set the vertical axis position, and the operation panel area is small. It has the effect of ending.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing the configuration of the present invention. FIG. 2 is a block diagram showing a configuration of one embodiment of the present invention. 3 to 5, FIG. 6 (a) and FIG. 7 are flowcharts for explaining the operation of one embodiment of the present invention. FIG. 6B is a schematic view for explaining the operation of the embodiment of the present invention. 1 ... acquisition storage means, 2 ... first instruction means,
3 ... reference storage means, 4 ... second instruction means, 5
... Display storage means, 6... Third instruction means, 7.
Indicating means, 8 ... variable resistor, 9 ... slider position information storage means, 10 ... readout means, 11 ... display position control means.

Claims (1)

(57) [Scope of request for utility model registration] 1. An acquisition storage means for storing data corresponding to an observed input signal, a first instruction means for instructing that data corresponding to an observed input signal be stored in the acquisition storage means, and a reference storage. Means, second instructing means for instructing transfer and storage of data stored in the acquisition storage means to the reference storage means, display storage means, and storage for display data stored in the acquisition storage means and storage data in the reference storage means. Third instruction means for instructing storing in the means,
A fourth instruction means for instructing a real waveform display, wherein the real waveform display and the storage contents of the display storage means are read out at a constant speed and the waveform display corresponding to the data stored in the display storage means is selectively performed. And a variable resistor for setting the vertical position of the display waveform, and a variable resistor for setting the vertical axis position of the display waveform when the first, second, third, and fourth indicating means indicate. Slider position information storage means for separately storing the slider position information of the variable resistor, and slider position information corresponding to each waveform display instruction in synchronization with the waveform display instruction when displaying a waveform. A reading means for reading from the slider position information storage means; and a display position control means for displaying a waveform at a vertical axis position associated with the read slider position information. Digital storage oscilloscope, characterized in that the.