JPS6355931B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Lissage display device for observing various phenomena by drawing a Lissage figure on a CRT screen, and in particular, a Lissage display device that is most suitable for a vector electrocardiograph that displays a Lissage figure as a vector electrocardiogram. Regarding.

Generally, with a vector electrocardiograph, the electrical phenomena of the heart are recorded as a Lissage figure (vector electrocardiogram) on a CRT.
By drawing on the screen, we observe phenomena.

However, in conventional vector electrocardiographs, only the Lissage figure, that is, the vector electrocardiogram, is displayed on the CRT, and it is not possible to know the relationship between the raw signals forming the vector electrocardiogram and the vector electrocardiogram. . Furthermore, when electrical phenomena are depicted as vectors, temporal elements do not appear on the CRT screen at all, so interpreting vector electrocardiograms tends to require skill.

In view of this, the present invention displays raw signals forming a Lissage figure as a vector electrocardiogram on a CRT screen at the same time as the Lissage figure.
A novel Lissage display device that displays temporal elements on each displayed waveform, specifically:
The object of the present invention is to provide a new Lissage display device that displays a point representing a common time or a line that changes with time on the display waveform of a Lissage figure and an elementary signal by controlling the brightness of a CRT.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram schematically showing a resurge display device according to the present invention, and FIG. 2 is a display example thereof.

In FIG. 1, reference numeral 1 denotes a measurement and processing section that measures electrical phenomena of the heart and converts them into digital signals, and data is transferred to an X memory 2 and a Y memory 3 as necessary. Then, the data in the X memory 2 and Y memory 3 is transferred to the D/A converters 4 and 5, respectively.
is converted into an analog signal, and the output thereof is input to the selection means 6. The selection means 6 further receives a sweep signal from the sweep signal generation circuit 7, and selectively outputs this sweep signal and the outputs of the D/A converters 4 and 5 as a horizontal deflection signal H and a vertical deflection signal V. These deflection signals are input to the CRT8.
Therefore, on the CRT8 screen, as shown in Figure 2A, the signals stored in the X memory 2 and Y memory 3 are displayed horizontally and vertically, respectively, and the Lissage figure formed based on these signals is simultaneously displayed. Is displayed.

This circuit also includes a brightness signal generation circuit 9 that generates a brightness signal that changes the brightness of the CRT, and brightness control means 10 that controls the brightness signal generation circuit 9, including means for setting the timing at which the brightness should be changed.
These circuits change the brightness of a part of the displayed waveform to display a point representing a common time or a line that changes with time as shown in Figure 2 B and C. There is.

Next, the present invention will be explained in more detail based on the embodiment shown in FIG.

In FIG. 3, reference numeral 11 indicates a first analog signal a and a second analog signal b which measure a phenomenon and form a Lissage figure.
a measurement and processing unit that converts into a digital signal; 1
2 and 13 are the first and second
X memory and Y memory each storing digital signals of
Memories 14 and 15 are D/D converters that convert data read from both memories 12 and 13 into analog signals.
A converters 16 and 17 are a horizontal reference position setting circuit and a vertical reference position setting circuit that set the reference positions in the horizontal and vertical directions when displaying on the CRT18 screen.
The outputs of D/A converters 14 and 15 are applied to V _XO and V _YO , respectively.
Voltages V _X and V _Y on which V ₁ and V ₂ are superimposed are output.

Further, 19 is a display address counter that specifies the addresses of the X memory 12 and Y memory 13 via address buses A and B and controls reading, and 20 is a time base generation decoder 21, a ternary counter 22, and an AND gate 23. , 24, 25, an OR gate 26, and an inverter 27, and a readout clock applied to the display address counter 19.
Read clock generation circuit that generates CLR, 2
8 is a ternary counter; 29 is a ternary counter 30 and a display switching decoder 31;
2, a first input signal a stored digitally in
A display switching signal _T1 indicating a period for displaying the second input signal b digitally stored in the Y memory 13, a display switching signal _T2 indicating a period for displaying the second input signal b digitally stored in the Y memory 13, and the first and second input signals a, Display switching signal indicating the period for displaying the Lissage figure formed by b
₃₂ is a sweep signal generation circuit that generates a sawtooth wave synchronized with clock pulse P ₂ as a sweep signal V _S ; 33
are transmission gates 34, 35, 36,
37 and OR gates 38 and 39, the outputs _V
This is a gate circuit group that inputs V _Y and a sweep signal V _S and selectively outputs this input as a horizontal deflection signal H and a vertical deflection signal V to the CRT 18 according to display switching signals T ₁ , T ₂ , and T ₃ . .

Furthermore, 40 is a brightness modulation setting means for setting the timing at which the brightness of the CRT should be changed, and 41 is a comparison circuit comprising a matching circuit 42 and a single-shot circuit 43, and comparing the contents of the display address counter with the contents of the brightness modulation setting means. A luminance signal generating circuit 44 generates a luminance signal F for changing the luminance of the CRT 18.

Next, the operation of this embodiment is shown in a display example in Fig. 2 and in Fig. 4.
This will be explained with reference to the timing chart shown in the figure.

First, the clock pulse P ₁ (FIG. 4 C) is divided into 1/3 by the ternary counter 28 and becomes the clock pulse P ₂
(Figure 4 D). This clock pulse _P2 is input to the ternary counter 30 in the display switching signal generation circuit 29 , and the output of this ternary counter 30 is input to the display switching decoder 31, as shown in FIG. Display switching signals T ₁ , T ₂ , and T ₃ are obtained. As described above, the display switching signals T ₁ , T ₂ , and T ₃ are signals indicating the period for displaying the first input signal a, the second input signal b, and the Lissage figure, respectively.

In addition, the sweep signal generation circuit 32 generates a clock pulse.
Input P ₂ and generate a sawtooth voltage V _S synchronized with it.

Incidentally, the output of the ternary counter 28 to which the clock pulse P ₁ is input is input to the time base generation decoder 21, and this decoder generates a signal T _B (FIG. ) is created. This signal T _B has a pulse width that is 1/3 that of the display switching signals T ₁ , T ₂ , and T ₃ . While this signal T _B is at "H", the read reference clock CL (see FIG. 4) passes through the AND gate 23 and is input to the AND gate 24.
Then, during the period when the display switching signal _T3 is "L", that is, during the period when the display switching signal _T1 or _T2 is "H", the readout reference clock CL is passed through the AND gate 24 and the OR gate 26 as the readout clock CLR for display. It is input to the address counter 19. On the other hand, during the period when the display switching signal _T3 is "H", a signal obtained by dividing the reading reference clock CL into 1/3 via the ternary counter 22 is sent to the AND gate 25 and
It is input to the display address counter 19 via the OR gate 26 as the read clock CLR.
In this case, the readout period will be determined by the display switching signal _T3 .

Here, since the display address counter 19 specifies the addresses of the X memory 12 and Y memory 13 according to the contents and reads the data, the display switching signal as shown in FIG. The period when T ₁ or T ₂ is “H”, i.e. the first or second period
During the period in which the input signals a and b are displayed, data is read out from the respective memories 12 and 13 according to the read reference clock CL during the latter 1/3 of the display period, and the display switching signal _T3 is During the period "H", that is, the period in which the Lissage figure is displayed, data is read out from the respective memories 12 and 13 in accordance with the clock divided by 1/3 of the read reference clock CL throughout the display period.

Therefore, first, when the display switching signal _T1 becomes "H" (period A), the transmission gates 34 and 36 in the gate circuit group 33 are turned on. Therefore, the sawtooth voltage V _S is output as the vertical deflection signal V as shown in FIG. 4B. On the other hand, in the horizontal deflection signal H, in the first 2/3 of the A period, the voltage _V The voltage VX obtained by superimposing the reference voltage _VX0 on the voltage _V1 obtained by D/A converting the voltage _VX0 is output as the horizontal deflection signal H (FIG. 4A). For this reason, A
In the period, the first input signal a forms a Lissage figure with the Y coordinate axis in the vertical direction as shown in Fig. 2A.
is displayed.

Next, during the B period when the display switching signal _T2 is "H", the transmission gates 35 and 37 in the gate display group 33 are turned on, so the sawtooth voltage V _S is output as the horizontal deflection signal H. (Figure 4a). Then, in the first 2/3 of the B period, the voltage V _Y0 indicating the horizontal reference position is Y0, and in the latter 1/3 of the B period, the voltage V
Since the voltage V Y obtained by D/A-converting the data read from the memory 13 _and the reference voltage V _Y0 superimposed on the voltage V _Y is output as the vertical deflection signal V (Fig. 4 b), the As shown in FIG. 2A, the raw second input signal b forming a Lissage figure with the X coordinate axis in the horizontal direction is displayed.

Furthermore, during the C period when the display switching signal _T3 is "H", the transmission gates 34 and 35 in the gate circuit group 33 are turned off, and the transmission gates 36 and 37 are turned on, so that the horizontal and vertical deflection signals H, V The sawtooth voltage V _S is never output. In other words, the voltage V _X obtained by D/A converting the data read from the X memory 12 and _the reference voltage _V
A voltage V Y obtained by superimposing a reference voltage V _Y0 on a voltage V ₂ obtained by D/A converting the data read from the memory 13 is applied to the CRT 18 as a vertical deflection signal _V (FIG. 4 A and B). Therefore, the first
A Lissage figure C formed by the second input signals a and b is displayed. Note that since the readout clock CLR in the C period has a repetition frequency that is 1/3 of the readout reference clock, the first and second
Compared to the display speed of the input signals a and b, the Lissage figure C is drawn somewhat slowly, and moreover, the Lissage figure C is displayed throughout the C period.

In this way, the first and second input signals a and b and the Lissage figure C are displayed simultaneously on the same screen of the CRT.

Therefore, for example, "10" is set in the brightness modulation setting means 40.
is set, when the content of the display address counter 19 becomes "10", an output is generated from the coincidence circuit 42, and in response to this output, the single-shot circuit 43 generates the output signal E for a certain period of time. This output signal E
In response to this, the brightness signal generation circuit 44 generates the brightness signal F.
Since the input is to CRT18, as shown in Figure 2 B,
On each display waveform representing the first and second input signals a, b and the Lissage figure C
Only the portion corresponding to address 2 and the 10th address of the Y memory 13 will shine brightly. Further, if "23" is set in the brightness modulation setting means 40, only the portion corresponding to the 23rd address of the X memory 12 and Y memory 13 shines brightly on each of the display waveforms a, b, and c.

In this way, the first and second
It becomes possible to indicate a position representing a common time on each display waveform representing the signals a and b and the Lissage figure C.

Also, this high brightness point can be moved over time on each displayed waveform. That is, first,
The brightness modulation setting means 40 is constituted by a counter (hereinafter referred to as a brightness modulation counter), and a brightness modulation clock CLE is input to this counter. Then, the repetition frequency of this luminance modulation clock CLE is made the same as, for example, the refresh rate of display waveforms a, b, and c. In other words, if clock pulse _P1 is 540Hz, the refresh rate of display waveforms a, b, and c is 60Hz, and the clock pulse for brightness modulation is 60Hz.
Set CLE to 60Hz. Then, the contents of the brightness modulation setting counter will increment each time display waveforms a, b, and c are refreshed, so the contents of the brightness modulation setting counter will be "1" at the first refresh, and therefore each On the displayed waveforms a, b, c, the X memory 12 and Y memory 13
The portion corresponding to the first address is displayed as a high brightness point. At the second refresh, the portion corresponding to the second address is displayed as a high-brightness point, and at the third refresh, the portion corresponding to the third address is displayed as a high-brightness point. That is, high brightness points are displayed on each display waveform a, a,
It will move on b and c.

Here, for example, X memory 12 and Y memory 1
3 up to address 1200, it takes about 1200/60, or 20 seconds, for the high brightness point to move through the entire display waveform. Note that by changing the output period of the single-shot circuit 43, the width of the brightly shining portion can be controlled.

Furthermore, according to the embodiment shown in FIG. 5, it is possible to display lines that change over time as shown in FIG. 2C.

In FIG. 5, 45 is a brightness modulation clock.
A brightness modulation counter that inputs CLE, 46 is the content N of the brightness modulation counter 45 and a display counter 19
47 is an AND gate 48, 49;
Consists of an OR gate 50 and an inverter 51,
When the first and second input signals a and b are displayed, the output signal E is input to the luminance signal generation circuit 44 only during the period when the signal T _B is "H", and the Lissage figure C
is displayed, the gate circuit group controls the output signal E to be input to the luminance signal generation circuit 44 during the period when the signal _T3 is "H".

Therefore, if the repetition frequency of the luminance modulation clock CLE is set to 60Hz as described above, the displayed waveform will
At the time of the second refresh, the X memory 12 and Y memory 13
The portion of the display waveform corresponding to the first address shines brightly, but during the second refresh, the portion of the display waveform corresponding to the first and second addresses of both memories 12 and 13 shines brightly. Then, at the third refresh, the first to
When the part corresponding to address 3 is refreshed for the fourth time, the part corresponding to addresses 1 to 4 shines brightly, and as shown by the thick line in Figure 2 C, the brightly shining part, that is, the high brightness area gradually increases. I will do it. Here, since the repetition frequency CLE of the luminance modulation clock is 60Hz, each display waveform a,
It takes about 20 seconds for all of b and c to become high brightness areas.

In this way, the first and second input signals a, b and the Lissage figure C are refreshed at high speed, but since the high brightness point or linear high brightness portion moves slowly on each display waveform, the phenomenon be able to recognize the passage of time.

Note that by changing the repetition frequency of the brightness modulation clock CLE, the moving speed of the high brightness point or linear high brightness portion can be changed. Furthermore, although a counter is used as the brightness modulation setting means 40, the present invention is not limited to this, and various devices such as a memory can be used.

Furthermore, although horizontal and vertical reference position setting circuits 16 _and 17 are provided in the embodiment of FIG. 3, they _are not necessarily necessary, and instead of these circuits, A digital signal may be input to each D/A converter 14, 15 at all times. Furthermore, the reading period from both memories 12 and 13 when displaying the first and second input signals a and b is set to the entire period of the display switching signals T ₁ and T ₂ in the same way as when displaying the Lissage figure C. It is also possible to control the transmission gates 36 and 37 of the gate circuit group 33 not only by the display switching signals T ₁ , T ₂ and T ₃ but also by a signal T _B indicating the read period. However, various changes are possible in the embodiments.

As described above, the Lissage display device according to the present invention displays the raw input signal forming the Lissage figure at the same time as the Lissage figure, and also displays a point representing a common time and a line that changes with time on each display waveform. Since the displayed waveforms are displayed, it is possible to understand not only the temporal changes in each displayed waveform, but also the mutual temporal relationship between the input signal and the Lissage figure. recognition becomes possible.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the outline of the present invention, Figure 2 is a block diagram showing the outline of the present invention.
Figures A to C are waveform diagrams showing display examples in the present invention,
FIG. 3 is a block diagram showing an embodiment of the resurge display device according to the present invention, FIG. 4 is a timing chart showing waveforms of various parts of the embodiment of FIG. 3, and FIG. FIG. 2 is a block diagram showing an example. Explanation of main figure numbers, 1, 11...Measurement and processing unit, 2, 12...X memory, 3, 13...Y memory, 4, 5, 14, 15...D/A converter, 6...
...Selection means, 7, 32...Sweep signal generation circuit,
8,18...CRT, 9,44...Brightness signal generation circuit, 10...Brightness control means, 16,17...Horizontal and vertical reference position setting circuit, 19...Display address counter, 20 ...Reading clock Generation circuit, 29 ...Display switching signal generation circuit, 33 ...
Gate circuit group, 34, 35, 36, 37...transmission gate, 40...luminance modulation setting means, 41 , 46...comparator, 42...matching circuit,
43...Single-shot circuit, 45...Brightness modulation counter.

Claims (1)

[Claims] 1 In a resurge display device that displays a resurge figure on a CRT screen, first and second memories that digitally store first and second input signals forming the resurge figure;
first and second D/A converters for converting data read from the memory into analog signals;
a sweep signal generation circuit that generates a sweep signal for sweeping in the horizontal and vertical directions on a CRT; first, second, and third displays each indicating a period for displaying the first and second input signals and the Lissage figure; A display switching signal generation circuit that generates a switching signal selects the first and second input signals as either horizontal or vertical deflection signals according to the first and second display switching signals, respectively. , and selects the sweep signal as the other deflection signal, and selects the first and second deflection signals according to the third display switching signal.
selecting means for selecting the input signals of as horizontal and vertical deflection signals and outputting them to the CRT;
a brightness signal generation circuit that generates a brightness signal for changing the brightness of a CRT; and brightness control means that controls the brightness signal generation circuit including means for setting the timing at which the brightness should be changed; 1 and 2 input signals to the CRT.
1. A Lissage display device characterized in that a dot representing a common time or a line that changes with time is displayed on each display waveform at the same time on a screen.