JP2554466B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a solid-state imaging device using a MOS static induction transistor (hereinafter abbreviated as SIT) in which imaging times of all pixels are matched.

[Prior art]

Conventionally, in a solid-state imaging device using a MOS type SIT, each pixel signal is usually read by an XY address selection method. FIG. 4 shows a configuration example using such a reading method. This is disclosed in Japanese Patent Application No. 59-59525 filed by the applicant of the present invention, and the waveform of its operating pulse is shown in FIG. In the figure, 21 _-11 , 21
_-12 , ..., 21- _mn are imaging pixels composed of a MOS type SIT which functions as a light receiving element and a switching element, and are arranged in a matrix of m rows and n columns. Row direction of the gate of each pixel column, each vertical selection line 22 _-1, 22 _-2, commonly connected to the ...... 22 _-m, and the source of the pixel columns in the column direction, respectively horizontal selection lines 23 _{- It} is commonly connected to ₁ , 23 _-2 , ...... 23 _-n . Further, the drains of all the pixels are commonly connected by the drain wiring 24, and the drain voltage V _DD is applied.

Each horizontal selection line 23 _-1 , 23 _-2 , ... 23 _-n is respectively a horizontal selection switch 25 _-1 , 25 _-2 ... 25 _-n and a horizontal bias switch 25 _-1 ′, 25 _-2 ′. , ... 25 _-n 'is commonly connected to each source terminal, and each horizontal selection switch 25 _-1 , 25 _-2 , ... 25 _-n drain terminal is connected to the video line 29 and via load resistor 31. Ground, while the horizontal bias switch 25 _-1 ', 2
Bias line 3 is applied to each drain terminal of 5 _-2 ', ... 25 _-n '
Connected to 0 and grounded. Horizontal selection switch 25 _-1 , 2,
The gate terminals of 5 _-2 , ... 25 _-n are sequentially activated by the horizontal scanning circuit 28, and similarly, the horizontal bias switch 2
Each gate terminal of 5 ₋₁ ′, 25 _-2 ′, ... 25 _-n ′ is controlled by the inversion pulse by the inverters 26 _-1 , 26 _-2 , ... 26 _-n of the output of the horizontal scanning circuit 28. Is configured. Reference numeral 27 is a vertical scanning circuit, which outputs vertical selection lines 22 _-1 , 22 according to its output pulse.
_-2 , ... 22- _m are activated sequentially.

In Fig. 5, φ _G1 , φ _G2 , ... are vertical selection lines 22 _-1 , 2
.. are pulses applied to 2 _-2 , ..., and φ _S1 , φ _S2 , ... are pulses applied to the horizontal selection switches 25 _-1 , 25 _-2 ,. V _φG is a read level of the vertical scanning signals φ _G1 , φ _G2 , ... In the horizontal scanning period t _H , and V _φR is a reset level of the horizontal blanking period t _BL .

In the solid-state imaging device configured as described above, when the scanning signal φ _G1 becomes V _φG by the operation of the vertical scanning circuit 27, the pixel column 21 connected to the first vertical selection line 22 _-1.
-11 , 21 _-12 , ... 21 _-1n is selected, and the horizontal selection switches 25 _-1 , 25 _-2 , ... are sequentially set by the signals φ _S1 , φ _S2 , ... output from the horizontal scanning circuit 28. When turned on, pixels 21 _-11 , 21 _-12 ,
...... 21 _-1n optical signals are sequentially output from the video line 29. Subsequently, the pixel rows 21 _-11 , 21 _-12 , ... 21 _-1n are reset when the signal φ _G1 becomes the high level V _φR .

Then, when the signal φ _G2 becomes V _φG , the second vertical selection line
The pixel columns 21 _-21 , 21 _-22 , ... 21 _-2n connected to 22 _-2 are selected, and the optical signal of each pixel is sequentially read by the horizontal scanning signals φ _S1 , φ _S2 , ... , Then reset. In the same manner, the optical signals of all pixels are sequentially read out and the video signal of one field is obtained.

[Problems to be solved by the invention]

In the solid-state imaging device using the conventional MOS type SIT,
When reading a pixel signal by the XY address selection method, there are the following problems.

That is, the first point is a problem related to the XY address selection system, in which the time when the incident image is picked up depending on the pixel position of the screen is one field period (1/60 in the NTSC system).
Therefore, when an object that moves within one field cycle is imaged, image distortion occurs, and the stop motion reproduction (still image) of the video camera recorded image is generated.
It has been a problem when used as an image recognition camera for industrial use.

The second point is a problem related to the pixel reset method of the MOS type SIT solid-state imaging device. That is, in the conventional device, all the pixels connected to each vertical selection line are collectively reset at the same time in the horizontal blanking period t _BL in which one horizontal scanning reading is completed as described above. On the other hand, the pixel readout time is deviated by 1 horizontal scanning period (about 53 μs in the NTSC method) between the first pixel and the last pixel in the horizontal direction. Therefore, 1 horizontal scanning period is added to the pixel imaging time. Only make a time difference. This time difference causes almost no problem with the integration time of 1/30 seconds or 1/60 seconds (in the case of the NTSC method) in the normal interlaced or non-interlaced scanning mode, but by providing a reset vertical scanning circuit, When the image pickup time of the pixel is set to a time shorter than the pixel signal read cycle (usually this time is the image pickup time) and the operation of the variable image pickup time mode (shutter mode) that changes by an integral multiple of the horizontal scanning cycle is performed, Due to this difference in image capturing time, the shortest image capturing time (that is, the maximum shutter speed) is limited.

That is, the allowable limit of the imaging time difference is about 20 to 1 in view of the deterioration of the image quality due to the sensitivity unevenness, so that it is 20 times the horizontal scanning time (53 μs × 20 = 1.06 in the NTSC system).
ms is the shortest imaging time (shutter speed is approximately 1 /
1000 seconds), and high-speed shutter operation beyond that was virtually impossible.

The present invention has been made to solve the above problems,
It is an object of the present invention to provide a solid-state imaging device in which imaging of all pixels is started at the same time and an imaging time difference between pixels does not occur.

[Means and Actions for Solving Problems]

In order to solve the above problems, the invention according to claim 1 includes an imaging pixel array section in which a plurality of imaging pixels composed of MOS static induction transistors are arranged in a matrix, and the interlaced scanning method is used. In the driven solid-state imaging device, all the pixels in the odd-numbered rows or all the pixels in the even-numbered rows are collectively and simultaneously for each field,
A means for resetting immediately after the end of the readout period for each field, and at the start of scanning for starting the readout of the pixels in the row corresponding to the previous field, the reset operation of all the pixels in the row corresponding to the field is terminated and imaging is started. Means, a means for simultaneously and independently and nondestructively reading out the signals of pixels of two consecutive rows of a row corresponding to the field and a row corresponding to the previous field adjacent to the field, and read by the reading means. And a means for deriving a difference signal between the pixel signals of the two consecutive pixels.

Then, by the operations of the resetting means and the image pickup starting means, the image pickup start points of all the pixels in each field are made coincident with each other, the signals of the pixels of two consecutive rows are read by the reading means, and the two consecutive pixels are read by the difference signal deriving means. By deriving the difference signal of the pixel signals of the row and canceling the signal component accumulated in the imaging time after the start of reading the pixels of the row corresponding to the field, the end time of the imaging time is set to the optical signal of the field. It is possible to set the end time of the accumulation period, which makes it possible to effectively match the imaging times of all pixels in each field.

Further, the invention according to claim 2 is provided with an imaging pixel array section in which a plurality of imaging pixels composed of MOS static induction transistors are arranged in a matrix, and either one of an odd row or an even row is provided. In a solid-state imaging device in which a pixel signal is read out every two fields, all pixels of either the odd-numbered row or the even-numbered row are collectively and simultaneously for each field, immediately after the end of the optical signal accumulation period. And a first resetting means for resetting all pixels of one of the odd-numbered row and the even-numbered row at the same time simultaneously in an arbitrary horizontal blanking period every two field periods. Second reset means for resetting immediately after the lapse of two field periods from the horizontal blanking period, and the other of the other in the arbitrary horizontal blanking period for every two field periods. Means for terminating the reset operation of all pixels and starting imaging, means for simultaneously and independently reading out the signals of the pixels of two consecutive rows in the optical signal accumulation period of one row for each two field periods, And a means for deriving a difference signal of pixel signals of pixels in each of two consecutive rows read by the reading means.

Then, by the operations of the second reset means and the imaging start means, the imaging start time points of all the pixels of the other row in each two-field period are made to coincide with each other, and the reading means reads the signals of the pixels of two consecutive rows. The difference signal deriving means derives the difference signal between the pixel signals of each two consecutive rows to cancel the signal component accumulated in the imaging time after the reading of the pixels of the other row every two field periods. By this, the end time of the imaging time of all the pixels of the other row can be set to the start time of the optical signal accumulation period of the pixels of the one row, whereby all the pixels of the other row in every two field period can be set. It is possible to effectively match the imaging times of.

〔Example〕

Examples of the present invention will be described below. The present invention
The present invention can be applied to a solid-state imaging device of an XY address selective reading system having interfering scanning-capable non-destructive imaging pixels.

FIG. 1 is a configuration diagram showing an embodiment of a solid-state imaging device according to the invention described in claim 1, and FIG. 2 is a diagram showing a waveform of an operation pulse thereof.
1 _-11 , 1 _-12 , ... 1 _-1n , 1 _-21 , 1 _-22 , ... 1 _-mn are MOS type _SITs that form each pixel and are arranged in a matrix of m rows and n columns. There is. And a vertical selection line commonly connected to the gate electrodes of the MOS type SITs that constitute each pixel arranged in the horizontal direction.
2 _-1, 2 _-2, and ...... 2 _-m, horizontal selection line 3 connected in common to a source terminal of the SIT constituting a pixel of a pixel and the even rows of the odd rows which are arranged in the vertical direction _-1A, 3 _{-1B , 3 -2A, 3 -2B, ......} 3 -nA, 3 by a selection pulse signal applied to the _-Nb, and to select the pixels to be the intersection. Further, the drain terminals of the MOS type SIT constituting each pixel are commonly connected, and the drain voltage V _DD is applied by the drain wiring 4.

MOS switches _{5 -1A, 5 -2A, 5 -2B} , 5 -3A, ...... 5 -mB performs A, depending on the field of B, and combinations of two rows of vertical selection lines each of which is selected at the same time One end of each of the MOS switches 5 _-1A , 5 _-2A , 5 _-2B , 5 _-3B is commonly connected to the first output line of the vertical scanning circuit 9 so that the output pulse V ₁ is applied. And likewise the MOS switch 5 _-3A ,
One end of 5 _-4A , 5 _-4B , 5 _-5B is commonly connected to the second output line so that the output pulse V ₂ is applied. Similarly, one end of each of the four continuous MOS switches is connected to the vertical scanning circuit 9 in common. On the other hand, MOS
The other end of switch _5-1A is connected to the first vertical select line
The other _ends of the switches 5 _-2A and 5 _-2B are commonly connected to the second vertical selection line. Similarly, the other _ends of the MOS switches 5 _-3A and 5 _-3B are commonly connected to the third vertical selection line, and similarly, the other _ends of two consecutive MOS switches are common to the vertical selection line. It is connected to the. Also, the MOS switch 5 _-1A ,
5 _-2A, the gates of the _...... 5 -mA is adapted to control pulse F _A is connected to a common is applied, likewise MOS switch 5 _-2B, 5 _-3B, each of _...... 5 -mB The gates are commonly connected and the control pulse F _B is applied.

The MOS switches 6 _-1 , 6 _-2 , ... 6 _-m are connected to the vertical selection lines 2 _-1 , 2 _-2 , ... 2 _-m , respectively, and the odd-numbered vertical selection lines or the even-numbered vertical selection lines are connected. It is a changeover switch for sending reset pulse R _R collectively for each vertical selection line, and pulse R _O is applied to each gate of MOS switches 6 _-1 , 6 _-3 , ... 6 _-m-1 A pulse R _E is applied to each gate of the MOS switches 6 _-2 , 6 _-4 , ... 6 _-m to control each MOS switch.

Horizontal selection MOS switch 7 _-11 , 7 _-12 , 7 _-21 , 7 _-22 , ...... 7 _-n1 ,
7 _-n2 are switches 7 _-11 and 7 _-12 , switches 7 _-21 and 7 _-22 , ..., switches _{depending on} the outputs H ₁ , H ₂ , ... H _n of the horizontal scanning circuit 10.
Each of 7- _n1 and 7- _n2 is selected as one set and driven simultaneously. One end of one switch of each set is commonly connected to the first video line 11 and the other end is commonly connected to the pixels of each column of the odd-numbered rows, and one end of the other switch of each set is connected to the second video line 11. The other end is connected to the video line 12 in common to the pixels in each column of even rows. Load resistors 13 and 14 each having one end grounded are connected to the video lines 11 and 12, respectively. Then, the signal current from each selected pixel is under the gate electrode of the MOS type SIT which constitutes each pixel,
A current that depends on the surface potential due to the accumulation of holes generated by light irradiation becomes a current that flows through the load resistors 13 and 14 and is derived as an output voltage.

Horizontal selection switch 7 _-11 ′, 7 _-12 ′, 7 _-21 ′, 7 _-22 ′,…
... 7 _-n1 ', 7 _-n2' is provided in order to ground the horizontal selection line which is not the selected state (or set to a constant voltage), the output H _1, H ₂ of the horizontal scanning circuit 10, ...... the inverter 8
It is designed to be controlled by the pulse inverted by _-1 , 8 _-2 , ... 8 _-n . The reason why the horizontal selection line not in the selected state is grounded is to prevent the horizontal selection line immediately before reading from deviating from the ground potential and appearing as a pseudo signal at the time of signal reading.

Both output voltages derived on the video lines 11 and 12 are input to the differential circuit 15 to output the difference voltage, and then the absolute value circuit 16 makes the signal polarity constant, and the next signal processing circuit 17
Then, the waveform is processed and is sent to the display device 18 and the recording device 19.

Next, referring to the waveform diagram of the operation pulse of FIG.
The operation of the embodiment shown in FIG. 1 will be described in detail.
The embodiment shown in FIG. 1 is a MOS for interlaced scanning.
Is a solid-state imaging device using a type SIT, and pixel information of pixel columns connected to odd-numbered vertical selection lines in the A field, and pixels of pixel columns connected to even-numbered vertical selection lines in the B field. Each is configured to read information. In FIG. 2, G1, G2, G3 and G4 are MOS switches 5 _-1A ; 5 _-2A , 5 _-2B ; 5 _-3B based on the vertical scanning pulse outputs V1 and V2 from the vertical scanning circuit 9. , 5 _-3A ; 5 _-4A , 5
_4B shows pulse signal waveforms applied to each vertical selection line 2 _-1 , 2 _-2 , 2 _-3 , 2 _-4 via _-4B .

Hereinafter, a method of matching the imaging times of the pixels in the pixel columns connected to the odd-numbered vertical selection lines corresponding to the A field will be described. First, all pixels connected to the odd-numbered vertical selection lines are collectively reset in the blanking period immediately after the end of the A field reading period. The integration of the optical signal of the input image starts at the same time when this reset is completed, and B
It continues for the whole period of reading the field. Next, at the same time when the reading of the A field is started, the reading is started from the beginning of each pixel column connected to the odd-numbered vertical selection lines, but the time from the start of the reading of the A field to the reading of the pixels of the vertical selection line is It depends not only on the address of the vertical selection line but also on the address of the horizontal selection line. On the other hand, in the pixels connected to the even-numbered vertical selection lines corresponding to the B field, as in the odd-numbered vertical selection lines, batch reset is performed in the blanking period immediately after the completion of the B field reading, and the A field reading is performed. Imaging is started together with the start.

By the way, the signal component accumulated in the pixel after the start of the A field reading of the vertical selection line pixels of the odd-numbered rows is the signal of the same horizontal address pixel of the vertical selection lines of the even-numbered rows adjacent to the vertical selection lines of the odd-numbered rows. Can be considered equal to the components. Therefore, at the same time as selecting the odd-numbered vertical select lines and the immediately subsequent even-numbered vertical select lines at the same time, the pixel signals of the pixels in the same column direction are independently read at the same timing, and the difference between those output signals is obtained. For example, it is possible to cancel the signal component stored in the imaging time after the start of reading the A field of the vertical selection line pixels in the odd rows.

As a result, the effective image pickup time is only the B field read period regardless of the vertical address and horizontal address of each pixel column connected to the odd-numbered vertical selection lines.
It is possible to match the imaging times of all the pixels in the field. The operation relating to the odd-numbered vertical selection lines in the A field described above is exactly the same as the operation relating to the even-numbered vertical selection lines in the B field.

The above is the basic operation. Next, the operation of the present embodiment will be described in more detail. First, in the A field, the reset pulse R _R is applied to the vertical selection lines 2 _-2 , 2 _-4, ... By the control pulse R _E during the blanking time to collectively reset the pixel columns of even rows. After reset, the even-numbered pixel columns subsequently enter the optical information storage state. On the other hand, the odd-numbered pixel columns in which the optical information is being stored are in the read state. Here, the control pulse F _A becomes the selection level, and the vertical scanning pulse output V1 from the vertical scanning circuit 9 passes through the MOS switches 5 _-1A and 5 _-2A as shown by G1 and G2 in FIG. Select lines 2 _-1 and 2
_Is applied to _−2, and the pixel rows 1 _-11 , 1 _-12, ... Of the first row and the pixel rows 1 _-21 , _1-22, ... Of the second row are in the selected state. Then, by the output (H1, H2 ...) Of the horizontal scanning circuit 10, the MOS
Switch 7 _-11 7 _-12, 7 _-21 7 _-22 ... are sequentially turned on, the pixel column 1 _-11 of the first row, 1 _-12 ... and the pixel columns of the second row 1 _- The signals ₂₁ , ₂₁ , ₂₂ ... _Are read out independently to the video lines 11 and 12 at the same time.

Next, the vertical scanning pulse output V2 from the vertical scanning circuit 9
But through the MOS switches 5 _-3A and 5 _-4A, as indicated by a G3, G4 2, is applied to the vertical selection line 2 _-3 and 2 _-4, the third row of pixel columns 1 _{-31, 1-32} ... and the pixel row of the fourth row _1-41 , _1-42
... is selected. Then, by the outputs (H1, H2 ...) Of the horizontal scanning circuit 10, MOS switches _7-11 and _7-12 , 7
_-21 and 7 _-22 ... sequentially turn on, and the third row of pixel columns 1 _-31 ,
The signals of _1-32 ... And the pixel rows _1-41 , _1-42 ... of the fourth row are simultaneously read out independently to the video lines 11 and 12, respectively. In the same manner, the simultaneous reading of the pixel columns of the even rows in the optical information storage state after the reset adjacent to the odd rows is continued, and the reading of the A field is completed. here,
The pixel signals read out independently on the two video lines 11 and 12 are input to the differential circuit 15 and the difference signal between them is output.

Next, in the B field, blanking time control reset pulse R _R pulse R _O by a vertical selection line 2 _-1, 2 _-3 ...
・ Reset the pixel columns of odd rows all at once by applying to
Start the accumulation of optical information. On the other hand, the even-numbered pixel columns during the accumulation of optical information are in the read state. Where the control pulse
F _B becomes the selection level, and the vertical scanning pulse output V1 from the vertical scanning circuit 9 passes through the MOS switches 5 _-2B and 5 _-3B ,
It is applied to the vertical selection line 2 _-2 and _2-3, the pixel row of the second row
1 _-21 , 1 _-22 ... And the pixel columns 1 _{-31 1,1 -32} ... Of the third row are in the selected state. Then, the output of the horizontal scanning circuit 10 (H1, H
2 ...), the MOS switches 7 _-11 and 7 _-12 , 7 _-21 and 7 _-22
... are sequentially turned on, and the second row of pixel columns _1-21 , _1-22 ...
.. and the signals of the pixel columns 1 _-31 , 1 _-32, ... Of the third row are simultaneously and independently read to the video lines 11 and 12, respectively.
Similarly, the pixel signals read out on the two video lines 11 and 12 are input to the differential circuit 15 and the difference signal is output. It

Pixels are reset all together during the blanking period between each field. At this reset, the control pulse R _O or R _E
At the same time, the reset pulse R _{R is set} to the selection level, then the reset pulse R _R is first returned to the non-selection level, and then the control pulse R _O or R _E is returned to the non-selection level with a slight delay.

Due to the reset operation characteristics of the MOS type SIT, the selection level of the reset pulse is the vertical scanning circuit output for reading V ₁ , V ₂ , ...
It is necessary to set a certain level higher than the selection level of.

As described above, in each field of A and B, at the same time as selecting the odd-numbered or even-numbered vertical selection lines, the adjacent even-numbered or odd-numbered vertical selection lines in the immediately succeeding stage are selected, and pixels in the same column direction are selected. Pixel signals are read out independently at the same timing and sent to the two video lines 11 and 12. Then, the output signals sent out on the video lines 11 and 12 are input to the differential circuit 15, and the difference signal between them is output. This difference signal is obtained by canceling the signal component accumulated in the image pickup time after the start of field reading, and therefore the effective image pickup time of each field is only the read period of the other field, and the image pickup of all pixels of each field is performed. The time will be the same.

As described above, in a non-destructive readable MOS type SIT is used as a pixel and an interlaced scanning method is applied, an operation of collectively resetting all the pixels in each field and two consecutive vertical selection lines Are simultaneously read out, and by using a new pixel driving means that combines operations for deriving a difference signal between these two output signals, the imaging times of all the pixels in the field can be effectively matched.

Next, an embodiment of the invention described in claim 2 will be described with reference to a time chart of operation waveforms shown in FIG. Structure of this embodiment, in an embodiment of the invention described in paragraph 1 claims shown in FIG. 1, MOS switch 5 _-2B, 5 _-3B, and _...... 5 -nB, these switches The driving control pulse F _B is omitted, and the illustration is omitted.

In FIG. 3, the scanning period 2 is used only as the input image integration period in the pixels connected to the odd-numbered vertical selection lines, and in this period, as in the first embodiment, the even-numbered vertical selection is performed. The pixels connected to the line are not read out. In the scanning period 1, while the vertical selection line pixels in the odd-numbered rows continue to be integrated, the reading is performed at the same time as the vertical selection line pixels in the even-numbered rows that have started the integration from the beginning of the scanning period, and the difference between the read signals is derived. Output.

That is, first, in the scanning period 2, the reset pulse R _R is applied to the vertical selection lines 2 _-2 , 2 _-4, ... by the control pulse R _E during the blanking time to collectively reset the pixel columns in even rows. . On the other hand, the pixel columns of odd rows are integrated. In the middle of the scanning period 2, a reset pulse R _R is applied to the vertical selection lines 2 _-1 , 2 _-3, ... With the control pulse R _O to collectively reset the pixel columns in the odd rows and A new integration of pixel columns is started. Then in scan period 1,
During the blanking time, a reset pulse R _R is applied to the vertical selection lines 2 _-2 , 2 _-4, ... With a control pulse R _E to collectively reset the pixel columns in even rows. After that, the vertical scanning circuit 9
The vertical scanning pulse output V1 from the MOS switch 5 _-1A and 5
_-2A through the vertical selection line 2 as shown by G1 and G2 in FIG.
_-1 and 2 _-2 , the first row of pixel columns 1 _-11 , 1 _-12 ...
And the pixel columns _1-21 , _1-22, ... Of the second row are in the selected state. Next, the MOS switches 7 _-11 and 7 _-12 , 7 _-21 and 7 _-22 ... are sequentially turned on by the outputs (H1, H2 ...) Of the horizontal scanning circuit 10, and the first row of pixel columns The signals of 1 _-11 , 1 _-12 ... And the pixel columns 1 _-21 , 1 _{-22 of} the second row are read out to the video lines 11 and 12 simultaneously and independently. The integration time of the pixel columns in the odd rows here is the time from resetting the odd rows in the scanning period 2 to reading in the scanning period 1, that is, T _S.

Then, the vertical scanning pulse output V2 from the vertical scanning circuit 9
However, through the MOS switches 5 _-3A and 5 _-4A , the vertical selection line 2 _-3
, And 2 _-4 , and the pixel rows 1 _-31 , 1 _-32, ... of the third row and the pixel rows 1 _-41 , 1 _-42 , ... of the fourth row are selected.
Next, the MOS switches _7-11 and _7-12 , _7-21 and _7-22 ... are sequentially turned on by the outputs (H1, H2 ...) Of the horizontal scanning circuit 10, and the third row of pixel columns _1-31 , 1 _-32 ... And the signal of pixel row 1 _-41 , 1 _-42 ...
2 are read independently at the same time. In the same manner, the reading of the odd-numbered pixel columns accompanied with the simultaneous read-out of the adjacent even-numbered pixel columns after the reset is completed. Here, the pixel signals read on the two video lines 11 and 12 are input to the differential circuit 15, and the difference signal between them is output.

Also in this embodiment, the integrated signal component of each pixel from the time of entering the signal readout period of the odd-numbered row of the scanning period 1 to the time when the signal of each pixel of the odd-numbered row is actually read out (see FIG. 3). , The odd / even row pixel output waveform hatched portion from the time of batch resetting of the even rows to the time t ₃ when the signals of the pixels of the odd rows are read is the difference signal of the read signals to the video lines 11 and 12. Canceled by taking. Therefore, the signal component that appears in the output of the differential circuit is only the signal component in the integration period T _S in the scanning period 2 regardless of the address of the read pixel, and for all pixels connected to the vertical selection lines in odd rows, The integration time is the same.

Then, the integration start time t ₁ of the input light information of each odd-numbered pixel column in the scanning period 2 is the horizontal blanking period t _HB
And the integration period T _S until the time t ₂ of the vertical blanking period after the end of the scanning period 2 is set to a desired time under the constraint of T _S = (horizontal scanning period × integer). It is decided by doing.

In the second embodiment, the reading of only the odd-numbered pixel columns has been described. However, the even-numbered pixel columns can be read by changing the configuration of the device and the pulse timing.

As described above, in this embodiment, since the integration time of the odd-numbered rows is canceled by the integration time of the even-numbered rows, the image pickup signal cannot be obtained in the scanning period 2, but the input image integration of all pixels in the odd-numbered rows is performed. The time can be matched and the integration time can be arbitrarily changed by an integral multiple of the horizontal scanning period.
It can have a 1/700 high-speed shutter function. Therefore, various applications are possible such as capturing the state of coordinate movement of an object moving at high speed on a TV moving image and obtaining the moving speed in image processing.

〔The invention's effect〕

As described above based on the embodiment, according to the invention described in the first aspect of the invention, it is possible to match the shooting times of all the pixels in each field, and the shooting target of the imaging target during the imaging period can be matched. It is possible to eliminate the distortion of the reproduced image due to the movement. Further, according to the invention as set forth in claim 2, since it is possible to make the imaging time of all pixels of either the odd-numbered row or the even-numbered row for every two field periods the same, By setting the imaging time to an integral multiple of the horizontal scanning period of one field period or less, it is possible to provide a high-speed shutter function with almost no additional circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the invention described in claim 1, FIG. 2 is a diagram showing an operation signal waveform thereof, and FIG. 3 is in claim 2 FIG. 4 is a diagram showing an operation signal waveform used in the embodiment of the described invention, FIG. 4 is a diagram showing a configuration example of a conventional solid-state imaging device, and FIG. 5 is a diagram showing the operation signal waveform. In the figure, 1 _-11 , 1 _-12 , ... 1 _-mn is a pixel, 2 _-1 , 2, _-2 , ...
2 _-m vertical selection _{line, 3 -1A, 3 -1B, 3} -2A, 3 -2B, ...... horizontal selection _{lines, 5 -1A, 5 -2A, 5} -2B, ...... 5 -mB vertical Select switch, 6
_-1 , 6, _-2 , ... 6 _-m is reset switch, 7 _-11 , 7
_-12 , 7 _-21 , 7 _-22 , ... is a horizontal selection switch, 9 is a vertical scanning circuit, 10 is a horizontal scanning circuit, 11 and 12 are video lines, 15 is a differential circuit, 16 is an absolute value circuit, 17 Indicates a signal processing circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masaharu Imai 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Masatoshi Ida 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Inventor Chihiro Nakagawa 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Inventor Kazuya Matsumoto 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Inventor Junichi Nakamura 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd.

Claims (2)

(57) [Claims] 1. A solid-state imaging device driven by an interlaced scanning method, comprising an imaging pixel array section in which a plurality of imaging pixels composed of MOS static induction transistors are arranged in a matrix, and an odd-numbered row for each field. All pixels or all pixels in an even-numbered row are reset at the same time immediately after the end of the reading period for each field, and at the start of scanning to start reading the pixels in the row corresponding to the previous field, Means for terminating the reset operation of all the pixels in the row corresponding to, and starting the image pickup, and the signals of pixels in two consecutive rows in the row corresponding to the field and the row corresponding to the previous field adjacent to the field at the same time. Means for independently nondestructively reading out and a difference signal between the pixel signals of the pixels of two consecutive rows read out by the reading means are derived. Means for adjusting the image pickup start time points of all the pixels in each field by the operations of the resetting means and the image pickup starting means, the reading means reads out the signals of the pixels of two consecutive rows, and the difference signal deriving means makes them continuous. By deriving the difference signal of the pixel signals of each two rows and canceling the signal component accumulated in the imaging time after the start of reading the pixels of the row corresponding to the field, the end time of the imaging time is set to the field. The solid-state imaging device is configured such that the imaging times of all pixels in each field are made to coincide with each other by setting the end time of the optical signal accumulation period. 2. An image pickup pixel array section in which a plurality of image pickup pixels each composed of a MOS electrostatic induction transistor are arranged in a matrix, and a pixel signal of either an odd row or an even row is read every two fields. In the solid-state imaging device described above, a first reset unit that resets all pixels of either the odd-numbered row or the even-numbered row for each field at the same time, immediately after the end of the optical signal accumulation period, Immediately after the lapse of two field periods from the arbitrary horizontal blanking period, all pixels of either the odd-numbered row or the even-numbered row are simultaneously batched in an arbitrary horizontal blanking period every two field periods. Second resetting means for resetting to all the pixels and resetting operation of all the pixels in the other row in the arbitrary horizontal blanking period every two field periods. And means for starting imaging by, the optical signal accumulation period of one line for each of the 2 field period,
A means for simultaneously and independently reading the signals of the pixels of two consecutive rows, and a means for deriving a difference signal between the pixel signals of the pixels of each two consecutive rows read by the reading means,
By the operations of the second reset means and the imaging start means, the imaging start time points of all the pixels in the other row in each two-field period are made to coincide with each other, and the reading means makes consecutive 2
The signal of the pixel in the row is read out, and the difference signal between the pixel signals in two consecutive rows is derived by the difference signal deriving means, and the difference signal is accumulated in the imaging time after the readout of the pixel in the other row is started every two field periods. By canceling the signal component
By setting the end time of the image pickup time of all the pixels of the other row as the start time of the optical signal accumulation period of the pixels of the one row, the image pickup times of all the pixels of the other row are matched every two field periods. A solid-state imaging device having the above-mentioned configuration.