JP2551473B2 - Semiconductor memory device having error detection / correction function - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to an error detection / correction circuit and an error detection / correction circuit included in a large capacity semiconductor memory device having an error detection / correction function. A possible improvement of the codeword generation circuit.

[Prior Art] EEPROM (electrically writable and erasable non-volatile semiconductor memory device), DRAM (dynamic random access memory)
As the capacity of semiconductor memory devices such as memory) and SRAM (static random access memory) increases, the number of defective memory cells increases accordingly, and the conventional redundant memory cell method may not be able to cope with it. Conceivable. Further, during operation of the semiconductor memory device, erroneous writing and reading of data may occur due to the occurrence of latent defective cells that have not been detected at the time of product shipment, noise, and the like. Therefore, data error detection and correction functions have been added to large-capacity semiconductor memory devices. First, an error detection and correction method of information will be described by taking a Hamming code, which is one of the commonly used linear codes, as an example.

First, consider a binary block code of length n. The following linear simultaneous equations, A code in which all the sequences w = (x1, x2, ..., _Xn ) that satisfy the above are code words is called a linear code. Where m <n, x _i ∈ {0,
1}, i = 1, ..., N, a _ij (i = 1, ..., N; j = 1, ..., N) are constants having 0 or 1, and the operation follows Boolean algebra.

The above simultaneous equations are called parity check equations, and the coefficient matrix of this parity check equation, Is called a parity check matrix.

In the parity check equation, variables that can be selected independently are called information bits, and variables that are dependent on them are called check bits.

If the code is w, the parity check equation can be expressed as Hw ^T = 0 (mod.2). w is the above code word, and T is a symbol indicating transposition.

Depending on the parity check matrix as described above, one having the following form is called a canonical parity check matrix.

However, I _m is an m × m identity matrix.

At this time, the check bits are the first m bits (x1, x2, ..., x
_m ). The relation between the information bit and the check bit is given by the following equation in the case of the canonical parity check matrix (x ₁ … x _m ) ＝ (m _{m + 1} , ・ ・ ・, x _n ) P ^T (mod.2) Therefore, when the information bit (m _{m + 1} , ..., X _n ) is arbitrarily selected, the check bit corresponding thereto is uniquely determined.

For the above canonical parity check matrix, Is called the generator matrix.

In the linear code, the code word w is generated from the content of the information bit w ₁ using the generator matrix G as follows.

w = w ₁ G (mod.2) In the above parity check matrix H, when each column is non-zero and there is no column equal to each other, the code generated by the generator matrix G corresponding to the matrix H is Hamming-coded. It is called a code or a Hamming single error correction code.

For the code word w, s = Hw ^T (mod.2) is called the syndrome s of w. Since the syndrome s is 0 for the error-free codeword w, the fact that the syndrome s of the given codeword is not 0 means that the codeword contains an error. The given codeword is a single error pattern, , The syndrome s is s = H (w + e _i ) ^T = He _i ^T. That is, the syndrome s is equal to the i-th column of the parity check matrix H.

If the given codeword is a Hamming code, the check matrix H
Information having a single error pattern has different syndromes s, since each column of is non-zero and there is no column that is equal to each other. Therefore, error detection and correction can be performed by obtaining the syndrome of given data and adding the corresponding single error pattern to the given information.

Accurate data writing / reading in a semiconductor memory device is performed using the above-described error-correctable / detectable codeword. That is, at the time of data writing, a check bit is generated corresponding to externally given data, and the check bit generated corresponding to the given write data is linked to the write data and stored. At the time of reading, the information of the accessed memory cell and the check bit linked to it are read to form a code word, and the presence or absence of an error is detected and corrected from the code word, so that accurate data is read. It is a thing. The configuration and operation of the semiconductor memory device having the error detection and correction function according to the above theory will be described below.

FIG. 7 is a diagram showing an overall schematic configuration of a conventional semiconductor memory device having an error correction function. Referring to FIG. 7, a conventional semiconductor memory device corresponds to an memory cell array 1 for storing memory information (hereinafter referred to as information bit) given from the outside and an information bit of the memory cell array 1.
An inspection memory cell array 2 including a plurality of memory cells for storing generated inspection information (hereinafter referred to as an inspection bit) is included. The memory cell array 1 has memory cells arranged in a plurality of rows and columns. The inspection memory cell array 2 also has a plurality of memory cells.

In order to select a memory cell of the memory cell array 1,
An X decoder 3 which decodes an X address given through the X address input terminals 21a to 21m and generates a row selection signal.
And Y given through the Y address input terminals 22a to 22n.
A Y decoder 4 for decoding an address and generating a column selection signal is provided. Row and column selection signals from the X decoder 3 and Y decoder 4 are also applied to the inspection memory cell array 2.

Data terminals 23a-23i for data input / output
A data input / output circuit 6 for exchanging data with an external device via the input / output circuit, and an information bit given via the data input / output circuit 6 to generate a check bit in accordance with a predetermined generator matrix. An error correction coding circuit 7 for adding the checked bits to a given information bit and passing it.
And write to the selected memory cell in the information bit memory cell array 1 from the error correction coding circuit 7,
A write / read circuit 5 for writing a check bit to a selected memory cell of the test memory cell array 2 and reading an information bit and a check bit from the selected memory cell at the time of data reading, and a write / read circuit 5. Receiving the given information bits and check bits from, the error detection and correction of the read data (information bits and check bits) is performed according to a predetermined check matrix, and thereafter,
An error decoding circuit 8 for providing information bits (this is a corrected information bit) to the data terminals 23a-23i via the data input / output circuit 6 is provided. This semiconductor memory device is integrated on a semiconductor chip 100.

Next, the semiconductor memory device has a x2 configuration, that is, 2 data
The operation in the case of input or output in bit units will be described as an example. Further, as the generator matrix G used in the error correction coding circuit 7, As the check matrix H used in the error decoding circuit 8, think of. In the above configuration, assuming that the information bits given from the outside are D0 and D1 and the check bits generated corresponding to these information bits are P1, P2 and P3, the error detection correctable code word w is Given in.

The operation performed by the error decoding circuit 8 is performed by the above-mentioned check matrix H.
Based on, the symmetry s is generated from the read codeword (a set of information bits and check bits) based on the following equation.

When this syndrome s is not 0, it becomes the same as any column vector of the check matrix H. Therefore, an error is corrected by detecting whether the syndrome is equal to the column vector of the check matrix H and inverting the bit value of the column corresponding to the column vector.

A list of the input and output relationships of the above-mentioned encoding and decoding is shown in FIG. Data writing and reading operations of the conventional semiconductor memory device will be described below with reference to FIGS. 7 and 8.

Consider a case where 2-bit data (0, 1) is externally supplied via the data terminals 23a to 23i. This external data (code word) is waveform-shaped by the input / output circuit 6,
It is given to the error correction coding circuit 7. The error correction coding circuit 7 generates check bits (1,1,0) from the given information bits (0,1) based on the above-mentioned generator matrix G, and is given the generated check bits. It is added to the information bit and given to the writing / reading circuit 5. On the other hand, X address input terminals 21a to 21m and Y address input terminals 22a to 22n
The X address and the Y address are given to the X decoder 3 and the Y decoder 4, respectively, via. X decoder 3
The Y decoder 4 decodes the applied address and selects the corresponding row and column from the memory cell array 1 and the test memory cell array 2. Writing / reading circuit 5
The information bits from 1 to 3 are written to the selected memory cells of the memory cell array 1, and the check bits are written to the selected memory cells of the test memory cell array 2. As a result, the information bit and the inspection bit are stored in the memory cell array 1 and the inspection memory cell array 2 in a linked form.

Next, the read operation will be described. Address input terminal 21
The X address and the Y address are given to the X decoder 3 and the Y decoder 4 via a to 21m and 22a to 22n. The X decoder 3 and the Y decoder 4 decode the given address, and select the corresponding memory cells of the memory cell array 1 and the test memory cell array 2. As a result,
The information bit is read from the selected memory cell of the memory cell array 1, and the check bit is read from the test memory cell array 2. The read information bit and check bit are applied to write / read circuit 5 and then to error decoding circuit 8. The error decoding circuit 8 detects and corrects the error of the information bit and the check bit from the applied information bit and the check bit according to the list shown in FIG. Now consider the case where the information bit read is (0,1) and the check bit is (1,1,0). In this case, since there is no error in the read code word (information bit and check bit), the error decoding circuit 8 outputs the information bit (0, 1), and the data input / output circuit 6 and the data It is transmitted to the outside of the device through the terminals 23a to 23i.

Due to some cause of memory cell defect, noise, etc., (0,1) and the information bit to be read are (0.0) and 1
Consider a bit wrong. In this case, since the check bit stored in association with this information bit and read is (1,1,0), the error correction decoding circuit 8 reads the read data (0 , 0) is corrected to (0, 1) and then applied to the data input / output circuit 6. Similarly, even when a 1-bit error occurs only in the check bit from the check memory cell array 2, as shown in FIG. 8, there is an error in the information bit (0, 1). Therefore, the read information bit (0, 1) is applied to the data input / output circuit 6 via the error decoding circuit 8.

As described above, it becomes possible to read data accurately, and when data different from the originally written data is read due to some cause (memory cell defect, noise, etc.). It is possible to read data accurately.

[Problems to be Solved by the Invention] As described above, in a conventional semiconductor memory device having an error correction function, generation of check bits and addition to information bits based on a predetermined generator matrix and check matrix, And the detection and correction of errors in the read codewords (information bits and check bits). Therefore, if the information bit given from the outside is determined, the check bit added corresponding to the information bit is also uniquely determined, and also the read code word is uniquely output from the error decoding circuit 8. The data to be done is determined according to the check matrix. Therefore, in the conventional semiconductor memory device, the error correction coding circuit 7 and the error decoding circuit 8 are configured by hardware using logic gates. Specific configurations of the error correction coding circuit and the error decoding circuit will be described below.

FIG. 9 is a diagram showing, at a logical level, a specific configuration of the error correction coding circuit and the error decoding circuit in the case where the semiconductor memory device is configured to input / output data in units of 2 bits. Referring to FIG. 9, error correction coding circuit 7 has XOR gate X1 which receives information bits D0 and D1 given from the outside.
And a signal line S1 for passing the information bit D0 given from the outside and a signal line S2 for passing the information bit D1 from the outside. The output of the XOR gate X1 gives the check bit P1, the signal line S1 gives the check bit P2 and the signal line S2 gives the check bit P3.

The error decoding circuit 8 includes five XOR gates X2 to X6 and 2
Inverters I1 and I2 and two AND gates A1 and A2 are provided. The XOR gate X2 receives the information bits D0 and D1 from the memory cell array 1 and the inspection bit P1 from the inspection memory cell array 2. The XOR gate X3 receives the information bit D1 and the check bit P2. The XOR gate X4 receives the information bit D1 and the check bit P3. Inverter 11 receives the XOR gate X3 output. Inverter I2 receives the XOR gate X4 output. A
The ND gate A1 receives the XOR gate X2 output, the XOR gate X3 output, and the inverter I2 output. AND gate A2 is XOR gate X2
It receives the output, the inverter I1 output and the XOR gate X4 output. XOR gate X5 receives information bit D0 and AND gate A1 output. XOR gate X6 receives information bit D1 and AND gate A2 output. Information bits D0, D1 after correction, that is, to be applied to the data input / output circuit 6, are output from the XOR gates X5, X6. By configuring the error correction coding circuit and the error decoding circuit by hardware as described above, it is possible to detect and correct errors at a higher speed than the operation of detecting and correcting errors by software. Has become.

However, when the circuit configuration for error detection / correction code is configured as a hardware configuration as described above, it includes many logic gates. Therefore, when the operating power supply potential fluctuates, the potential level of each logic gate output is changed. Also fluctuates, which causes a problem that the logical operation speed of data is reduced and an erroneous logical operation is performed. This problem will be described in more detail with reference to FIG.

Referring to FIG. 10, XO included in the error correction coding circuit
The R gate X1 is a p-channel MOS transistor T1 and an n-channel MOS transistor T2 CMOS inverter stage,
A CMOS inverter stage including a channel MOS transistor T3 and an n-channel MOS transistor T4. The inverter stage consisting of the transistors T1, T2 receives the information bit D0. The inverter stage consisting of the transistors T3, T4 receives the information bit D1. Furthermore, the XOR gate X1 is a transistor T
In response to the output of the inverter stage consisting of T3 and T4, the transistor is turned on and passes through the output of the inverter stage consisting of transistors T1 and T2.
A pass transistor T6 that is turned on in response to the output of the inverter stage consisting of 4 and passes the information bit D0,
In response to information bit D1, it turns on and the transistor
A pass transistor T7 that passes the output of the inverter stage consisting of T1 and T2, and a pass transistor T8 that turns on in response to the output of the information bit D1 and passes the information bit D0.
And an inverter I3 that inverts and outputs the output of the pass transistor T8.

Similarly, the error decoding circuit 8 includes a logic gate formed of MOS transistors. The XOR gate X2 includes a CMOS inverter stage including transistors T10 and T11, a CMOS inverter stage including transistors T12 and T13, a CMOS inverter stage including transistors T14 and T15, and pass transistors T16 to T23. The inverter stage consisting of the transistors T10, T11 receives the check bit P1. Transistor
The inverter stage consisting of T12 and T13 receives the information bit D0. The inverter stage consisting of the transistors T14, T15 receives the information bit D1. The pass transistors T16 and T17 are turned on in response to the output of the inverter stage composed of the transistors T12 and T13. The pass transistors T18 and T19 are turned on in response to the information bit D0. Pass transistor T20,
T21 is turned on in response to the output of the inverter stage composed of the transistors T14 and T15. The pass transistors T22 and T23 are turned on in response to the information bit D1. XOR gate X2
Is output via the inverter 14.

The XOR gate X4 is a pass transistor T4 which is turned on in response to a CMOS inverter stage composed of transistors T40 and T41 and an inverter stage output composed of transistors T14 and T15.
2, T43, pass transistors T44 and T45 which are turned on in response to the information bit D1, and an inverter I6 provided in the output section.

The inverter I1 is composed of a CMOS inverter including transistors T50 and T51.

The inverter I2 is composed of a CMOS inverter including transistors T52 and T53.

AND gate A1 is connected to input transistors T60, T61 and T62.
And load transistors T63, T64 and T64, and a CMOS inverter stage composed of MOS transistors T66 and T67 provided in the output section.

AND gate A2 is connected to input transistors T71, T72 and T73.
And load transistors T74, T75, T76, and an inverter stage composed of transistors T77, T78 in the output section.

XOR gate X5 is a CMOS inverter stage composed of transistors T80 and 81, and an inverter I7 that receives the output of AND gate A1.
And the pass transistors T82 and T83 that are turned on in response to the output of the inverter I7, the pass transistors T84 and T85 that are turned on in response to the output of the AND gate A1, and the inverter I8 provided in the output stage. To be done. The corrected information bit D0 is output from the inverter I8.

XOR gate X6 is a CMOS inverter stage consisting of transistors T90 and T91, and an inverter stage I9 that receives the output of AND gate A2.
And the pass transistors T92 and T93 that are turned on in response to the output of the inverter I9, the pass transistors T94 and T95 that are turned on in response to the output of the AND gate A2, and the inverter I10 provided in the output stage. To be done. Inverter I10
Outputs the corrected information bit D1.

A sense amplifier 9 for detecting and amplifying the read information is provided between the error bit encoding circuit and the information bit memory cell array 1 and check bit memory cell array 2.

Usually, the operating margin on the high potential side of the semiconductor memory device is specified to be 4 to 6V, for example. Memory cell array 1,
The operating margin on the high potential side of 2 is set to 3 to 7 V, which is wider than the operating margin of this semiconductor memory device. However, since the operation margin on the high potential side of the error correction coding circuit or the error decoding circuit is as narrow as 4 to 6 V, the operation margin on the high potential side of the semiconductor memory device as a whole is high in the circuit configuration for error correction. It is determined by the potential side operation margin.

Consider, for example, a case where the operating power supply potential Vcc drops from 5V to 4V for some reason. In this case, each XOR
The gate includes an inverter stage and a pass transistor whose operation is controlled in response to the output of the inverter stage. Therefore, when the operating power supply voltage Vcc drops to, for example, 4V, the "H" level of the inverter stage output also drops, and the inverter stage output level applied to the gate of each pass transistor also drops. The pass transistor can carry a voltage equal to the difference between the voltage applied to the gate and each unique threshold voltage. Therefore, the signal voltage transmitted from the pass transistor becomes lower than 4V by the threshold voltage of this transistor. Therefore, a plurality of such pass transistors are provided, and the output of the pass transistor on the output side of each XOR gate is further reduced. Since the lowered potential level of the output signal is further transmitted through the decoding circuit through the inverter stage and the pass transistor, it is considered that the signal potential level is further lowered.
This lowering of the signal potential level lowers the operating speed in each logic gate. (For example, in the case of an inverter stage, the operating speed becomes faster because the higher the power supply potential is, the faster the charging operation of the output level becomes. , In the opposite case, the speed of asses slows down). Further, when the input potential level applied to each logic gate becomes close to the input logic threshold value, each logic gate cannot perform an accurate logic operation, and an incorrect signal level is transmitted as an output signal. Can be considered.

Therefore, although the circuit configuration for correcting the data error in the memory device is provided as described above, the operation margin on the high potential side of the circuit configuration for error detection / correction is narrow, This makes it impossible to perform accurate judgment and correction, and causes a drawback that the judgment operation becomes slow.

That is, when a circuit configuration for detecting and correcting an error in information is provided by a conventional hardware configuration using a logic gate, the operation margin on the high potential side in the semiconductor memory device becomes narrow and an accurate information error occurs. This makes it impossible to perform detection / correction, and in addition, the determination operation becomes slower, resulting in a delay in the access time of the semiconductor memory device.

Japanese Patent Laid-Open No. 61-101857 discloses a computer system in which an error detection / correction circuit provided outside the main memory is implemented as a ROM. This prior art aims to eliminate an increase in the amount of hardware that occurs when an error detection / correction circuit, that is, a check bit generation circuit and an error detection / correction circuit is configured by logic gates such as an XOR gate and an AND gate. For this purpose, for this purpose, "a widely used and inexpensively available" R
The OM is used to construct the check bit generation circuit and the error detection / correction circuit. Therefore, this prior art is intended only to improve the error detection / correction circuit provided outside the memory device, and any consideration should be given to the error detection / correction circuit built in the semiconductor memory device. In addition, it does not recognize any problem peculiar to the semiconductor memory device having the error detection / correction function as described above.

An object of the present invention is to expand an operating power supply voltage margin of a semiconductor memory device having an error detecting / correcting function, thereby accurately and rapidly performing error detection / correction of information even if the operating power supply voltage fluctuates. It is to provide a semiconductor memory device capable of performing the same.

Another object of the present invention is to provide a semiconductor memory device having a function capable of performing error detection / correction accurately and at high speed even when a high-potential power supply voltage is reduced.

Still another object of the present invention is to widen the operating power supply voltage margin of the error detection / correction circuit built in the semiconductor memory device to the same extent as the operating power supply voltage margin of the memory cell portion included in the semiconductor memory device. That is, the operating power supply voltage margin of the entire semiconductor memory device is expanded.

[Means for Solving the Problem] A semiconductor memory device having an error detection / correction function according to the present invention is provided with at least one of an error correction coding circuit and an error correction decoding circuit built in the semiconductor memory device as a ROM.
It consists of. That is, the semiconductor memory device capable of error detection / correction according to the present invention receives storage information (information bit) given from the outside to generate a corresponding check bit, and the given information bit and the check bit generated. The information bit and the check bit linked to this information bit are read from the memory cell selected in response to the error correction coding circuit and the external address which are linked and output, and the error detection and correction of the read bit data are performed. At least one of the error correction decoding circuits that outputs the information bit after performing the operation stores the data to be output corresponding to each address with the given data as an address input.
It is characterized by being composed of ROM.

[Operation] The ROM-composed error correction coding circuit or error correction decoding circuit portion of the present invention has the same circuit configuration as the memory cell array portion and the peripheral circuit portion (including the inspection memory cell array) of this semiconductor memory device. You can
It is not necessary to provide multiple stages of logic gates (especially XOR gates), and even if the operating power supply potential fluctuates, the output potential level fluctuation amount can be set to the same level as that of the memory cell array section and its peripheral circuit section. By this, the power supply voltage margin of the correction encoding circuit portion or the error correction decoding circuit portion can be made approximately the same as that of the memory cell array portion,
A wide operating power supply voltage margin can be realized as the entire semiconductor memory device.

[Embodiment of the Invention] FIG. 1 is a block diagram schematically showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor memory device according to an embodiment of the present invention is integrated and formed on a semiconductor chip 100. X address input terminals 21a to 21m, Y address input terminals 22a to 22n, data input / output terminals 23a to 23i and control signal input terminals 25 to 27 are provided on the semiconductor chip 100 for inputting and outputting signals. There is.

The control signals ▲ ▼ (write enable signal), ▲ ▼ (output enable signal) and ▲ ▼ (chip enable signal) given to the control signal input terminals 25 to 27 are given to the control signal generating circuit 30. The control signal generation circuit 30 includes a signal ▲ ▼ for designating a write / read operation mode of the semiconductor memory device, an output enable signal ▲ ▼ for giving a data write / read operation timing,
And a signal indicating selection / non-selection of the semiconductor memory device ▲
In response to ▼, various control signals for controlling the operation of the semiconductor memory device are generated. The various control signals generated by the control signal generation circuit 30 differ depending on whether the semiconductor memory device is an EEPROM, a DRAM, an SRAM, or the like.

The X address given through the X address input terminals 21a to 21m is given to the X decoder 3. The X decoder 3 selects the corresponding row of the information bit memory cell array 1 and the test memory cell array 2 in response to the given X address. The Y address given to the Y address input terminals 22a to 22n is given to the Y decoder 4. Y decoder 4
Selects a corresponding column from the information bit memory cell array 1 and the inspection memory cell array 2 in response to the applied Y address.

The data input / output terminals 23a-23i are coupled to the data input / output circuit 6. The data input / output circuit 6 waveform-shapes the applied data, applies information bits from the outside to the error correction coding mask ROM 10 at the time of writing the data, and shapes the data from the error decoding mask ROM 11 at the time of reading the data. To the data input / output terminals 23a-23i.

The error correction coding mask ROM 10 includes a data input / output circuit 6
The memory information (information bit) given from the address is used as an address input, and the check bit (see FIG. 8) corresponding to the given information bit is stored in advance. The given information bit and this mask ROM are formed. The check bit is linked to the write / read circuit 5.

The writing / reading circuit 5 writes the information bit and the check bit supplied from the error correction coding mask ROM 10 to the selected memory cell of the information bit memory cell array 1 and the check memory cell array 2, respectively.

The error decoding mask ROM 11 receives the information bit and the check bit from the memory cell selected at the time of data reading via the write / read circuit 5. Error decoding mask
The ROM 11 receives the given information bits and check bits as its address inputs, and stores the corresponding information bits and check bits of each address in a mask ROM.

In writing / reading data in / from a semiconductor memory device, when input data is applied, generated check bits or information bits are uniquely determined according to a check matrix or a generation matrix. Therefore, if each error correction coding circuit and error decoding circuit is formed into a mask ROM and the input data is used as the address signal of each mask ROM, desired check bits and / or information bits can be easily generated.

FIG. 2 is a diagram showing an example of a specific configuration of the error correction coding mask ROM 10 which is an embodiment of the present invention. Referring to FIG. 2, the mask error correction coding mask ROM 10 includes a decoder unit for decoding the given information bits D0 and D1.
And a ROM memory unit that stores in advance check bits corresponding to input information. In the configuration of FIG. 2, the configuration in which the number of information bits is 2 and the number of check bits is 3 is shown, and the generator matrix used for generating the check bits is in accordance with the table shown in FIG. The case where the same one is used is shown as an example. The decoder unit includes an inverter I21 receiving the information bit D0, an inverter I22 receiving the information bit D1, and four NOR gates N1 to N1.
With N4. NOR gate N1 receives information bit D0 and information bit D1. NOR gate N2 receives inverter I21 output and information bit D1. NOR gate N3 receives information bit D0 and the output of inverter I22. NOR gate N4 receives an inverter I21 output and an inverter I22 output. NOR
The outputs of the gates N1 to N4 are connected to the word lines WL1 to WL4 of the ROM memory section, respectively.

In the ROM memory section, the memory transistors M1 to M6 are arranged so as to give the same "1" and "0" patterns as the partial matrix corresponding to the matrix for generating check bits of the generator matrix G.
Here, in the ROM memory section, the memory transistors are provided so as to be respectively arranged at the intersections of the word lines and the bit lines. Depending on the film thickness of the gate oxide film of each memory transistor, “0”, “1” Is configured to be stored. However, in the configuration of FIG. 2, only the memory transistors M1 to M6 which store the information "0" with the thinned gate oxide film are shown. Specifically, in the ROM memory section, the word line WL1 and the bit line WL1
Memory transistors M1, M2 and M3 are located at each intersection of BL1 to BL3.
Is provided. A memory transistor M4 is provided at the intersection of the word line WL2 and the bit line BL3. A memory transistor M5 is provided at the intersection of the word line WL3 and the bit line BL2.
A memory transistor M6 is provided at the intersection of the word line WL4 and the bit line BL1. Bit lines BL1 to BL3 are sense amplifiers 9
Connected to. The sense amplifier 9 detects and amplifies the potential on the outputs of the bit lines BL1 to BL3, and then outputs it as the check bits P1 to P3. That is, the signal level on the bit line BL1 gives the check bit P1, the signal level on the bit line BL2 gives the check bit P2, and the signal level on the bit line BL3 gives the check bit P3.

FIG. 3 is a diagram showing an example of a specific configuration of the error decoding mask ROM of the semiconductor memory device according to the embodiment of the present invention. Even in the configuration shown in FIG. 3, the case where the decoding is the same as the table shown in FIG. 8 is shown as an example. Referring to FIG. 3, the error decoding mask ROM 11 is
It has a decoder part and a memory part. Decoder part is 5
Inverters I41 to I46 and 32 NOR gates N10 to N12 are provided. However, this has 2 information bits,
This is the case where the check bits are 3 bits. This decoder section
NOR type decoder configuration, input information D0, D1 and P1 to P3
Complementary information data from ▲ ▼, ▲ ▼ and ▲
▼ to ▲ are generated, decoded by each NOR gate N10 to N12, and the corresponding word line is selected from the ROM memory section. For example, NOR gate N10 receives information bits D0, D1, check bits P1, P2 and P3. NOR gate N11 receives information bit D0, information bit D1, check bits P1, P2 and inverted bit ▲ ▼. NOR gate N12 is each inverter
Output of I41 to I42, that is, inverted information bit ▲
▼, ▲ ▼ and inverted check bit ▲ ▼-▲
Receive ▼.

In the ROM memory section, read information bits corresponding to the input information D0, D1 to P1 to P3 are stored in ROM. That is, this ROM memory portion has a configuration in which 32 word lines and 2 bit lines are provided for each NOR gate N10 to N12.
A memory transistor in which the film thickness of the gate oxide film is set according to the stored information is provided at the intersection of each word line and bit line. The bit line output is applied to the sense amplifier 9, amplified there and then output as read information D0, D1. Next, the operation will be briefly described.

Now, consider a case where the storage information (information bit) externally given via the data input / output terminals 23a to 23i is (1,0). In this case, in the error correction coding ROM 10, only the output of the NOR gate N3 becomes "H" in response to the given information bit (1,0), and the remaining NOR gates N1, N2 and N4 outputs are "L". It becomes a level. As a result, the potential of the word line WL3 rises and the memory transistor M5 is turned on.
As a result, the potential on the bit line BL2 is discharged to the "L" level, and the outputs of the remaining bit lines BL1 and BL3 are set to the "H" level which is the precharged level. This bit line BL
After the potentials (H, L, H) appearing on 1, BL2 and BL3, that is, (1,0,1), are detected and amplified by the sense amplifier 9,
The check bits P1 to P3 are output. In the above description, the precharge path of each bit line BL1 to BL3 is the same as that provided in a normal ROM circuit,
It is omitted to avoid complication of the drawing. (1,0,1) check bit P generated via this sense amplifier 9
1, P2 and P3 are linked to information bits D0 and D1 for writing and
It is applied to read circuit 5. The write / read circuit 5 has already
The information bit and the inspection bit are written into the memory cells in the information bit memory cell array 1 and the inspection memory cell array 2 selected through the decoder 3 and the Y decoder 4, respectively. This completes the write operation.

In the configuration of FIG. 2, the configuration for outputting the information bits D0 and D1 during the above-described data writing operation is not shown, but this configuration may be a configuration in which the information bits D0 and D1 are allowed to pass through. The ROM memory unit may store the information bit corresponding to this information bit.

In this data write path, the decoder section has a NOR type decoder configuration, which is similar to the configurations of the X decoder 3 and the Y decoder 4 provided in the memory cell array section. The voltage margin can be approximately the same as the margin provided for the memory array section. That is, even if the operating power supply voltage decreases, this operating power supply potential decrease appears in the NOR gate output, but since this output is transmitted to the word line, it is similar to the word line selecting operation in the normal memory cell array section. The operating margin can be set to the same level as that of the memory cell array portion, and thus the operating margin with respect to the power supply voltage can be greatly improved as compared with the circuit configuration using the conventional logic gate.

Although the memory cell selecting operation in the memory cell array 1 and the inspection memory cell array 2 has not been described in the above description, this is because the X address and the Y address are the X decoder 3 in response to the control signal ▲ ▼ given from the outside. And Y decoder 4 respectively, and in response to a control signal from control signal generating circuit 30, a selecting operation for the memory cell array is performed. A data write command is issued in response to control signals ▲ ▼ and ▲ ▼. That is, when the write enable signal ▲ ▼ is active "L" and the output enable signal ▲ ▼ is inactive "H" during data writing, the data is taken into the data input / output circuit 6 and the error correction coding mask. It is given to ROM10. Next, the data read operation will be described.

Further, in response to the external control signal (), the X address and the Y address are assigned to the X decoder 3 and the Y decoder 4, respectively.
To the memory cell array 1 and the inspection memory cell array 2 and the corresponding memory cell is selected, and the information bit and the inspection bit in each are read. The read information bits and check bits are applied to error decoding mask ROM 11 via write / read circuit 5. The error decoding mask ROM 11 has given information bits D0, D1 and check bits P1 to P3 as its address inputs, and is stored fixedly in correspondence, that is,
Read the information in ROM. That is, for example, if the information bit is (1,0) and the check bit is (1,0,1),
Mask ROM is (1,0) corresponding to address (1,0,1,0,1)
The word line corresponding to this address is selected and stored, and its content is given to the data input / output circuit 6 as the read information D0, D1 via the sense amplifier 9.
The data input / output circuit 6 outputs the data given in response to the control signals ▲ ▼ and ▲ ▼ as read data.

If, for some reason, a 1-bit error occurs, that is, if the read bits from the memory cell array 1 and the test memory cell array 2 are (1,1,1,0,1) (the information bit D0 is incorrect). Case), (0,0,1,0,1) (information bit D1 is error), (1,0,0,0,1) (check bit P1 is error), ( (1,0,1,1,1) (that is, when the check bit P2 is erroneous), (1,0,1,
0,0) (that is, the check bit P3 is incorrect),
Write information (1,0) is masked R at any time
Since it is OM, the error decoding circuit 11 can read the data accurately. That is, the information reading is performed by correcting the error of the information.

Even when reading this data, the decryption mask RO
Since the decoder section of M11 has the same NOR type configuration as the decoder section provided corresponding to the memory cell array section, this power supply voltage operation margin can be the same as that for the memory cell array section. As a whole, the operating power supply voltage margin of the semiconductor memory device can be improved.

For other combinations of the information bit and the check bit, the corresponding information in the mask ROM is read out by the decoder section, and the data input / output circuit is provided after the error detection and correction of the information. It is read via 6.

An example of the structure of the mask ROM is shown in FIGS. 4A to 4C. FIG. 4A shows an example of the circuit configuration of the mask ROM, and FIG.
Its plan layout is shown in FIG. 4, and its partial sectional structure is shown in FIG. 4C. In FIG. 4A, the mask ROM includes a memory transistor M10, M13 that has a thin gate oxide film and stores information “0”, and a memory transistor M11, M13, which has a thick gate oxide film and stores information “1”. M12 is provided. Memory transistors M10, M11 by word line WL10
Is selected, and the information of each memory transistor M10, M11 is transmitted onto the bit lines BL20, BL21. The memory transistors M12 and M13 are selected by the word line WL11, and the information of the memory transistors M12 and M13 is transmitted onto the bit lines BL20 and BL21.

Referring to FIG. 4B, memory transistors M10 and M13
The respective gate oxide films are thin, and the memory transistors M11 and M12 are thick. The thinner the gate oxide film, the lower the threshold voltage,
On the other hand, the thicker the gate oxide film, the higher the threshold voltage of the memory transistor. Therefore, even if the same voltage is applied to the gate of the memory transistor via the word line, the memory transistor having the thinner gate oxide film is conductive, while the memory transistor having the thicker gate oxide film is non-conductive. It remains conductive. As a result, information "0" and "1" are stored.

FIG. 4C is a drawing showing a cross-sectional structure along the line XX ′ shown in FIG. 4B. The memory transistor M12 that stores information "1" is composed of a source diffusion layer 201a and a drain diffusion layer 201b on the semiconductor substrate 200, and a thick gate oxide film B and a gate electrode 203 thereon. Information “0”
The memory transistor M13 for storing the data is composed of the source diffusion layer 201c connected to the bit line, the drain diffusion layer 201b connected to the ground potential, the thin gate oxide film A on the drain diffusion layer 201b, and the gate electrode 203 serving as the word line. Composed. As described above, information can be easily stored simply by changing the thickness of the gate oxide film.

In addition to this structure, the film pressure of the word line and the gate electrode is kept constant without changing the film thickness of the gate oxide film, and information is stored depending on the presence / absence of contact between each gate electrode and the word line. There is also.

FIG. 5 is a diagram showing a FAMOS cell structure used as a memory cell in a normal memory cell section. Referring to FIG. 5, a FAMOS cell (EPROM cell) is an impurity region serving as a source and drain diffusion layer formed on a semiconductor substrate 300.
301a, 301b, a floating gate 302 formed on the semiconductor substrate 300 via an interlayer insulating film 304 and storing information depending on whether charge is accumulated therein, and an interlayer insulating film 305 on the floating gate 302. The control gate 303 is formed.

Therefore, when the memory cell structure of the memory cell array is the FAMOS cell structure as shown in FIG. 5, the ROM for error detection and correction is formed in the same manufacturing process as the memory cell transistor in the memory cell array. Therefore, the process can be significantly simplified as compared with the case where the conventional logic gate is used. That is,
In the thin gate oxide film, the gate electrode is formed in the same manufacturing process as the floating gate 302, and the gate electrode in the thick gate oxide film is formed in the same manufacturing process as the control gate 303. By doing so, the mask ROM can be easily formed in the same manufacturing process. In this case, when the information is stored in the mask ROM not by the thickness of the gate oxide film but by the presence / absence of contact between the gate electrode and the word line, the control gate 303 in the configuration shown in FIG.
Alternatively, the mask ROM can be formed by the same manufacturing process as that of any of the floating gates 302.

Even if the memory cell structure included in the storage memory cell arrays 1 and 2 is not a FAMOS cell structure but a normal DRAM cell (see FIG. 6), the size of the gate oxide film thickness of the memory transistor of the ROM or the gate Even when information is stored depending on the presence or absence of the electrode and the contact electrode, the memory transistor of the ROM can be formed in the same manufacturing process as the transistor of the memory cell array portion. That is, referring to FIG. 6, the gate electrode of the ROM memory transistor can be formed in the same manufacturing process as either the gate electrode 400 of the DRAM cell or the cell plate 401 which is one electrode of the information storage capacitor.
It is possible to easily form an error detection / correction ROM that is a mask ROM without complicating the manufacturing process. Referring to FIG. 6, the DRAM cell comprises a semiconductor substrate 405, an impurity diffusion region 406a serving as a source, an impurity diffusion region 406b serving as a drain, and a gate insulating film 407.

Here, FIG. 5 (b) and FIG. 6 (b) show the equivalent circuits of the FAMOS cell and the DRAM cell, respectively.

[Effects of the Invention] As described above, according to the present invention, at least one of the error correction code circuit portion and the error decoding circuit portion in the semiconductor memory device having the error detection / correction function is ROM.
Since the error correction encoding / decoding circuit portion is configured in the same manner as the memory cell array portion and the peripheral circuit portion related to the semiconductor memory device other than the above, it is possible to perform the error correction. The operating power supply voltage margins of the encoding circuit portion and the decoding circuit portion can be expanded to the same extent as the operating power supply voltage margins of the information bit and check bit storage portion and its associated peripheral circuit portion. A wide operating power supply voltage margin can be given to the entire device,
It is possible to obtain a semiconductor memory device capable of accurately reading data at high speed even when the power supply voltage fluctuates.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing an overall configuration of a semiconductor memory device which is an embodiment of the present invention. FIG. 2 is a diagram showing an example of a specific configuration of the error correction coding mask ROM in the semiconductor memory device according to the embodiment of the present invention.
FIG. 3 is a diagram specifically showing an example of the configuration of the error decoding mask ROM of the semiconductor memory device according to the embodiment of the present invention. 4A to 4C are diagrams showing an example of a specific configuration of the mask ROM, FIG. 4A shows an example of an equivalent circuit of the mask ROM, and FIG. 4B is a plane of the mask ROM shown in FIG. 4A. The layout is shown in FIG. 4C, which is line XX ′ in FIG. 4B.
It is a figure which shows the cross-section. FIG. 5 is a diagram schematically showing a sectional structure and an equivalent circuit when a FAMOS cell is used as a memory cell of a memory cell array. FIG. 6 is a diagram showing a sectional structure of a DRAM cell and its equivalent circuit when the DRAM cell is used as the memory cell structure of the memory cell array. FIG. 7 is a diagram schematically showing an overall structure of a conventional semiconductor memory device. FIG. 8 is a view showing a list of input / output correspondences at the time of encoding and decoding for error detection and correction in the semiconductor memory device. FIG. 9 is a diagram showing an example of the configuration of the error correction coding circuit and the error decoding circuit in the conventional semiconductor memory device at the logical level, and the configuration according to FIG. 8 is shown. FIG. 10 is a circuit diagram showing a more specific circuit configuration of the error correction coding circuit and the error decoding circuit shown in FIG. In the figure, 1 is a memory cell array for storing information bits, 2 is a test memory cell array for storing check bits, 3 is an X decoder, 4 is a Y decoder, 5 is a write / read circuit, and 6 is data. An input / output circuit, 10 is an error correction coding mask ROM, 11 is an error decoding mask ROM, and 100 is a semiconductor chip. In the drawings, the same reference numerals indicate the same or corresponding parts.

Front page continued (72) Inventor Kenji Noguchi 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation Kita Itami Works (56) References JP 61-261896 (JP, A) JP 56- 107396 (JP, A)

Claims (1)

(57) [Claims] 1. In a data writing operation, a plurality of storage elements are provided, and inspection information is generated corresponding to storage information given from the outside, and the generated inspection information is added to the storage information. Means for writing the code word to the storage element selected by the external address after forming a code word of at least 1-bit error detection and correction by means of the memory, and the storage activated by the data read and selected by the external address. A semiconductor memory device, comprising means for reading a stored codeword from an element and outputting storage information that has been subjected to error detection and correction processing based on the read codeword as read information. At least one of the error detection / correction means uses the given information as an address input and stores the output information corresponding to the given information for each address. A semiconductor memory device having an error detection / correction function, which is configured by using an output-only memory element and wherein the read-only memory element is formed on the same semiconductor chip as the plurality of memory elements.