JPH02126500A - Semiconductor memory device equipped with error detecting and correcting function - Google Patents

Abstract

PURPOSE:To expand an operation power-supply voltage margin and to accurately detect and correct an error in information at high speed by composing at least one of an error correcting and encoding circuit and an error correcting and decoding circuit of a mask ROM. CONSTITUTION:An input/output circuit 6 waveform-shapes data from terminals 23a-23i, sends an information bit to an error correcting and encoding mask ROM 10 in writing, and waveform-shapes data from an error decoding mask ROM 11 and sends the data to the terminals 23a-23i in reading out. The ROM 10 previously stores a parity bit corresponding to the given information bit and sends the input information bit and the parity bit to a writing and reading circuit 5. The circuit 5 writes the respective bits to a memory 1 for information and a memory 2 for inspection. Further, when input data are given, the parity/ information bit to be generated is uniquely determined according to an inspection matrix/generator matrix.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to semiconductor memory devices, particularly error detection and correction J [1 This invention relates to improvements in circuits and error detection/5f correct code word generation circuits.

[Prior art] Semiconductor memories such as EEFROM (non-volatile semiconductor memory device that can be electrically written and erased), DRAM (dynamic random access memory), and SRAM (static random access memory) As devices become larger in capacity, the number of defective memory cells will increase accordingly, and it is conceivable that the conventional redundant memory cell system will no longer be able to cope with this. Furthermore, during the operation of a semiconductor memory device, erroneous data writing and reading may occur due to the emergence of latent defective cells that were not detected at the time of product shipment, noise, and the like. For this reason, data error detection and =1 correct functions have been added to large-capacity conductor storage devices. First, an information error detection and correction IE method will be described using Hamming 71, which is one of the commonly used linear square codes, as an example.

First, consider a binary block code of length n. The following linear system of equations, I! l plus series W= (xL X2+ ...+
xn) are all codewords? 1 is called a linear code. However, here man, Xi e (0, 1).

i-1,..., n, a,, (i-1,...
.

The above simultaneous equations are called a parity check equation, and the coefficient matrix of this parity check equation is called a parity check matrix.

In the parity check equation, the variables that can be selected independently are the information bits, and the variables that are dependent on them are the check bits!・I call it.

Letting the sign be W, the parity check equation is HwT-0
It can be expressed as (mod, 2). W is the code word mentioned above, and T is a symbol indicating transposition.

Depending on the above-mentioned parity check matrix, one having the following form is called a canonical parity check matrix.

n k However, 1.7 is an mxm unit matrix.

At this time, the check bit is the first In bit (Xl.

x2. ..., xllll). The relationship between the information bit and the inspection bit is correct! In the case of '1I11 type parity check matrix, (X+ ...Xtn) - (mm++ * ...
*xn) PT (mod, 2) Therefore, information pi-(m□7....+xl
l), the corresponding check bit is uniquely determined.

For the above noon parity check matrix, It G-k t [P” 1m] is called a generator matrix.

In Linear No. 71? No. 1 9W is '6 of the information bit Wl
is generated using the generation matrix G as follows.

wmw G (mod, 2) In the above parity check matrix H, if each column is non-zero and there are no mutually equal columns, then No. 71 generated by the generator matrix G corresponding to matrix H is Hamming No. 71. Or Hamming's single error correction? Call it No. 1.

For a codeword W, s −Hw"' (mod, 2) is called the syndrome S of W. For a codeword W without an error, the syndrome S is [), so the given code If the syndrome S of a word is not 0, it means that the codeword contains an error.If a given codeword has a single error pattern, e, Liao(0,..., 0 .1. (1,...,0)
, the syndrome S becomes s-H(w+eI)''-He, T. That is, the syndrome S is equal to the first column of the parity check matrix H.

When the code word is Hamming 71, each column of the parity check matrix H is non-zero and there are no mutually equal columns, so the information that makes a single error pattern (i) is Therefore, error detection and correction can be performed by determining the syndrome of the data obtained from I'J and adding the corresponding I1l error pattern to the given information.

IF-accurate data writing/reading in a semiconductor memory device is performed using error-correctable/detectable code words as described above. That is, when writing data, check bits are generated in response to externally applied data, and the check bits generated in response to the given write data are linked to the write data to write the data. Then, when reading data, the information of the accessed memory cell and the check bits linked thereto are read out as word 71, and the ? ] By detecting the presence or absence of errors from the code word and correcting them, accurate data can be read. The structure and operation of a semiconductor memory device that performs an error detection and correction function according to the above theory will be described below.

FIG. 7 is a diagram showing the overall general structure of a conventional semiconductor memory device having an error correction function. Referring to FIG. 7, the conventional semiconductor memory device stores storage information (
The memory cell array 1 stores the information bits (hereinafter referred to as information bits), and the memory cell array F (number The test memory cell array 2 includes a test memory cell array 2 consisting of memory cells.The memory cell array 1 has memory cells arranged in a plurality of rows and columns.The test memory cell array 2 similarly has a plurality of memory cells.

In order to select a memory cell in memory cell array 1,
An X decoder 3 decodes the X address received through the address input terminals 21a to 21m and generates a row selection signal, and a column selection is performed by decoding the Y address given through the Y address input terminals 22a to 22n. A Y decoder 4 for generating a signal is provided. Row and column selection numbers 1; from the X decoder 3 and Y decoder 4 are also applied to the test memory cell array 2.

In order to perform human output of data, data terminals 233-2
A data input/output circuit 6 exchanges data with an external device via the 3i, and a data input/output circuit 6 which receives information bits given through the data input/output circuit 6 and generates check bits according to a predetermined generation matrix. Error correction that adds the generated check bit to the given information bit and passes it? ] Writing the information bits from the encoder circuit and the error correction 71 encoding circuit 7 into the selected memory cells in the memory cell array 1, and writing the test bits into the selected memory cells in the test memory cell array 2. , and a write/read circuit 5 that reads information bits and check bits from the selected memory cell during data reading, and a write/read circuit 5 that reads information bits and check bits from the write/read circuit 5;・According to the predetermined parity check matrix, errors in the read data (information bits and checks in 11.) are detected and corrected. ) through the data input/output circuit 6 to the data terminal 23
An error decoding circuit 8 for providing data to a to 23i is provided.

This semiconductor memory device is integrated on a semiconductor chip 100.

Next, the semiconductor memory device has a x2 configuration, that is, the data is
The operation in the case of a configuration in which input or output is performed in bit units will be explained as an example. Also, consider that the following is used as the generation matrix G used in the error correction encoding circuit 7, and the following is used as the check matrix H used in the error decoding circuit 8. In the above configuration, information given from the outside!・ are DO, DI, and the check bits generated corresponding to this information bit are PI, P2 . P3, the code word W that allows error detection and correction is given by the following formula (%) - (Do, DI)G.

The operation performed by the error decoding circuit 8 is to generate a syndrome S from the read code word (a set of information bits and check bits) based on the above-mentioned check matrix H based on the following equation.

8 "" (SO, S!, S2) -HwT If this syndrome S is not O, it will be the same as any column vector of the parity check matrix 11. Therefore, by detecting which column 1:1 of this syndrome is equal to the column vector of the parity check matrix H and inverting the bit value of the column corresponding to this column vector, error correction iF is performed jj.

A list of the human output relationships for encoding and decoding described above is shown in FIG. Data write and read operations of a conventional semiconductor memory device will be described below with reference to FIGS. 7 and 8.

Consider a case where 2-bit data (0, 1) is applied from the outside via the data terminals 23a to 23i. This external data (code word) is waveform-shaped by the input/output circuit 6 and then applied to the error correction encoding circuit 7. The error correction encoding circuit 7 converts the given information bits (0, 1>,
Check bits (1, 1, 0) based on the above generation matrix G
The generated check bit is added to the applied information bit and applied to the write/read circuit 5. On the other hand, an X address and a Y address are provided to an X decoder 3 and a Y decoder 4 via X address input terminals 21a to 21m and Y address input terminals 22a to 22n, respectively. The X decoder 3 and the Y decoder 4 decode the applied address and select the corresponding row and column from the memory cell array 1 and the test memory cell array 2. Information bits from write/read circuit 5 are written into selected memory cells of memory cell array 1, and test bits are written into selected memory cells of test memory cell array 2. As a result, in the memory cell array 1 and the test memory cell array 2, the information bits and the test bits are linked and stored in a t-shaped manner.

Next, the read operation will be explained. Address input terminal 21
An X address and a Y address are given to an X decoder 3 and a Y decoder 4 via a to 21 m and 22a to 22n. X decoder 3 and Y decoder 4 decode the received address and select corresponding memory cells in memory cell array 1 and test memory cell array 2. As a result, information bits are read from the selected memory cells of memory cell array 1, and test bits are read from test memory cell array 2. The read information bits and check bits are applied to the write/read circuit 5 and then to the error decoding circuit 8. The error decoding circuit 8 detects and corrects errors in the information bits and check bits according to the list shown in FIG. 8 from the supplied information bits and check bits. Now, consider the case where the read information bits are (0, 1) and the check bits are (1, 1°0). In this case, the read codeword (information bits and check bits) has an error (l
1. Because it does not exist. :? Information bits (0, 1) are outputted from the Mori decoding circuit 8 and transmitted to the outside of the device via the data output circuit 6 and data terminals 2.3a to 23i.

Due to defects in memory cells, noise, etc., the information bits that should be read as (0, 1) are now (0, O).
If one bit is wrong, it will be explained.

In this case, since the check bits that are stored and read out are (1, 1, 0) linked to this information bit, the error correction decoding circuit 8 uses the read data (0) as shown in FIG. , O) are corrected as (0, 1) and then provided to the data input/output circuit 6. Similarly, the test memory cell array 2
Even if a 1-bit error occurs only in the check bit from The read information bits (0, 1) are applied to the data output circuit 6 via the circuit 8.

As described above, it becomes possible to read data accurately, and data different from the originally written data due to causes such as tll (defects in memory cells, noise, etc.) Even when the data is read, it is possible to read the data accurately.

[Problems to be Solved by the Invention] As described above, in a semiconductor memory device equipped with a conventional error correction 1F function, check bits are generated based on a predetermined generation matrix and check matrix and added to information bits. , as well as read? ] Error detection and :1 correction in the code word (information bits and check bits) are performed. Therefore, once the information bits that can be retrieved from the outside are determined, the corresponding check bits are also uniquely determined, and also the check bits that are read out are uniquely determined to be 2 (by the decoding circuit). The data to be output from the error correction encoding circuit 7 is determined according to the parity check matrix.
The error decoding circuit 8 has been implemented as hardware 11-S using logic gates. The specific configurations of this error correction encoding circuit and error decoding circuit will be explained next.

FIG. 9 is a diagram showing, at a logical level, a specific configuration of an error+iT jF encoding circuit and an error decoding circuit in the case where the semiconductor memory device is configured to output data at 2 bits+11th place. Referring to FIG. 9, error correction encoding circuit 7
consists of an XOR gate X1 that receives information bits Do and DI given from the outside, a signal line S1 that passes the information bit DO that is given from the outside, and a signal line S2 that passes the information bit D1 that comes from the outside. be done. XOR
Gate X1 output provides test bit P1, signal line S1 provides test bit P2, and signal line S2 provides test bit P3.

,! The Mori decoding circuit 8 includes five XOR gates X2~
X6, two inverters 11.12, and two AND
Gate A1. Equipped with A2. XOR gate X2 receives information bit DO1D1 from memory cell array 2 and test bit pt from test memory cell array 2. XO
R gate X3 receives information bit D1 and check bit P2. XOR gate X4 receives information bit D1 and check bit P3. Inverter! 1 receives the output of XOR gate X3. Inverter I2 receives the output of XOR gate X4. AND game) At receives the output of XOR gate X2, the output of XOR gate X3, and the output of inverter I2. AND gate A2 receives the output of XOR gate X2, the output of inverter 11, and the output of XOR gate X4. XO
R gate X5 receives information bit DO and AND gate A1 output.

XOR gate X6 connects information bit D1 and AND gate A2
Receive output. XOR game) I5. Information bits Do and DI after correction, that is, to be given to the data output circuit 6, are output from I6.

As mentioned above, the error correction encoding circuit and the error decoding circuit are configured in hardware (1-1), which enables faster error detection and iT It is now possible to hold a market.

However, as mentioned above, when the error detection/correction code circuit configuration is configured as a hardware configuration, it includes a large number of logic gates, so when the operating power supply potential fluctuates, each logic gate output The potential level of also changes,
This causes problems such as a reduction in the speed of data logic operations and erroneous logic operations. This problem will be explained in more detail with reference to FIG.

Referring to Figure 10,! tsu,iljIg? The OR gate X1, which includes the No. 1 conversion circuit, is a p-channel MO3l.
Transistor T1 and n-channel MO3I - transistor T2
and a CMOS inverter stage consisting of a p-channel MOS transistor T'3 and a +1 channel MO3l-transistor T4. A C inverter stage consisting of transistors TI, T2 receives the information bit DO. Transistor T3. Consisting of T4
The inverter stage receives the information bit D1. Further, the XOR gate 1-X1 is connected to the transistor T3. In response to the output of the inverter stage consisting of T4, the transistor TI is turned on.

A pass transistor T5 passes the output of the inverter stage consisting of T2, and a pass transistor T3. A pass transistor T6 turns on in response to the output of the inverter stage consisting of T4 and passes the information bit DO, and a pass transistor T6 turns on in response to the information bit D1 and passes the information bit DO.
, a pass transistor T7 that passes the inverter stage output consisting of I'2, a pass transistor T8 that turns on in response to the output of the information bit D1 and avoids passing the information bit D1, and inverts the output of the pass transistor T8. and an inverter 13 for outputting.

Similarly, the error decoding circuit 8 includes logic gates made up of MOS I-transistors. XOR gate
2 is a CMOS inverter stage consisting of transistors TIO and Tll, and a CMOS inverter stage consisting of transistors T12 and T13.
MOS inverter stage and transistor T14. T1
A CMOS inverter stage consisting of 1.5 and pass transistors T16 to T23 is used. Transistor TIO, Tl
An inverter stage consisting of I receives check bit P1. Transistor 'r12. An inverter stage consisting of T13 receives the information bit DO. Transistor T14. An inverter stage consisting of T15 receives the information bit D1. Pass transistor T16. T17 is a transistor T12. T
It is turned on in response to the output of the inverter stage consisting of 13. Pass transistors T18 and T19 are information bits Do.
It turns on in response to. Pass transistor T20.
T21 is a transistor T14. It turns on in response to the output of the inverter stage consisting of T15. Pass transistor T22. T23 turns on in response to information bit D1. The output of XOR gate X2 is output via inverter I4.

XOR gate X4 is connected to transistor T40. A CMOS inverter stage consisting of T41 and transistors T14. T
The pass transistors T42 and T43 turn on in response to the output of the inverter stage consisting of 15 and the information bit D1.
Pass transistor T44. turns on in response to T44. ”
! '45, and an inverter 6 provided at the output section.

Inverter ■1 is a transistor〕'50. It is composed of a CMOS inverter consisting of T51.

-f inverter I2 is turned off at tMI by a CMOS inverter consisting of transistors T52 and T53.

AND gate A1 has input transistor T60°T61
and T62, load transistors T63, T64 and T65, and a CMOS inverter stage consisting of MOS l-transistors T66 and T67 provided at the output section.

AND gate A2 has input I transistor T71°T7
2 and T73, and load transistors T74°T75.
T76 and an inverter stage consisting of output transistors T77 and T778.

XOR gate X5 is connected to transistor T80. A CMOS inverter stage consisting of T81, an inverter I7 that receives the output of AND gate A1, and a pass transistor T82.783 that turns on in response to the output of inverter I.
It is composed of a pass transistor T84, "I" 85, which turns on in response to the output of the AND gate A1, and an inverter I8 provided at the output stage. The inverter 18 outputs the information bit DO after the correction IE.

XOR gate X6 is connected to transistor T90. A CMOS inverter stage consisting of a CMOS inverter stage T01, an inverter stage I9 receiving the AND gate IA2 output, and a pass transistor T92. T9
3 and a pass transistor T94.3, which is turned on in response to the AND gate) A2 output. T95 and an inverter 110 provided at the output stage. Inverter 11
0 to jJ correct/post-correct information bit D1 is output.

Is there an error in memory cell array 1 for information bits and test memory cell array 2 for test bits? ] A sense amplifier 9 for detecting and amplifying read information is provided between the encoder and the encoding circuit.

Normal゛! The operating margin on the high potential side of a conductive memory device is defined as, for example, 4 to 6V. The operating margin of the memory cell arrays 1 and 2 on the high potential side is set to 3 to 7 V, which is wider than the operating margin of this semiconductor memory device.

However, since the error correction encoding circuit and error decoding circuit have a narrow operating margin of 4 to 6 V on the high potential side,
The operating margin on the high potential side of the semiconductor memory device as a whole is determined by the operating margin on the high potential side of the circuit configuration for error correction.

Now, for example, a case can be made in which the operating power supply potential Vcc drops from 5V to 4V due to some reason.

In this case, each XOR gate includes an inverter stage and a transistor whose operation is controlled in response to the inverter stage output. Therefore, when the operating power supply potential Vcc drops to, for example, 4V, the inverter stage output “H#
The level also decreases, and the inverter stage output level applied to the gate of the six bus transistors also decreases. A pass transistor is capable of transmitting a voltage equal to the difference between the voltage applied to its gate and the threshold voltage of each unit. Therefore, the signal potential reached from the pass transistor becomes lower than 4V by the threshold voltage of this transistor. Therefore, a plurality of stages of such pass transistors are provided, and the output of the pass transistor on the output side of each XOR gate further decreases. Since this reduced potential level of the output signal is further transmitted through the inverter stage and the transistor in the decoding circuit, it is possible that the signal potential level is further reduced. As the No. 3 potential level decreases, the operating speed of each logic gate decreases (for example, in the case of an inverter stage, the higher the power supply potential, the faster the charging operation of the output level becomes, so the access speed becomes faster. In the opposite case, the access speed becomes slower.If the input potential level applied to the input logic gate approaches its input logic threshold, each logic gate will no longer be able to perform accurate logic operations. , it is conceivable that an erroneous signal level of 1 and 1 may be transmitted as an output signal.

Therefore, although a circuit configuration is provided to correct data errors in the recording device as described above, the operating margin on the high potential side of this error detection/correction circuit configuration is narrow. However, there are disadvantages in that accurate judgment and correction of data cannot be performed and the judgment operation becomes slow.

In other words, when a circuit configuration for detecting and correcting information errors is provided using a conventional 1-doware configuration using logic gates, the operating margin on the high potential side of the semiconductor memory device becomes narrower, and accurate information cannot be obtained. Error detection and correction cannot be performed, and in addition, the determination operation becomes slow, resulting in a disadvantage that the access time of the semiconductor memory device becomes slow.

In a computer system, a configuration in which an error detection/correction circuit provided outside the main memory is converted into a ROM is disclosed in Japanese Patent Laid-Open No. 101857/1983. This prior art eliminates the need for an increase in the amount of hardware that would occur if the error detection/correction circuit, that is, the check bit generation circuit and the error detection positive circuit, were implemented using logic gates such as an For this purpose, we constructed a check bit generation circuit and an error detection/correction circuit for $14 using R0M, which is widely used, inexpensive, and capable of nJ manual labor. There is.

Therefore, the future JI technology is intended only to improve the error detection/correction circuit provided outside the storage device, and is intended to improve only the error detection/correction circuit provided outside the storage device.
In addition, C1 and others have not taken into account the circuits used in the semiconductor memory device, and have not recognized the problems inherent in semiconductor memory devices that have the above-mentioned error detection and correction functions.

The purpose of this invention is to expand the operating power supply voltage margin of a semiconductor memory device that can overcome error detection and +JiE functions, thereby enabling accurate and high-speed information error detection and :f-correction even if the operating power supply voltage fluctuates. We present a conductive memory device that can be used.

Another object of the present invention is to provide a dedicated memory device 1i, which has a function that allows accurate and high-speed error detection and correction even when the high-potential power supply voltage decreases. be.

Still another object 1-1 of the present invention is to make the operating power supply voltage margin of the error detection/correction circuit built in the semiconductor memory device comparable to the operating power supply voltage margin of the memory cell section included in the semiconductor memory device. The objective is to widen the operating power supply voltage margin of the semiconductor memory device as a whole.

[Means for Solving the Problems] A semiconductor storage device having an error detection/correction iF function according to the present invention has a 3-error TiF encoding circuit and a 1-error+i'J' correct decoding circuit built into the semiconductor storage device. At least one of them is constructed from a mask ROM. That is, the semiconductor memory device capable of error detection and H-correction according to the present invention receives storage information (information bits) given from the outside and generates corresponding check bits, and combines the given information bits and the generated check bits. Error in linking and outputting ;! In response to the J'In 71 encoding circuit and external address, an information bit and an inspection pin I linked to this information bit are read out from the selected memory cell, and errors in the read bit data are detected and corrected. At least one of the error correction decoding circuits that output the rear information bits receives the given data as an address input, and is a mask ROM that stores data to be output corresponding to each address.
It is characterized by being composed of.

[Function] The error correction encoding circuit or the error correction decoding circuit portion in the form of a mask ROM in the present invention is compatible with the memory cell array portion and peripheral circuits (including the test memory cell array) of this semiconductor storage device and this peripheral circuit portion. It is possible to have a similar circuit configuration, there is no need to provide several stages of logic gates (especially Can be set to the same degree,
This makes it possible to make the voltage margin of the correction encoding circuit or the error correction decoding circuit comparable to that of the memory cell array, thereby realizing a wide operating power supply voltage margin for the entire semiconductor memory device. .

[Embodiment of the Invention] FIG. 1 is a block diagram schematically showing the overall configuration of a semiconductor memory device that is an embodiment of the invention.

Referring to FIG. 1, a semiconductor device according to an embodiment of the present invention i
13 devices are integrated and formed on the semiconductor chip 100. On the semiconductor chip 100, in order to input and output signals, there are X address input terminals 21a to 21m, Y address input terminals T-22a to 22n, and data input/output terminal 2.
3a-231 and control signal input terminals 25-27 are provided.

Control signals WE (write enable No. 1, υ enable signal) applied to the control signal input terminals 25 to 27, respectively, are applied to the control signal generation circuit 3o. qr+r
TSTA issue is here! 1 path 3υ is a semiconductor memory device in response to a signal W specifying a write/read operation mode of the semiconductor memory device and a signal n indicating selection/non-selection of an output enable device that provides data write/read operation timing. Generates various control signals to control the operation of the storage device.

The various control signals generated by this control t= signal generation circuit 30 are
It differs depending on whether it is M or SRAM.

The X address applied via the X address input terminals 21a to 21'n is applied to the X decoder 3.

The X decoder 3 selects the corresponding row of the information bit memory cell array 1 and the test memory cell array 2 in response to the applied X address. Y address input terminal 22
a~22nni. The obtained X address is given to the Y decoder 4. Y decoder 4 beams. In response to the obtained Y address, a corresponding column is selected from information bit memory cell array 1 and test memory cell array 2.

The data input/output terminals 2 3 a to 23 i are coupled to a data output circuit 6 . The data output circuit 6 shapes the waveform of the given data, and when writing data, gives information bits from the outside to the error correction 11: encoded mask ROMI O.
When reading data, data from the error decoding mask ROMII is waveform-shaped and applied to data input/output terminals 23a to 23i.

The error correction encoded mask ROM10 receives storage information (information bits) given from the data input/output circuit 6 as an address input, and checks check bits (information bits) corresponding to the given information bits.
(see FIG. 8) are stored in advance, and the given information bits and the check bits stored in the mask ROM are linked and applied to the write/read circuit 5.

The write/read circuit 5 is an error correction encoded mask ROM10.
The information bit and test bit obtained from j'y are written into the selected memory cell of the information bit memory cell array 1 and the test memory cell array 2, respectively.

The error decoding mask ROMI 1 receives information bits and check bits from a selected memory cell during data reading via the write/read circuit 5. The error decoding mask ROM II takes the given information bits and check bits as its address inputs, and stores the information bits and check bits corresponding to each address in a mask ROM.

In writing and reading data in a semiconductor memory device, when input data is given, a check bit or information bit to be generated is uniquely determined according to a check matrix or a generation matrix. Therefore, if each error correction encoding circuit and error decoding circuit are made into a mask ROFvl and input data is used as an address signal for each mask ROM,
Desired test bits and/or information bits can be easily generated.

FIG. 2 is a diagram showing an example of a specific configuration of the error correction encoding mask ROM10, which is an embodiment of the present invention. Second
Referring to the figure, the mask error correction encoding mask ROM10 includes a decoder section that decodes the information bits DO and DI obtained at t4, and a ROM memory section that stores check bits corresponding to input information in advance. In the configuration of FIG. 2, the configuration is shown where the information bits are 2 bits and the check bits are 3 bits, and the generation matrix used for generating the check bits follows the table shown in FIG. 8. An example is shown in which the same one is used. The decoder section includes an inverter 121 receiving information bit 1-D0, an inverter 122 receiving information bit D1, and four NOR gates 1-N1-N4. NOR gate N1 inputs information bit DO and information bit D.
1 and receive.

NOR gate N2 receives the inverter 122 output and information bit D1. NOR gate N3 inputs information bit D
0 and the inverter 122 output. NOR gate N
4 receives the output of the inverter 21 and the output of the inverter 122. The outputs of the NOR gates N1-N4 are connected to word lines WL1-WL4 of the ROM memory section, respectively.

In the RO-1 memory section, memory transistors M1-M6 are arranged so as to provide a "1""0" pattern similar to the submatrix corresponding to the check bit generation matrix of the generation matrix G. Here, in the ROM memory section, memory transistors are arranged at the intersections of word lines and bit lines, and depending on the thickness of the gate oxide film of each memory transistor, the "0" degree of stored information is It is structured so that memory can be carried out. however,
In the configuration of FIG. 2, only memory transistors M1 to M6 storing information "0" whose gate oxide films are thinned are shown. Specifically, in the ROM memory section, memory transistors M11M2 and N3 are provided at each intersection of word line WLI and bit lines BLI to BL3. A memory transistor M4 is provided at the intersection of word line WL2 and bit line BL3. Word 3Gt w L
A memory transistor M5 is provided at the intersection of bit 3 and bit 99 B L 2. Word mWL4 and bit line BL
A memory transistor M6 is provided at the intersection with I. Bit lines BLI to BL3 are connected to sense amplifier 9.

The sense amplifier 9 detects and amplifies the potentials on the outputs of the bits tlL1 to BL3, and then outputs them as test bits P1 to P3. That is, the (m-numbered bell on bit line BLI gives test bit P1, the ta signal bell on bit lines B and L2 gives test bit P2, and the signal level on bit line BL3 gives test bit P3. give.

FIG. 3 is a diagram showing an example of a specific configuration of an error decoding mask ROM of a semiconductor memory device according to Embodiment 1 of the present invention. Even in the configuration shown in FIG. 3, the case where the decoding is the same as the table shown in FIG. 8 is shown as an example. Error decoding mask ROMI with reference to FIG.
1 has a decoder part and a memory part. The decoder section has 5 inverters 141 to 146 and 32 NO
R gates NIO to N12 are provided. However, this is the case where the information bits are 2 bits and the check bits are 3 bits. This decoder section has an NOR type decoder configuration, and generates complementary information data DO, Di, and P1 to P3 from input information Do, DI, and P1 to P3, and generates complementary information data DO, Di, and P1 to P3 for each N
The configuration is such that decoding is performed using OR gates NIO to N12 and a corresponding word line is selected from the ROM memory section. For example, NOR gate NIO uses information bits DO, D1 . ) receives A check bits PI, P2 and P3. NOR game 1-
N11 receives information bit DO, information bit Di, check bits l-r'1, P2 and inversion bit P3.

NOR gate N12 is each inverter! 41-I42 outputs, ie inverted information bits DO.

Dl and inverted check bits P1-P3 are received.

In the ROM memory section, input information DO, DI~P1~P3
Read information bits corresponding to are stored in ROM. In other words, this ROM memory section is connected to each NOR gate N.
It has a configuration in which 32 word lines and two bit lines are provided for IO to N12, and the thickness of the gate oxide film is set at the intersection of each word line and bit line according to the stored information. A memory transistor is provided. The bit line output is applied to the sense amplifier 9, where it is amplified and then output as read information Do, D1. Next, the operation will be briefly explained.

Now, consider a case where the stored information (information bits) given from the outside via the data output terminals 23B to 231 is (1, 0). In this case, error + i J' correct 7 cocoding R
In OM10,! Information bit obtained (1,0)
In response to this, only the NOR gate N3 output becomes 'H', and the remaining NOR gates N1, N2 and N4 outputs become 'L'.
゛ level.

As a result, the potential of the word line WL3 rises and the memory transistor M5 is turned on. As a result, the potential on the bit line BL2 is discharged to the "L" level, and the outputs of the remaining bit lines BLI and BL3 become the precharged "H" level. This bit line BLI, BL
The potentials (H, L, H), that is, (1°0.1) appearing on BL2 and BL3 are sensed and amplified by the sense amplifier 9, and then output as test bits P1 to P3. In the above description, the precharge paths for each bit line BLI to BL3 are similar to those provided in a normal ROM circuit, and are omitted to avoid clutter δ in the drawings. Generated via this sense amplifier 9 (
1.0. Check bits PL, P2 and P3 in 1) are information bits DO.

It is linked with Dl and given to the write/read circuit 5. The write/read circuit 5 writes information bits and test bits to memory cells in the information bit memory cell array 1 and test memory cell array 2 that have already been selected via the X decoder 3 and the Y decoder 4, respectively. This completes the write operation.

During the above-described data write operation, the configuration shown in FIG. 2 does not show a configuration that outputs the information bits DO and DI, but this configuration may be configured to allow the information bits DU and DI to pass through as is. The configuration may be such that information bits corresponding to this information bit are written in the ROM memory section.

In this data write path, the decoder section has a NOR type decoder configuration, and this configuration is similar to the configuration of the X decoder 3 and Y decoder 4 provided in the memory cell array section. The voltage margin can be made comparable to the margin provided for the memory array section. In other words, even if the operating power supply voltage decreases, this decrease in operating power supply potential will appear in the NOR gate output, but since this output is transmitted on the word line,
This is similar to the word line selection operation in a normal memory cell array, and the operating margin can be set to the same level as the memory cell array. You can change the operating margin.

Note that in the above explanation, the selection operation of memory cells in the memory cell array 1 and the test memory cell array 2 was not explained, but this is because the X address and Y address are After being taken into the X decoder and Y decoder 4, a selection operation for the memory cell array is performed in response to a control signal from the control circuit 30. This is done in response to signals WE and OE.In other words, when write enable signal WE is active 'L#' and output enable signal ODE is inactive H' during data writing, data is transferred to data input/output circuit 6. The data readout operation will be described next.

In addition, in response to the external control signal CE, the X address and Y address are given to the X decoder 3 and Y decoder 4, respectively, and after being decoded there, the corresponding memory cells are selected from the memory cell array 1 and the test memory cell array 2. and the information bits and check bits in each are read out. The read information bits and check bits are passed through a write/read circuit 5 to an error decoding mask R.
Given to OM11. The error decoding mask ROM 11 stores the given information bits Do, DI and check bits P1 to P.
3 as the address input, and the fixedly stored information corresponding to λ·1, that is, the information stored in the ROM is read out. That is, for example, if the information bits are (1, 0) and the check bits are (1, 0, 1), the address (1, 0, 1, (
1, 1) Accordingly, (1, 0) is made into a mask ROM and the word line corresponding to this address is selected, and its contents are sent through the sense amplifier 9. The data is then returned to the data input/output circuit 6 as read information DO, DI. Data input/output circuit 6 outputs the applied data as read data in response to control signals WE and OE.

If a 1-bit error occurs for some reason, that is, if the read bits from memory cell array 1 and test memory cell array 2 are (1° 1.1, 0.1) (information bit DO is incorrect). place, ¥), (0,0
, 1, 0, 1) (if information bit D1 or error)
, (1,0,0°0.1) (when check bit P1 is in error), (1,0,1,1,1) (in other words, when check bit P2 is in error), (1 ,o,1,0.O
) (that is, when check bit P3 is in error), the write information (1, 0) is stored in a mask ROM corresponding to this case, so that the error decoding circuit 11 can read the data more accurately. be done a) be done;

That is, as a result, information is read out with errors in the information corrected.

Even in this data read case, the decoding mask RO
The decoder section of MII is the same as the decoder section provided corresponding to the memory cell array section.

Since it has an R-type configuration, this power supply voltage operating margin can be made similar to that provided in the memory cell array section, and the operating power supply voltage margin of the semiconductor memory device as a whole can be improved. .

For other combinations of information bits and check bits, the corresponding mask ROM information is similarly read out by the decoder section, and after the information is detected and corrected, the data is input. It is read out via the output circuit 6.

An example of the structure of a mask ROM is shown in FIGS. 4A to 4C. Figure 4A shows an example of the configuration of the mask ROM circuit (1-), Figure 4B shows its back and r-out, and
Figure C shows a partial cross-sectional structure.

In FIG. 4A, the mask 110M is shown in FIG.
Memory transistors Mln, Ml' whose oxide films are made thinner and store information "0" (and memory transistors Mll, whose gate oxide films are made thicker and which store information "1°")
M12 is provided. Word line WLlo connects memory transistor ~110. M11 is selected, and the information of each memory transistor MIO, M]1 is transferred to the bit line BL20. B
It is transmitted onto L21. Word line WLII connects memory transistor M12. M13 is selected and three memory transistors M12. The information of M13 is bit wBx-20,
It is transmitted onto BL21.

Referring to FIG. fl'UB, the gate oxide films of memory transistors M10 and M 1 B are made thinner, and the film thicknesses of memory transistors M11° and M12 are made thicker. The thinner the gate oxide film is, the lower the threshold voltage is, while the thicker the gate oxide film jv is, the higher the threshold voltage of the memory transistor is. Therefore, even if the same voltage is applied to the gate of the memory transistor through the word line, the memory transistor with the thinner gate oxide film is conductive, while the memory transistor with the thicker gate oxide film is non-conducting. It remains conductive. As a result, information "0" and "1" are stored.

FIG. 4C is a diagram showing a cross-sectional structure taken along line xx' shown in FIG. 4B. The memory transistor M12 that stores information “1” is located in the source diffusion layer 2 on the semiconductor substrate 200.
01a, a drain diffusion layer 201b, a thick gate oxide layer 201b thereon, and a gate electrode 203.

The memory transistor M13 that stores information "0" has a source diffusion layer 201C connected to a bit line, a drain diffusion layer 201b connected to a ground potential, a thin gate oxide film A thereon, and a gate serving as a word line. and an electrode 203. As described above, information can be easily stored by simply changing the gate oxide film 1117.

Also, by changing this configuration, the film thickness of the word line and gate electrode is kept constant without changing the film thickness of the gate oxide film.
There is also a tM configuration in which information is self-memorized by making contact between each gate electrode and a word line.

FIG. 5 is a diagram showing the structure of a FA~(OS cell) used as a storage cell in a normal memory cell section. Referring to FIG.
, 9 impurity regions 303a, 3t)lb formed on the substrate 300 to become source and drain diffusion layers, and impurity regions 303a, 3t)lb formed on the semiconductor substrate 300 via an interlayer insulating film 3L14, and a Enter information according to
Therefore, the memory cell structure of the memory cell array is as follows:
In case of FAMOS cell structure as shown in the figure 1. ! The ROM for N9 detection and decoding can be formed in the same manufacturing process as the memory cell transistor in the memory cell 7 Louis, compared to the case using conventional logic gates. , it is possible to significantly shorten the time by about 1-1. That is, in the thin part of the gate oxide film, the gate electrode is connected to the floating gate 302.
The mask ROM can be easily formed in the same manufacturing process by forming the gate electrode in the thick part of the gate oxide film in the same manufacturing process as the control gate 1-303. Can be done. In this case, when information is stored in the mask ROM not by the thickness of the gate oxide film but by the contact between the gate electrode and the word line, the structure shown in FIG. Floating game! - It becomes possible to configure a mask ROM with the same manufacturing time t2 as any of 302.

The memory cell structure included in these two memory cell arrays 1 and 2 is a FAMOS cell structure (normal DRAM).
Even in the case of a cell (see Figure 6), the memory transistor of the ROM is a game! - Even in the case of storing information depending on the thickness of the oxide film or the presence or absence of H between the gate electrode and the contact electrode, the memory transistor of the ROM can be formed in the same manufacturing process as the transistor of the memory cell array section. That is, referring to FIG. 6, the gate electrode 400 of the DRAM cell or the cell plate 401 which becomes one electrode of the information storage capacitor is manufactured in the same manner as the gate electrode 400 of the ROM memory transistor. l1l-n can be formed, and the error detection n-positive RO~1 can be easily formed as a mask ROM without complicating the manufacturing process. Referring now to FIG. 6, the DRAM cell is composed of a semiconductor substrate 405, an impurity diffusion region 406a serving as a source, an impurity diffusion region 406b serving as a drain, and a gate insulating film 407.

Here, in FIG. 5(b) and FIG. 6Cb), etc. of FAklOS cell and DRA Fb1 cell, respectively (
+tfiH route.

[Effects of the Invention] As described above, according to the present invention, it is possible to perform error detection and error correction in a conductor storage device by performing error detection and error correction in a conductive memory device by performing a code circuit portion and a decoding circuit portion. Mask RO
M for 11? I achieved it, so it's 1.2X, huh? j゛ Positive 7 code and 1 (the naturalized circuit part is the same $1.L configuration as the memory cell array part and its related peripheral circuit part which constitute the conductor register ta device) This makes it possible to make the operating power supply voltage margin of the error H positive 71 specific gravity circuit part and the decoding circuit part the same as the operating power supply voltage margin of the information bit and check bit register part and its related peripheral circuit part. This makes it possible to provide a wide operating power supply voltage margin for the semiconductor memory device as a whole, and to read data at high speed even when the power supply voltage fluctuates by λ·l.
It is now possible to create a semiconductor memory device that will make this possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the overall +1-1 configuration of a conductor storage device according to an embodiment of the present invention. FIG. 2 shows error correction in a half-J9 memory device, which is an embodiment of the present invention. ] is a diagram showing an example of a specific configuration of a number specific gravity disk ROM. FIG. 3 shows the decoding masks RO to 1 (1
FIG. 3 is a diagram specifically showing an example of the formation of 48 to 4C are diagrams showing an example of a specific configuration of a mask ROM, FIG. 4A is a diagram showing an example of an equivalent circuit of a mask ROM, and FIG. 4B is a mask shown in FIG. Figure 4C shows the 114 structure of the blank line x-x' in Figure 4B. Figure 5 shows the memory cell array r out. 1υ1ITi when using FA to IOS cells as memory cells
'i+1tS structure and the equivalent circuit are shown schematically. Figure 6 shows the memory cell [,1
DRAM when using DRAM cell as 4-structure
FIG. 2 is a diagram showing a cross-sectional structure of a cell and its cavity 1i1ti circuit. FIG. 7 is a diagram showing the overall configuration of a conventional semiconductor device in Itm3 terms. Figure 8 is! 1' is a diagram listing the input/output χ·1 correspondence during 7.1 encoding and decoding for error detection 5J in a conductive storage device. Figure 9 shows the conventional semicircular system ω, error in the device:
”Correct? ] A diagram showing an example of the configuration of an encoding circuit and a decoding circuit at a logical level, and shows the configuration according to FIG. 8. FIG. 10 is a circuit diagram showing a more specific circuit configuration of the error correction circuit and error decoding circuit shown in FIG. In the figure, 1 is a memory cell array for storing information bits, r12 is a test memory cell array for storing test bits I, ' is an X decoder, 4 is a Y decoder, and 5 is a write/read circuit. , 6 is a data output circuit, 10 is an error correction +E7T1 encoding mask ROM 111 is an error decoding mask ROM, and 100 is a semiconductor chip. In the figures, the same reference numerals indicate the same or the same parts.

Claims (1)

[Claims] It has a plurality of memory elements, and during a data write operation, generates test information in response to memory information given from the outside, adds the generated test information to the memory information, and thereby writes at least one bit of data. means for writing the code word into a storage element selected by an external address after forming an error-detectable/correctable code word; A semiconductor memory device that reads a code word, performs error detection and correction on the read code word, and then outputs stored information included in the corrected code word as read information. At least one of the generation means and the error detection/correction means is configured using a read-only storage device that takes given information as an address input and stores output information corresponding to the given information in correspondence with each address, A semiconductor memory device having an error detection/correction function, wherein the read-only memory device is formed on the same semiconductor chip as the plurality of memory elements.