DE3936704A1 - Error-detecting cellular semiconductor memory with codeword generator - includes writing and read=out circuits for test data and stored codewords, integrated on same memory chip - Google Patents

Abstract

The chip (100) includes a circuit (10) for generating a code for error detection and correction purposes on the basis of data supplied from outside, and for combining the data and code for transmission to a storage cell field (1). Another circuit (11) checks and corrects the read-out data which are built up from the stored data and code. The codeword generator (10) and error detection/correction circuit (11) are incorporated in a masked read-only memory which is integrated on the same chip with the storage cell field (1) and X and Y decoders (3, 4). ADVANTAGE - Margin of operating supply voltage is widened so that error detection and correction can be performed quickly and accurately, even when voltage fluctuates with considerable decline from its higher level.

Description

The invention relates to a semiconductor memory device. In particular, it relates to improvements a circuit for error checking / correction and one Circuit for generating a code word, which is an error can check / correct, as in semiconductor memory devices Large capacity with error checking / correction functions available.

When in a semiconductor memory device such as an EEPROM (an electrically writable and erasable non-volatile Semiconductor device), a DRAM (a dynamic random access memory) or an SRAM (a static random access memory) their capacity increases, the number of defective memory cells too, and therefore it is believed that a conventional redundancy memory cell system does not have one can cope with such a situation. It continues sometimes during the operation of a semiconductor memory device  before that incorrect data is written or read are due to latently defective cells that are not have been discovered when the establishment was launched due to noise and the like. Therefore have been error checking and error correction functions for some time large for data in a semiconductor memory device Capacity added. First, a method for error checking / correction of information to be described, whereby the Hamming code, which is one of the is usually taken linear codes.

First, consider a two-dimensional block code of length n . A code that regards as a code word all the rows w = (x 1, x 2, ... , X _n ) that satisfy the following system of linear equations is called a linear code.

α ₁₁ x ₁ + α ₁₂ x ₂ + · · · + a _{1 n} x _n
= 0
α _{21 x 1} + α _{22 x 2} + · · · + α _{2 n} x _n (mod. 2)
= 0
. . .
α _{m 1} x ₁ + a _{m 2} x ₂ + · · · + α _mn x _n
= 0
m < n ,
x _i ∈ (0, 1)
i = 1,. . ., n ,

where a _ÿ (i = 1, _... , n ; j = 1,..., n) is assumed to be constant with the value 0 or 1, and an operation is carried out taking Boolean algebra into account.

The system of equations above is called the parity check equation, while the coefficient matrix of this parity check equation, as shown below is called a parity check matrix.  

In the parity check equation, variables that are independent can be chosen, called information bits, while Variables determined based on the selected variables are called check bits.

Assuming a code is w , the parity equation can be expressed as follows:

Hw ^T = 0 (mod. 2),

where w is the code word described above and T is a symbol representing the transposition.

In the parity check matrix described above, the one that the takes the following form, in particular a canonical parity check matrix called:

where I _{m is} the unit matrix of size m × m .

Here the check bits contain the first m bits (x 1, x 2,..., X _m ). The relationship between the information bits and the check bits in the case of the canonical parity check matrix is given by the following expression:

(x ₁... x _m ) = (x _{m +1} , _... , x _n ) P ^T (mod. 2)

Therefore, if the information bits (x _{m +1} , _... , X _n ) are selected arbitrarily, the check bits corresponding to them are uniquely determined.

According to the canonical parity check matrix described above the matrix shown below becomes a generation matrix called:

In the above parity check matrix H, if each column is non-0 and there is no column that is the same as another, a code generated by the generation matrix G associated with the matrix H is called a Hammig code or a Hamming single error correction code .

For the code word w is

s = Hw ^T (mod. 2)

called the syndrome "s" by w . Since the syndrome s = 0 for an error-free code word w , the code word contains an error if the syndrome s of a given code word is not 0. If the code word is as follows

contains a single error pattern, the syndrome is s

s = H (w + e _i ) ^T = He _i ^T.

The syndrome s is therefore equal to the first column of the parity check matrix H.

If the given code word, a Hamming Code is, each column of the check matrix H is not 0, and there is no column that is a different equal so that s have information with a single error syndromes patterns different from each other. Hence, error checking and error correction can be performed by taking the syndromes of the given data and adding the individual error patterns corresponding to them to the given information.

Correct data writing / reading in the semiconductor memory device is by applying the code word described above carried out that can correct / check an error. The means that when data is written, check bits for the external given data, and then those for the given Data to be written generated test bits with the data to be written Data connected to be saved. At the Data are read in a memory cell that is accessed is stored information and the related Check bits both read to form a code word, and that Error checking and correction based on the code word, is executed, which ensures correct and correct data reading can be executed. The configuration and operation of the Semiconductor memory device, the error checking / correction functions according to the theory described above will now described below.

As shown in Fig. 1, a semiconductor memory device has a memory cell array 1 for storing information which is provided externally (hereinafter referred to as information bits), and a memory cell array 2 for testing, which a plurality of memory cells for storing test information, respectively the information bits of the memory cell array 1 are generated (hereinafter referred to as check bits). The memory cell array 1 contains the memory cells arranged in a plurality of rows and columns. The memory cell array for checking also contains a plurality of memory cells.

To select the memory cells of the memory cell array 1 is an X decoder 3 for decoding an X address, which is applied via X address input connections 21 a to 21 m to generate a row selection signal, and a Y decoder 4 for decoding a Y address, the m for generating a column selection signal Y is applied via a -Adreßeingangsanschlüsse 22 to 22 is provided. The row and column selection signals from the X decoder 3 and the Y decoder 4 are also supplied to the memory cell array 2 for testing.

Furthermore, a data input and output circuit 6 is provided for inputting data into and outputting data from an external device via data connections 23 a to 23 i for inputting and outputting data. An error correction coding circuit 7 is provided for receiving the information bits which are applied via the data input and output circuit 6 for generating the check bits in accordance with the predetermined generation matrix. The test bits generated are added to the information bits created in order to match them. A read / write circuit 5 is for writing the information bits from the error correction coding circuit 7 into the selected memory cells in the memory cell array 1 and also for writing the check bits into the selected memory cells in the memory cell array 2 for checking and for reading the information bits and the check bits from the memory cells that are selected when reading data are provided. Finally, there is an error decoding circuit 8 for picking up the information bits and the check bits sent from the read / write circuit 5 for checking and correcting an error of the read data (information bits and check bits) and then for applying the information bits (which are corrected) to the data terminals 23 a to 23 i provided via the data input and output circuit 6 . This semiconductor memory device is integrated on a semiconductor chip 100 .

In the following, the operation of a semiconductor memory device with a dual configuration is described as an example, ie with a configuration in which the data input and output takes place in two-bit units. Furthermore, the following matrix is regarded as the generation matrix G , which is used in the error coding circuit 7 .

The following matrix is then taken as the test matrix H , which is used in the error decoding circuit 8 :

Assuming that the externally applied information bits are D 0, D 1, while the check bits dependent on the information bits are P 1, P 2, P 3, in the above arrangement, a code word w capable of errors becomes Check and correct as follows:

When the error decoding circuit 8 is operated with the test matrix H described above, a syndrome s is generated from the read code word (a combination of information bits and test bits) according to the following expression:

If the syndrome s is not 0, it is identical to a column vector of the test matrix H. Therefore, error correction is carried out by checking which column vector of the check matrix H is equal to this syndrome and by inverting a bit value of the column that corresponds to this column vector.

A relation between input and output of the coding and decoding described above is shown in FIG. 2. The operations of writing and reading data from the semiconductor memory device are described below with reference to FIGS. 1 and 2.

The case is now considered in which two-bit data (0, 1) are applied externally via the data connections 23 a to 23 i . The external data (a code word) is transmitted to the error coding circuit after its pulse shape is formed in the input and output circuit 6 . The error coding circuit 7 generates check bits (1, 1, 0) from the applied information bits (0, 1) in accordance with the above generation matrix G and adds the generated check bits to the applied information bits and feeds them to the read / write circuit 5 . Furthermore, the X address and the Y address are correspondingly applied to the X decoder 3 and the Y decoder 4 through the X address input connections 21 a to 22 m . Both the X decoder 3 and the Y decoder 4 decode the applied addresses to select the corresponding row and column in the memory cell array 1 and the memory cell array 2 for checking. The information bits from the read / write circuit 5 are written into the selected memory cells of the memory cell array 1 , while the test bits are written into the selected memory cells of the memory cell array 2 for testing. Consequently, the information bits and the check bits are combined to be stored in the memory cell array 1 and the memory cell array 2 for checking.

The reading activity is described next. The X address and the Y address are supplied to the X decoder 3 and the Y decoder 4 via the address input connections 21 a to 21 m and 22 a to 22 m, respectively. The X decoder 3 and the Y decoder 4 decode the supplied addresses to select their corresponding memory cells in the memory cell array 1 and the memory cell array 2 for checking. As a result, the information bits are read out from the selected memory cells of the memory cell array 1 , while the test bits are read out from the memory cell array 2 for testing.

The read out information bits and check bits are applied to the read / write circuit 5 and then to the error decoding circuit 8 . The error decoding circuit 8 performs error checking and correction of the information bits and the check bits from the supplied information bits and check bits according to the table shown in FIG. 2. Now consider the case where the information bits read are (0,1) and the check bits are (1, 1, 0). In this case, there is no error in the code word read (information bits and check bits), so the information bits (0,1) are output from the error decoding circuit so that they are sent outside the device through the data input and output circuit and the data terminals 23 a to 23 i are transmitted. Let us now consider the case in which the (0, 1) information bits to be read are actually read as (0, 0), i.e. as a one-bit error, due to certain errors in the memory cells, noise or the like. In this case, since the check bits associated with the information bits to be read out to be stored are (1, 1, 0), the error correction decoding circuit 8 corrects the read data (0, 0) in (0, 1) and then applies them to the Data input and output circuit 6 on, as shown in Fig. 2. In the case where one-bit error occurs only in the check bits from the memory cell array 2 for checking, there is no error in the information bits (0, 1) as shown in Fig. 2, so that the read information bits (0, 1) be applied to the data input and output circuit 6 via the error decoding circuit 8 .

As has been described, correct data reading can be performed will. It can also be done in the case in which the data read differs from the data originally written is due to some Cause (error in the memory cell, noise, etc.).  

As mentioned above, the semiconductor memory device with the error correction function enables the occurrence of check bits and the addition of the check bits to the information bits according to the predetermined generation matrix and check matrix for error checking and correction in the read code word (information bits and check bits). Therefore, if the externally created information bits are determined, the corresponding check bits added to them are clearly determined. And also a read code word, the data to be output by the error decoding circuit 8 are clearly determined according to the test matrix. Therefore, the error correction encoding circuit 7 and the error decoding circuit 8 are implemented on a hardware basis using logic gates in the semiconductor memory device. The detailed configuration of the error correction coding circuit and the error decoding circuit will now be described.

Fig. 3 is a diagram showing the detailed arrangement of the error correction encoding circuit and the error decoding circuit at a logic level when the semiconductor memory device-bit units Two inputs data to and outputs. As shown in FIG. 3, the error correction coding circuit 7 has an XOR gate X 1 for receiving information bits D 0, D 1 which are externally applied, a signal line S 1 for routing the externally applied information bit D 0 and a signal line S. 2 for routing the externally applied information bit D 1. The output of the XOR gate X 1 provides a test bit P 1, and the signal line S 1 provides a test bit P 2, while the signal line S 2 applies a test bit P 3.

The error decoding circuit 8 has five XOR gates X 2 to X 6, two inverters I 1, I 2 and two AND gates A 1, A 2. The XOR gate X 2 receives the information bits D 0, D 1 from the memory cell array 1 and the test bit P 1 from the memory cell array 2 for testing. The XOR gate X 3 receives the information bit D 1 and the check bit P 2. The XOR gate X 4 receives the information bit D 1 and the check bit P 3. The inverter I 1 receives the output of the XOR gate X 3. The inverter I 2 receives the output of the XOR gate X 4. The AND gate A 1 receives the output of the XOR gate X 2, the output of the XOR gate X 3 and the output of the inverter I 2. The AND gate A 2 receives the output of the XOR gate X 2, the output of the inverter I 1 and the output of the XOR gate X 4. The XOR gate X 5 receives the information bit D 0 and the output of the AND gate A 1. The XOR gate X 6 receives the information bit D 1 and the output of the AND gate A 2. The corrected information bits D 0, D 1 passed through the XOR gates X 5, X 6 are then applied to the data input and output circuit 6 . By implementing the error correction coding circuit and hardware decoding circuit as described above, the error checking and correction can be performed faster than on a software basis.

However, when a hardware-based error checking / correction code circuit is constructed as described, it has a number of logic gates so that when a supply potential applied thereto fluctuates, the potential level of each logic gate output also fluctuates. As a result, there arises a problem that the speed of the logical operations performed on the data decreases and an erroneous logical operation is also performed. This problem is described in detail with reference to FIG. 4.

As shown in Fig. 4, the XOR gate X 1, which is included in the error correction coding circuit, has a CMOS inverter stage, which consists of a p- channel MOS transistor T 1 and an n- channel MOS transistor T 2 is formed, and a CMOS inverter stage, which is formed from a p- channel MOS transistor T 3 and an n- channel MOS transistor T 4. The inverter stage formed from the transistors T 1, T 2 receives the information bit D 0. The inverter stage formed from the transistors T 3, T 4 receives the information bit D 1. Furthermore, the XOR gate X 1 has a pass transistor T 5 which is turned on in response to the output of the inverter stage formed by the transistors T 3, T 4, so that the output of the inverter stage formed by the transistors T 1, T 2 is passed becomes. The XOR gate X 1 further has a pass transistor T 6, which is made conductive in response to the output of the inverter stage formed by the transistors T 3, T 4, so that it passes the information bit D 0. Next 1, the XOR gates X a pass transistor T 7 which is turned on in response to the information bit D 1, so that it transmits the output of the inverter stage formed by the transistors T 1, T 2. The XOR gate X 1 further has a pass transistor T 8 which is turned on in response to the information bit D 1 so that it passes the information bit D 0. Finally, the XOR gate X 1 has an inverter I 3 for inverting the output of the pass transistor 8 so that this output can be output.

Similarly, the error decoding circuit 8 has a logic gate formed from MOS transistors. The XOR gate X 2 has a CMOS inverter stage formed from the transistors T 10, T 11, a CMOS inverter stage formed from the transistors T 12, T 13, a CMOS inverter stage formed from the transistors T 14, T 15 and pass transistors M 16 to M 23. The inverter stage formed from the transistors T 10, T 11 receives the test bit P 1. The inverter stage formed from the transistors T 12, T 13 receives the information bit D 0. The inverter stage formed from the transistors T 14, T 15 receives the information bit D 1. The pass transistors T 16, T 17 are turned on in response to the output of the inverter stage formed from the transistors T 12, T 13. The pass transistors T 18, T 19 are turned on in response to the information bit D 0. The pass transistors T 20, T 21 are turned on in response to the output of the inverter stage formed by the transistor T 14, T 15. The pass transistors T 22, T 23 are turned on in response to the information bit D 1. The output of the XOR gate X 2 is output via the inverter I 4.

The XOR gate X 4 has one of the transistors T 40, T 41 formed CMOS inverter stage, pass transistors T 42, T 43, which are turned on in response to the output of the inverter stage formed by the transistors T 14, T 15, pass transistors T 44, T 45, which are switched on in response to the information bit D 1, and an inverter I 6 provided in an output section.

The inverter I 1 has a CMOS inverter formed from the transistors T 50, T 51.

The inverter I 2 has a CMOS inverter formed from the transistors T 52, T 53.

The AND gate A 1 has input transistors T 60, T 61 and T 62, load transistors T 63, T 64, and T 65, an inverter stage formed from the MOS transistors T 66, T 67, which is provided at the output section .

The AND gate A 2 has input transistors T 71, T 72 and T 73, load transistors T 74, T 75 and T 76, and an inverter stage formed from the transistors T 77, T 78 in the output section.

The XOR gate X 5 has a formed by the transistors T 80, T 81 CMOS inverter circuit, an inverter I 7 for receiving the output of the AND gate A 1, pass transistors T 82, T 83, that of the response to the output Inverters I 7 are turned on, pass transistors T 84, T 85, which are turned on in response to the output of AND gate A 1, and an inverter I 8 provided at the output stage. The corrected information bit D 0 is output by the inverter I 8. The XOR gate X 6 has one of the transistors T 90, T 91, inverter stage formed, an inverter stage I 9 for receiving the output of the AND gate A 2, pass transistors T 92, T 93, which in response to the output of inverter I 9 are turned on, pass transistors T 94, T 95, which are turned on in response to the output of the AND gate A 2, and an inverter I 10 provided at the output stage. The corrected information bit D 1 is output by the inverter I 10.

Sense amplifiers 9 for reading and amplifying the information read out are provided between the memory cell array 1 for the information bits and the memory cell array 2 for check bits and the error coding circuit.

An operating margin on the high potential side of the semiconductor memory device is usually given as 4 V to 6 V, for example. The operating margins on the high potential side of the memory cell fields 1 , 2 are set at 3 V to 7 V greater than the operating margin of this semiconductor memory device. Since the operating margins on the high potential side of the error correction coding circuit and the error decoding circuit are narrow at 4 V to 6 V, the total operating margin on the high potential side of the semiconductor memory device is given by the operating margin on the high potential side of this error correction circuit arrangement.

It is now regarded as the event that the operational supply potential _Vcc is lowered from 5 V to 4 V for some reason. In this case, each XOR gate contains inverter stages and pass transistors that are controlled in response to the output of the inverter stages. Therefore, when the operational supply potential V _{cc is} lowered to 4 V, for example, the "H" level of the inverter stage output is lowered, so that the inverter stage output level applied to the gates of each pass transistor is also lowered. Each pass transistor can only transmit a voltage that is equal to the difference between the voltage applied to each gate and the internal threshold voltage. Therefore, a signal potential transmitted by the pass transistor is lowered further than 4 V by the threshold voltage of this transistor. Since a plurality of such pass transistors are provided, the output of the pass transistor on the output side of each XOR gate is further reduced. The lowered potential level of this output signal is further transmitted to the decoding circuit through inverter stages and pass transistors, so that the potential level of this signal is further lowered. The rate of operation in each logic gate is reduced due to the lowering of the potential level of this signal. As for the operating rate at the inverter stage, for example, the higher the supply potential, the higher the charging rate of its output, so that the access speed is increased. On the other hand, the lower supply potential reduces the loading of the output of the inverter, so that the access rate is reduced. Furthermore, it is believed that in the event that the input potential applied to each logic gate approaches the threshold of the logic gate, not every logic gate necessarily performs a correct logic operation. Therefore, erroneous signal levels are transmitted as output signals.

Despite the provision of the circuits to correct the errors of the data in the storage device as described above has some disadvantages, namely that the Operating margin on the lowered potential side of the Circuits for error checking / correction is narrow, so that the right decision and correction of the data is not can be carried out and / or the necessary Decision making is slower.

If the circuits for checking and correcting the Hardware-based information error while using implemented by logic gates, the Disadvantages on that the operating margin on the lowered Potential side reduced in the semiconductor memory device and correct error checking / correction of the information cannot be executed and / or that the decision-making for it runs more slowly, so that the access time on the semiconductor memory device is deteriorated.

Japanese Patent Application Laid-Open No. 61-101857 is a Computer system disclosed with an arrangement in which one Circuit for error checking / correction outside the Main memory is provided when ROM is formed. With this State of the art is the task, the number of Reduce hardware components when circuits for error checking / correction, d. i.e., a test bit generator circuit and an error checking / correction circuit using logic Gates such as XOR gates, AND gates, etc. are formed. To do this the test bit generator circuit and the Error checking / correction circuit using a ROM formed, "which is commonly and widely used and is available at a low price. " this state of the art only relates to improving one Circuit that relates to error checking / correction  and is provided outside the storage device, it does not refer to a circuit for error checking / correction, those in the semiconductor memory device is included. The problems that a semiconductor memory device with the error checking / correction functions described above are not in this prior art addressed.

It is therefore an object of the invention, the scope for Operating supply voltage of a semiconductor memory device with error checking / correction functions so that the Semiconductor memory device quickly and accurately check for errors and can correct information even if Fluctuations in the operating supply voltage occur.

The semiconductor memory device according to the invention with Error checking functions and error correction functions have one Error correction coding circuit and an error correction decoding circuit on, at least one of which is masked ROM implementation is running. That is, this semiconductor memory device with error checking / correction function the error correction coding circuit for receiving externally applied Information (information bits) for generating related Check bits and for outputting the recorded information bits and the generated test bits, which are connected to each other, and the error correction decoding circuit for reading information bits and the check bits associated with the information bits from the memory cells in response to an external Address is selected, and to output the information bits, after error checking and correction for the read out Bit data is executed, one of which being masked ROM implementation is formed. The masked ROM is used given data as an address for storing the data or for reading out data.  

The error correction coding circuit section or the error correction decoding circuit section in the masked ROM implementation can according to the invention of the same circuit arrangement be like that of a memory cell array section and a peripheral circuit section (including a Memory cell array for testing) in this semiconductor memory device. Even if the operational supply potential fluctuates, the magnitude of the deviations of this Output potential level set to the same orders of magnitude are like that of the memory cell array section and peripheral circuit section since no levels of logic Gates (especially XOR gates) in the error checking / correction circuits are provided. Hence the scope for the supply voltage of the error correction coding circuit part or the error correction decoding circuit portion be made equal to that of the memory cell array section, so that the large margin of the operating supply voltage of the entire semiconductor memory device can be used.

This has the further advantage that in particular a decrease in the high level of the supply voltage can be tolerated.

Further features and advantages of the invention result derive from the description of exemplary embodiments of the Invention based on the figures. From the figures show:

Fig. 1 is a schematic diagram showing the entire arrangement of a semiconductor memory device;

Figure 2 is a table showing the relationship between input and output by encoding and decoding for the error checking and -Correct in the semiconductor memory device.

Fig. 3 is a diagram showing on the logic level of an example of the configuration of an error correction encoding circuit and an error decoding circuit in the semiconductor memory device, wherein the table is applied in accordance with Fig. 2;

Fig. 4 is a circuit diagram showing in more detail the circuit configuration of the error correction coding circuit and error decoding circuit shown in Fig. 3;

Fig. 5 is a schematic block diagram illustrating the entire configuration of the semiconductor memory device according to an embodiment of the invention;

Fig. 6 is a diagram showing an example according to the precise design of a masked Fehlerkorrekturcodier-ROMs in a semiconductor memory device of an embodiment of the invention;

Fig. 7 is a diagram showing a detail of an example for the interpretation of the masked error decoding-ROMs in the semiconductor memory device according to an embodiment of the invention;

8A is a diagram showing an example of equivalent circuit of the masked ROMs.

Fig. 8B is a planar layout of the masked ROM shown in Fig. 8A;

Fig. 8C is a cross-sectional view taken along line XX 'in Fig. 8B.

Fig. 9 is a schematic diagram showing the cross sectional structure, and the equivalent circuit of a FAMOS cell when it is used as a memory cell in a memory cell array; and

Fig. 10 is a diagram showing the cross-sectional structure and the equivalent circuit of a DRAM cell as it is used as a memory cell in the memory cell array.

As shown in FIG. 5, the semiconductor memory device according to an embodiment of the invention is formed integrally on a semiconductor chip 100 . For input and output of signals, 100 X address input connections 21 a to 21 m , Y address input connections 22 a to 22 n , data input and data output connections 23 a to 23 i and control signal input connections 25 to 27 are provided on the semiconductor chip.

A control signal generator circuit 30 is provided with control signals: (a write enable signal), (an output enable signal) and (a chip enable signal) which are respectively applied through the control signal input terminals 25 to 27 . The control signal generator circuit 30 generates various types of control signals for controlling the operations of the semiconductor memory device in response to the signals: the signal for designating the read / write operation mode of the semiconductor memory device, the output enable signal for indicating the time of the write / read operation and the signal for indicating whether the Semiconductor memory device is selected or is not selected. These control signals generated by the control signal generating circuit 30 differ depending on whether the semiconductor memory device is an EEPROM, DRAM or an SRAM.

A through X -Adreßeingangsanschlüsse 21 a to 21 m applied X address is applied to the X decoder. 3 The X decoder 3 selects corresponding rows of a memory cell field for information bits and a memory cell field for checking 2 in response to the X address applied. A through Y -Adreßeingangsanschlüsse 22 a to 22 n Y-scale address is applied to the Y decoder. 4 The Y decoder 4 selects corresponding columns from the information bit memory cell array 1 and the test memory cell array 2 in response to the Y address applied.

The data input and output terminals 23 a to 23 i are connected to the data input and output circuit 6 . The data input and output circuitry shapes the pulse shapes of the given data to apply external bits of information to the error correction encoding masked ROM 10 when writing data, and also forms the pulse shapes of the data from an error encoding masked ROM 11 that when reading data to the data input and output terminals 23 a to 23 i are to be sent.

The error correction encoding masked ROM 10 uses information (information bits) supplied from the data input and output circuit 6 as an address and stores check bits corresponding to the supplied information bits (see Fig. 2) so that the supplied information bits and the Test bits in the masked ROM implementation are connected to one another so that they can be fed to the read / write circuit 5 .

The read / write circuit 5 writes the information bits and the check bits supplied from the error correction encoding masked ROM 10 into the corresponding memory cells selected from the information bit memory cell array 1 and the memory cell array 2 for checking.

The error-decoding masked ROM 11 receives the information bits and the check bits from the memory cells selected when the data is written via the read / write circuit. The error-decoding masked ROM 11 stores the corresponding information bits and check bits of its address in a masked ROM implementation using the supplied information bits and check bits as the address.

When writing / reading data in the semiconductor memory device the check bits or information bits to be generated are unique determined according to a test matrix or a generation matrix, if input data are specified. Therefore, if both the error correction coding circuit as well as the error decoding circuit realized by the masked ROM implementation and the input data as the address signal for each masked ROM is used, the desired check bits and / or information bits are easily generated.

As shown in Fig. 6, the error correction encoding masked ROM 10 has a decoder section for decoding applied information bits D 0, D 1, and a ROM memory section for pre-storing check bits associated with the input information. Fig. 6 shows the configuration in which the information bits consist of two bits, while the check bits consist of three bits. It also shows an example in which the same generation matrix as the generation matrix used in the table of Fig. 2 is used to generate the check bits. The decoder section has an inverter I 21 for receiving the information bit D 0 and an inverter I 22 for receiving the information bit D 1 and four NOR gates N 1 to N 4. The NOR gate N 1 receives the information bits D 0 and D 1. The NOR gate N 2 receives the output of the inverter I 21 and the information bit D 1. The NOR gate N 3 receives the information bit D 0 and the output of the inverter I 22. The NOR gate N 4 takes the output of the inter-ester I 21 and the output of the inverter I on the 22nd The outputs of the NOR gates N 1 to N 4 are connected to corresponding word lines WL 1 to WL 4 in the ROM memory section.

In the ROM memory section, memory transistors M 1 to M 6 are arranged to represent a "1" and "0" pattern which is identical to a sub-matrix corresponding to the matrix for generating the check bits in the generation matrix G. In the ROM memory section, each memory transistor is provided at the intersection of each word line and bit line, and thus a configuration is made such that the information "0", "1" is stored according to the thickness of the gate oxide film of each memory transistor. However, the arrangement shown in Fig. 6 shows only the memory transistors M 1 to M 6 for storing the information in "0" in which the gate oxide films are made thin. As will be described in detail, the memory transistors M 1, M 2 and M 3 are provided at the intersections of the word lines WL 1 and the bit lines BL 1 to BL 3 in the ROM memory section. The memory transistor M 4 is provided at the intersection of the word line WL 2 and the bit line BL 3. The memory transistor M 5 is provided at the intersection of the word line WL 3 and the bit line BL 2. The memory transistor M 6 is provided at the intersection of the word line WL 4 and the bit line BL 1. The bit lines BL 1 to BL 3 are all connected to a sense amplifier 9 . After the sense amplifier 9 detects the potentials on the outputs of the bit lines BL 1 to BL 3, it amplifies them and outputs them as test bits P 1 to P 3. That is, the signal level on the bit line BL 1 represents the test bit P 1, while the signal level on bit line BL 2 represents test bit P 2, and the signal level on bit line BL 3 represents test bit P 3.

The arrangement shown in FIG. 7 also represents an example of the decoding which is identical to that shown in the table of FIG. 2. As shown in Fig. 7, the error decoding masked ROM 11 has a decoder section and a memory section. The decoder section has five inverters I 41 to I 46 and thirty-two NOR gates N 10 to N 12. In this case the information bits consist of two bits, while the check bits consist of three bits. This decoder section is of an arrangement of the NOR type decoder; that is, from the configuration for generating complementary information data, and up to input information D 0, D 1 and P 1 to P 3, for decoding in the corresponding NOR gates N 10 to N 12 and for selecting the corresponding word line from the ROM Storage section. For example, NOR gate N 10 receives information bits D 0, D 1 and check bits P 1, P 2 and P 3. The NOR gate N 11 receives the information bits D 0, D 1, the check bits P 1, P 2 and an inverted bit. The NOR gate N 12 receives the output from each of the inverters I 41 to I 42, that is, the inverted information bits, and the inverted check bits 14 to 14.

The read-out information bits, which correspond to the input information D 0, D 1, P 1 to P 3, are stored in the ROM implementation in the ROM implementation. That is, this ROM memory section has a configuration such that thirty-one word lines and two bit lines are provided for each NOR gate N 10 to N 12, and a memory transistor whose thickness of the gate oxide film is determined according to the stored information at the intersection each word line and bit line is provided. The output of a bit line is applied to the sense amplifier 9 and, after being amplified therein, it is output as readout information D 0, D 1. Its operation is briefly described below.

The case is now considered that the information (information bits) entered from the outside via data input and output connections 23 a to 23 i is represented by (1, 0). In the error correction coding ROM 10 , only the output on the NOR gate N 3 goes to "H" level in response to the applied information bits (1, 0), while the outputs of the NOR gates N 1, N 2 and N 4 fall to the "L" level. As a result, the potential on the word line WL 3 rises and the memory transistor M 5 is switched on. Consequently, the potential on the bit line BL 2 is discharged to the "L" level, while the outputs of the other bit lines BL 1, BL 3 go to the "H" level, which are already precharged to this level. The potentials of (H , L , H) , ie, (1, 0, 1) appearing on the bit lines BL 1, BL 2 and BL 3 are output as test bits P 1 to P 3 after they have been read by the sense amplifier 9 and are reinforced. In the foregoing description, the precharge path of each bit line BL 1 to BL 3 is the same as that provided in an ordinary ROM circuit, and therefore the drawing is omitted to avoid excessive complication. The test bits P 1, P 2 and P 3 of (1, 0, 1) generated by the sense amplifier 9 are connected to the information bits D 0, D 1 and supplied to the read / write circuit 5 . The read / write circuit 5 writes the information bits and the check bits into the corresponding memory cells in the information memory cell array and the memory cell array 2 for checking, which have already been selected via the X decoder 3 and the Y decoder 4 . One cycle of the write operation is thus ended.

In the illustration for the writing activity described above, the arrangement of FIG. 6 does not show that for outputting the information bits D 0, D 1. However, it can be that for transmitting the unchanged information bits D 0, D 1, it can also continue for storing of the information bits corresponding to these information bits in the ROM section.

In this way of data writing, the decoder section is of a configuration of the NOR type decoder, which is the same as that of the X decoder 3 and Y decoder 4 provided in the memory cell array section, so that the margin of the operational supply voltage encodes this error correction masked ROMs can be as large as that corresponding to the memory cell array section. As the supply voltage is lowered, the decrease in the supply potential appears on the outputs of the NOR gates. This output is transferred to the word lines, this operation is the same as the word line selection operation in an ordinary memory cell array section. Therefore, its operating margin can be made the same as that of a memory cell array section. As a result, the operating margin for the supply voltage can be improved more than in the case of a circuit arrangement which uses conventional logic gates.

In the above description, the selection operation of the memory cells in the memory cell array 1 and the memory cell array 2 for testing has not been described. However, after the X address and the Y address are entered into the X decoder 3 and the Y decoder 4 in response to a control signal CE which is externally applied, the selection activity for the memory cell array becomes dependent on a control signal executed by the control signal generator circuit 30 . The data write command is executed in response to control signals and. That is, when the write enable signal is active at "L" while the output enable signal is inactive at "H" during data writing, data is input to the data input and output circuit 8 and then transferred to the error correction encoding masked ROM 10 . The data reading activity is now described.

After the X address and the Y address are applied to the X decoder 3 and the Y decoder 4 in response to the external control signal and are then decoded therein, the corresponding memory cells become the memory cell array 1 and the memory cell array 2 Check selected so that the information bits and check bits contained therein are read out. These read out information bits and check bits are applied to the error-decoding masked ROM 11 via the read / write circuit 5 . The error-decoding masked ROM 11 uses the applied information bits D 0, D 1 and the check bits P 1 to P 3 as address inputs for it, so that the corresponding permanently stored information is read out or kept in the ROM implementation. That is, if, for example, the information bits are (1, 0) and the check bits are (1, 0, 1), then (1, 0) is already in the masked ROM implementation at the corresponding address (1, 0, 1, 0, 1) is stored, and a word line corresponding to this address is selected, so that its content is transmitted as read information D 0, D 1 to the data input and output circuit 6 via the sense amplifier 9 . The data input and output circuit 6 outputs the given data as readout data in response to the control signals,,,. Whenever a one-bit error occurs due to any cause, that is, when the bits read out from memory cell array 1 and memory cell array 2 are checked (1, 1, 1, 0, 1) (information bit D 0 is defective), ( 0, 0, 1, 0, 1) (the information bit D 1 is faulty), (1, 0, 0, 0, 1) (the check bit P 1 is faulty), (1, 0, 1, 1, 1) (check bit P 2 is faulty) or (1, 0, 1, 0, 0) (check bit P 3 is faulty), the written information is (1, 0) in the masked ROM implementation, so that correct data reading is executed by the error decoding circuit 8 . That is, the reading of the information in which the error of the information is corrected is carried out.

Also in this data reading, the decoder section of the decoding masked ROM 11 has the same NOR type configuration as the decoder section provided corresponding to the memory cell array section, so that the operating margin for the supply voltage can be made equal to that for a memory cell array section, and thus Scope for the operating supply voltage in the semiconductor memory device can be improved.

Similarly, in the combination of the other information bits and check bits, the corresponding information is read out into the masked ROM by the decoder section so that it is read out through the data input and output circuit 6 after the error checking and correction of the information is performed.

As can be seen from Fig. 8A, the masked ROM has memory transistors M 10, M 13 for storing the information "0" which have thin gate oxide films. Furthermore, memory transistors M 11, M 12 with thick gate oxide films are provided, which are used to store information "1". The memory transistors M 10, M 11 are selected by a word line WL 10, and the information from each of the memory transistors M 10, M 11 is transferred to the bit lines BL 20 and BL 21, respectively. The memory transistors M 12, M 13 are selected by a word line WL 11, and the information in each of the memory transistors M 12, M 13 is transferred to the bit lines BL 20 and BL 21, respectively.

As shown in FIG. 8B, the memory transistors M 10 and M 13 have thin gate oxide films, while the memory transistors M 11, M 12 have thick gate oxide films. The memory transistor with a thin gate oxide film has a low threshold voltage, while that with a thick gate oxide film has a high threshold voltage. Therefore, when the same voltage is applied to the gates of the memory cells via the word lines, the memory transistor with the thin gate oxide film is made conductive, while the other memory transistor with a thick gate oxide film remains non-conductive. As a result, the information "0" and "1" can be stored.

Fig. 8C shows a cross-sectional view illustrating the cross-sectional structure along the line XX 'in Fig. 8B. The memory transistor M 12 for storing the information “1” is formed from a source diffusion layer 201 a and a drain diffusion layer 201 b on a semiconductor substrate 200 , a gate oxide film B of great thickness thereon and a gate electrode 203 . The memory transistor M 13 for storing the information "0" is made of a source diffusion layer 201 c , which is connected to a bit line, a drain diffusion layer 201 b , which is connected to a ground potential, a gate oxide film A of small thickness thereon and that Gate electrode 203 , which represents the word line, is formed. As described above, information can be easily stored depending only on the thickness of the gate oxide films.

In addition, there is another one instead of this configuration Configuration, namely information depending on whether or whether not the gate electrodes and the word lines together are connected, saved. The thickness of the remains Gate oxide films unchanged and the thickness of the word lines and the gate electrodes are kept constant.

As shown in FIG. 9, a FAMOS cell (an EPROM cell) composed of impurity regions 301 a , 301 b , which represent source and drain diffusion layers formed on a semiconductor substrate 300 , consists of a floating gate 302 , which is located on the Semiconductor substrate 300 is formed over an interlayer insulating film 304 and stores information depending on whether or not charge is stored therein and is formed from a control gate 303 formed above the floating gate 302 separately by an interlayer insulating film 305 .

Therefore, when the memory cell configuration of the memory cell array is the FAMOS cell structure as shown in Fig. 9, the ROM with the coding and decoding for error checking and correction can be formed in the same manufacturing steps as the memory cell transistors in the memory cell array, so that the manufacturing steps can be greatly simplified compared to the steps used for the conventional logic gates. That is, if the gate electrode of the thin gate oxide film section is formed in the same manufacturing steps as that for the floating gate 302 , while the gate electrode for the thick gate insulating film section is formed in the same step as that for the control gate 303 , the masked ROM can be easily made without additional Manufacturing steps are formed. In such a case, if information is stored not depending on the thickness of the gate oxide film but whether or not the gate electrodes and the word lines are connected to each other in the masked ROM, the masked ROM can be manufactured in the same manufacturing steps as the control gate 303 or the like floating gate 302 of the arrangement shown in FIG .

Even in the case that the structure of the memory cells contained in the memory cell arrays 1 , 2 is not that of the FAMOS cells, but that of ordinary DRAM cells (see Fig. 10), or in the case that the information is dependent on the In any case, thickness of the gate oxide films of the memory transistors of the ROM is stored or whether or not connections exist between the gate electrodes and the contact electrodes, the memory transistors of the masked ROM can be formed in the same manufacturing steps as the transistors in the memory cell array section. As shown in FIG. 10, the gate electrodes of the ROM memory transistors can be formed in the same manufacturing steps as the gate electrode 400 of the DRAM cell or the cell plate 401 , which is an electrode of an information storage capacitor. As a result, the ROM for error checking / correction in the masked ROM implementation can be easily formed without complicated manufacturing steps. As shown in Fig. 10, the DRAM cell is simply formed from a semiconductor substrate 405 , a diffused impurity region 406 a , which becomes the source, the other diffused impurity region 406 b , which becomes the drain, a gate insulating film 407 and a cell plate 401 .

The equivalent circuit diagrams of the FAMOS cell and the DRAM cell are shown in Figs. 9 (b) and 10 (b), respectively.

As described so far, at least according to the invention one of the error correction coding circuit section and the Error decoding circuit section in the masked ROM implementation formed in the semiconductor memory device, the Contains error checking / corrections so that the configurations of the error correction coding and decoding circuit sections may be the same as that of other sections of the semiconductor memory device; d. i.e., the memory cell array section and of the associated peripheral circuit section. Hence can the scope of the operating supply voltage for the Error correction coding circuit section and decoding circuit section be enlarged, namely like that Operating supply scope in the storage sections the information bits and the check bits and in the associated ones  peripheral switching sections. Consequently, a big one Scope for the operating supply voltage for the entire Semiconductor memory device are provided so that a such a semiconductor memory device can be provided, that can perform data reading quickly and correctly, even if the supply voltage fluctuates.

Claims (5)

1. A semiconductor memory device which has error-checking and / or correcting functions, with:

• a memory cell array with a plurality of memory elements;
• - A writing device ( 5 , 10 ) in the data write operating mode for generating test information which corresponds to the memory information supplied from the outside, connecting the generated test information with the memory information supplied from the outside to form a code word which tests and corrects errors for at least one-bit information can, and writing the code word in memory elements selected by an externally created address; and
• - An output device ( 5 , 11 ), which is activated in the data reading operating mode, for reading out the stored code word from the memory element selected by an external address and checking and correcting the error in the output code word and then outputting the memory information contained in the corrected code word as readout information ,

characterized in that at least one of the code word generator means ( 10 ) and error check / error correcting means ( 11 ) is formed using read-only memory means for storing code word information in each address corresponding to the information supplied, and the read-only memory means is the same Semiconductor chip ( 100 ) as the memory cell array ( 1 ) containing the plurality of memory elements is formed. 2. The semiconductor memory device as claimed in claim 1, characterized in that the code word generator and the error checking / correcting device both using the read-only memory device are formed. 3. The semiconductor memory device according to claim 1 or 2, characterized in that read-only storage means is a masked ROM. 4. The semiconductor memory device according to claim 3, characterized in that the masked ROM is in the same Manufacturing step how the memory cell array is made.