TWI723213B - Memory device including column redundancy - Google Patents

Abstract

A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats. A memory device according to the invention may improve repair efficiency by increasing a usable column redundancy.

Description

Including row redundancy storage device

The embodiments of the inventive concept described herein relate to a storage device, and more specifically, to a storage device with row redundancy.

Storage devices are widely used in electronic devices such as mobile devices and computers. The storage capacity of storage devices has recently increased with the development of manufacturing process technology. However, as a result of the recent progress in miniaturization process technology, the number of defective storage cells in the storage device has increased, which has caused the yield of the storage device to decrease.

In an effort to improve yield, spare memory cells are incorporated into storage devices. However, defects may occur in the backup storage unit, and the yield of the backup storage unit will also decrease, resulting in a decrease in the yield of the storage device.

An embodiment of the inventive concept provides a storage device including row redundancy.

An embodiment of the inventive concept provides a storage device including a storage cell array and a row decoder. The memory cell array includes a plurality of pads connected to a word line and a plurality of bit lines. The row decoder includes a first repair circuit in which a first repair row address is stored and a second repair circuit in which a second repair row address is stored. When the first repair row address coincides with the received row address in a read command or a write command, the row decoder is configured to divide and divide all the rows in one of the plurality of pads. Select another bit line from the multiple bit lines other than the multiple bit lines corresponding to the received row address, and when the second repair row address coincides with the received row address The row decoder is configured to select other bit lines from among the plurality of bit lines other than the bit line corresponding to the received row address among the plurality of pads.

An embodiment of the inventive concept provides a storage device including a storage cell array and a row decoder. The memory cell array includes a first plurality of pads connected to a first word line and a second plurality of pads connected to a second word line, wherein the first word line and A plurality of storage units of the second character line. The row decoder may include a first repair circuit and a second repair circuit. A first repair row address is stored in the first repair circuit, and a second repair row address is stored in the second repair circuit. When the first repair row address coincides with the received row address in a read command or a write command, the row decoder is configured to select from a plurality of bit lines in the first plurality of pads A different first bit line of the plurality of bit lines is selected from the bit lines corresponding to the received row address, and when the second repair row address is the same as the received row address When the addresses coincide, the row decoder is configured to select among the second plurality of pads from the plurality of bit lines that are different from the bit lines corresponding to the received row address The second bit line.

The embodiment of the inventive concept further provides a storage device including a plurality of storage cell arrays and a plurality of row decoders. The memory cell array includes a plurality of pads connected to one word line and a plurality of bit lines connected to the plurality of pads. The plurality of row decoders are respectively connected to the plurality of storage cell arrays, and each row decoder includes a first repair circuit storing a first repair row address and a second repair circuit storing a second repair row address therein Repair the circuit. At least two storage cell arrays among the plurality of storage cell arrays are selected based on a single activation command. When the received row address in the read command or the write command coincides with the first repair row address, connect to the selected at least two storage cell arrays from the plurality of row decoders Each of the at least two row decoders in one of the plurality of pads selects the other from the plurality of bit lines other than the bit line corresponding to the received row address Bit line. When the received row address and the second repair row address coincide with each other, each of the at least two row decoders connected to the selected at least two storage cell arrays is in the The second bit line is selected from the plurality of bit lines other than the bit line corresponding to the received row address among the plurality of pads.

Hereinafter, embodiments of the concept of the present invention are described in detail and clearly so that those of ordinary skill in the art can easily implement the concept of the present invention.

As is conventional in the conceptual field of the present invention, the embodiment may be described and illustrated by a block capable of realizing the function or multiple functions. These blocks (which can be referred to as units or modules in this article) are physically composed of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, and optical components. , Hard-wired circuits, etc., implemented by analog and/or digital circuits, and can be selectively driven by firmware and/or software. The circuit may, for example, be implemented in one or more semiconductor wafers, or implemented on a substrate supporting such as a printed circuit board. The circuits that make up a block can be implemented by dedicated hardware or processors (such as one or more programmed microprocessors and associated circuits), or a combination of dedicated hardware can perform some functions of the block and be processed by The device performs other functions of the block. Without departing from the scope of the concept of the present invention, each block of the embodiment can be physically separated into two or more interactive and discrete blocks. Similarly, the blocks of the embodiments can be combined into more complex blocks without departing from the scope of the concept of the present invention.

FIG. 1 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. 1, the storage device 1000 may include a storage cell array 1100, a row decoder 1200, and a peripheral circuit 1300. Row decoder

The memory cell array 1100 may include a first pad 1101 to a seventeenth pad 1117 (only the display pads 1101, 1108, 1109, 1116, and 1117 are shown to simplify the drawing). 1, the pads may be arranged in the memory cell array 1100 in the order of the first pad 1101 to the eighth pad 1108, the seventeenth pad 1117, and the ninth pad 1109 to the sixteenth pad 1116. The seventeenth pad 1117 may store metadata (for example, parity data) associated with normal data stored in the first pad 1101 to the sixteenth pad 1116. The arrangement of the seventeenth pad 1117 arranged between the eighth pad 1108 and the ninth pad 1109 is not limited to that illustrated in FIG. 1. For example, the seventeenth pad 1117 may be disposed at any position in the storage cell array 1100, such as the left side of the first pad 1101 or the right side of the sixteenth pad 1116. In addition, although the memory cell array 1100 is described as including seventeen pads 1101 to 1117, in other embodiments, the memory cell array 1100 may include more or less than the 17 pads described in FIG. 1.

The first pad 1101 to the seventeenth pad 1117 can be configured and implemented in the same manner as each other. For the sake of brevity of description, in FIG. 1, one bit line BL from a plurality of bit lines BL (not shown) and a plurality of spare bit lines SBL (not shown) are shown in each pad. One spare bit line SBL in) and shows one word line WL from a plurality of word lines WL (not shown). 1, the first pad 1101 to the seventeenth pad 1117 share the word line WL (and other word lines), but do not share the bit line BL and the spare bit line SBL. In other words, the bit line BL and the spare bit line SBL in one of the first pads 1101 to 1117 do not extend to the other pads of the first pad 1101 to the seventeenth pad 1117. The detailed configuration of each of the first pad 1101 to the seventeenth pad 1117 will be explained with reference to FIG. 2.

In the first pad 1101, it is possible to use the first input/output pad DQ1 (which is one of the first input/output pad DQ1 to the seventeenth input/output pad DQ17 1320 configured as the peripheral circuit 1300). Perform data registration/output associated with the storage cells connected to the word line WL and the bit line BL. Similarly, in each of the second pad 1102 to the seventeenth pad 1117, a corresponding one of the second input/output pad DQ2 to the seventeenth input/output pad DQ17 1320 of the peripheral circuit 1300 can be used The input/output pads perform data registration/output associated with the storage cells connected to the word line WL and the bit line BL. However, the relationship between the pads and the input/output pads, the number of pads, and the number of input/output pads are not limited to those described in FIG. 1, and can be implemented in different configurations.

The storage device 1000 may receive a start command before receiving a write command or a read command from the outside (for example, a storage controller or a test device of a host such as the host 7100 shown in FIG. 14). All storage units connected to the character line of the storage device 1000 can be selected based on the activation command. After that, if the storage device 1000 receives a write command or a read command, multiple bit lines can be selected. In an embodiment, the bit line BL shown in the first pad 1101 to the seventeenth pad 1117 may be selected through a write command or a read command. Data registration/output can be performed on the storage unit connected to the selected bit line BL.

As described above, the data stored in the storage units of the first pad 1101 to the sixteenth pad 1116 can be normal data, and the data used to correct errors in the normal data (ie, error correction data) can be stored in the seventeenth Pad 1117 in the storage unit. Here, the combination of the normal data and the error correction data added to the normal data may be referred to as a "code word". That is, the data registration/output corresponding to the codeword can be performed according to the write command or the read command in the storage cell array 1100.

In an embodiment, the error correction data may be parity data generated by performing error correction coding on normal data. In the case of performing error correction encoding and decoding outside the storage device 1000, the data registration/output of the seventeenth pad 1117 can be performed through the seventeenth input/output pad DQ17. In the case of performing error correction encoding and decoding in the storage device 1000 (that is, in the case where the storage device 1000 includes an on-chip error correction code (ECC) circuit), the seventeenth input/output pad may not be used DQ17 comes to input or output the data of the seventeenth pad 1117. In the case where the storage device 1000 includes an on-chip error correction code circuit, the seventeenth pad DQ17 can be removed from the storage device 1000.

The row decoder 1200 can be connected to the memory cell array 1100 via a row selection line CSL and a spare row selection line SCSL. The row decoder 1200 selects a row selection line CSL or a spare row selection line SCSL based on a write command or a read command. If the row decoder 1200 selects the row selection line CSL, the bit line BL is selected. As in the above description, if the row decoder 1200 selects the spare row selection line SCSL, the spare bit line SBL is selected. Hereinafter, the line repair according to the embodiment of the concept of the present invention will be explained.

In FIG. 1, it is assumed that there are defects in the memory cells connected to the word line WL and the bit line BL of the first pad 1101, the eighth pad 1108, and the ninth pad 1109. In addition, it is assumed that there are defects in the memory cells connected to the word line WL and the spare bit line SBL of the ninth pad 1109. Defective storage cells are indicated by "X" in Figure 1.

1, the number of defective memory cells connected to the bit line BL (3) may be greater than the number of defective memory cells connected to the spare bit line SBL (1). The number of errors that can be corrected through error correction encoding and decoding is limited. Therefore, in the following description, it is assumed that data errors stored in the storage cells connected to the word line WL and the bit line BL shown in FIG. 1 cannot be corrected by error correction coding and decoding, and are stored in the word line WL. The data error of the storage unit connected to the spare bit line SBL can be corrected by error correction coding and decoding.

As described above, the row decoder 1200 may select all the bit lines BL shown in the first pad 1101 to the seventeenth pad 1117 based on the write command or the read command. 1, the storage cells of the first pad 1101 and the eighth pad 1108 connected to the bit line BL can be replaced by storage cells connected to the spare bit line SBL, respectively. However, because the storage cell connected to the spare bit line SBL of the ninth pad 1109 is defective as indicated by "X", the storage cell of the ninth pad 1109 connected to the bit line BL shown may not be able to be connected to the ninth pad 1109. The storage cell connected to the spare bit line SBL of the pad 1109 is replaced. Therefore, in the case of a normal storage device, all the bit lines BL of the first pad 1101 to the seventeenth pad 1117 may be unusable due to the error of the spare storage unit of the ninth pad 1109. This may reduce the yield of the storage device.

However, according to the embodiment of the inventive concept, the storage cells connected to the bit lines BL of the first pad 1101 to the seventeenth pad 1117 can be replaced by the storage cells connected to the spare bit line SBL at the same time (ie, selection and spare The storage cell connected to the bit line SBL instead of the storage cell connected to the bit line BL). Thus, the defective storage cells of the ninth pad 1109 connected to the bit line BL can be replaced by defective spare storage cells, and the non-defective storage cells of the sixteenth pad 1116 and the seventeenth pad 1117 can also be replaced Substitute. Since the number of defects is reduced (reduced from 3 to 1) by the row repair according to the embodiment of the inventive concept, it is stored in the repaired (or replaced) storage unit (the storage unit connected to the spare bit line SBL) The data error of can be corrected by error correction coding and decoding. That is, if all storage cells corresponding to the codeword are replaced by spare storage cells at the same time, the spare bit line SBL of the ninth pad 1109 can be used. Since the data in the defective storage unit can be corrected and used by error correction encoding and decoding, the yield rate of the storage device 1000 according to the embodiment of the concept of the present invention can be improved.

The peripheral circuit 1300 may include a command and address (CMD/ADD) pad 1310, a first input/output pad DQ1 to a seventeenth input/output pad DQ17 1320, and an error correction circuit 1330 (or error Correction code (error correction code, ECC) circuit). As described above, in the case of performing error correction encoding and decoding inside the storage device 1000, the peripheral circuit 1300 may only include the first input/output pad DQ1 to the sixteenth input/output pad DQ16.

The peripheral circuit 1300 may provide a row address (not shown) to the row decoder 1200 according to a command (for example, a read command or a write command) received from outside the storage device 1000 (for example, a storage controller of the host). The peripheral circuit 1300 may provide input data (ie, input/output data) to the row decoder 1200 in response to a write command, or may receive output data (ie, input/output data) from the row decoder 1200 in response to a read command. data). The input data can be input to the peripheral circuit 1300 via the first input/output pad DQ1 to the seventeenth input/output pad DQ17. The output data can be output to the outside of the storage device 1000 (for example, the storage controller of the host) via the first input/output pad DQ1 to the seventeenth input/output pad DQ17.

The error correction circuit 1330 can generate parity data by performing error correction coding on the input data (ie, normal data). The input data and the parity data can be stored in the first pad 1101 to the seventeenth pad 1117 together. After that, the error correction circuit 1330 can correct data errors by performing error correction decoding on the data read from the first pad 1101 to the seventeenth pad 1117. The error-corrected data can be output to the outside via the first input/output pad DQ1 to the seventeenth input/output pad DQ17.

The error correction circuit 1330 may use, for example, the following coded modulation (coded modulation) to correct errors: low density parity check (LDPC) codes, Bose, Chaudhuri, Hocque-nghem (BCH) code, turbo code (turbo code), Reed-Solomon code (Reed-Solomon code), convolution code (recursive systematic code, RSC), trellis code modulation Change (trellis-coded modulation, TCM), or block coded modulation (block coded modulation, BCM), or other suitable coding modulation schemes.

In other embodiments of the inventive concept, the peripheral circuit 1300 may not include the error correction circuit 1330. In this case, error correction encoding and decoding can be performed outside the storage device 1000 (for example, in the storage controller of the host).

FIG. 2 illustrates a block diagram of the first pad shown in FIG. 1 in detail. In particular, FIG. 2 illustrates a block diagram of the first pad 1101. In an embodiment of the inventive concept, each of the second pad 1102 to the seventeenth pad 1117 can be implemented and configured in the same manner as the first pad 1101 shown in FIG. 2. 2, the first pad 1101 includes a normal storage cell area and a spare storage cell area. The normal storage cell area includes a storage cell (memory cell, MC). For example, each storage unit may be a dynamic random access memory (DRAM) unit, a static random access memory (SRAM) unit, etc. Alternatively, each storage unit may be a non-volatile storage unit. For example, each storage unit can be a NOR flash memory cell, a NAND flash memory cell, or a ferroelectric random access memory (NOR flash memory cell). random access memory (FeRAM) unit, phase change random access memory (PRAM) unit, thyristor random access memory (TRAM) unit, resistive random access memory ( resistive random access memory, ReRAM) unit, magnetic random access memory (magnetic random access memory, MRAM) unit, etc.

The spare memory cell area includes a spare memory cell (SMC). The backup storage unit and the storage unit can be implemented to have the same configuration. When a defect occurs in a storage unit, a spare storage unit can be used (or used) to repair the defective storage unit (the spare storage unit can be used to replace the defective storage unit). For example, as shown in FIG. 1, the first pad 1101 of the defective memory cell connected to the bit line BL is replaced with the spare memory cell SBL connected to the spare bit line, and therefore the first pad 1101 indicates "repair" ". In other embodiments of the inventive concept, the spare storage unit area may be arranged on the right side of the normal storage unit area, or in addition to being arranged on the left side of the normal storage unit area, but also on the right side of the normal storage unit area.

Errors in the data stored in the storage unit can be roughly divided into hard errors or soft errors. A hard error may occur, for example, when the storage unit is physically damaged, or in other words, the hardware of the storage unit is damaged. A soft error may mean that the hardware of the storage unit is not damaged, but the data of the storage unit temporarily transitions due to, for example, alpha particles or other reasons that are not related to the hardware of the storage unit itself. Hard errors can be corrected by spare storage units (or replaced by spare storage units) or by error correction encoding and decoding. Soft errors can be corrected by error correction encoding and decoding.

2, the normal memory cell region including the memory cell MC (ie, the first plurality of memory cells) may be associated with a plurality of word lines WL1, WL2 to WLm and a plurality of bit lines BL1, BL2 to BLn (ie, the first plurality of memory cells). Two or more storage units) to connect. The spare storage cell area including the spare storage cell SMC (ie, the second plurality of storage cells) can be connected to the plurality of word lines WL1, WL2 to WLm and the plurality of spare bit lines SBL1, SBL2 to SBLy (ie, the second most One bit line) to connect. Hereinafter, the plurality of spare bit lines SBL is referred to as "column redundancy". Here, each of “m” and “n” may be a positive integer and in other considerations may be determined by the characteristics of the storage device (for example, the capacitance and area of the bit line), and/or specifications. For example, "m" can be 384, 512, 640, 767, 832, 1024 or other suitable positive integers. "N" can be 512, 1024, 2048 or other suitable positive integers. However, the embodiments of the inventive concept are not limited by the above-mentioned numerical values. Also in FIG. 2, "y" represents the number of spare bit lines, that is, the yield of the storage device can be increased as "y" increases. However, the area of the storage device will increase while the yield is improved. In the following, the repair operation will be explained.

For example, referring to FIG. 2 further, it is assumed that among the memory cells connected to the first bit line BL1, there are defects in the memory cells marked by "X". The data in the storage unit indicated by "X" may be in an error state. When an external (for example, a host or a processor) requests access to the first bit line BL1 from the storage device, the first spare bit line SBL1 may be selected instead of the first bit line BL1. That is to say, to the external device (for example, the host or processor), it may appear that the first bit line BL1 is selected, but in the storage device, the first spare bit line SBL1 may be actually selected instead of the first bit line SBL1. The first bit line BL1. Of course, the first bit line BL1 may not be selected, but any one of the spare bit lines SBL2 to SBLy may be selected.

Although not shown in FIG. 2, the first pad 1101 may further include a spare word line and a spare storage unit connected to the spare word line. For example, the spare word line may be set after the m-th word line WLm or may be set before the first word line WL1. The spare word line or spare bit line can be used according to the defect position of the storage cell.

FIG. 3 is a block diagram illustrating the relationship between the row selection line and the bit line shown in FIG. 1 in detail. 3, the storage device 2000 includes a storage cell array 2100 and a row decoder 2200. The storage cell array 2100 may include a first pad 2101 to a seventeenth pad 2117 (in order to simplify the drawing, only the first pad 2101, the eighth pad 2108, the ninth pad 2109, the sixteenth pad 2116, and the seventeenth pad are shown. 2117). Also for simplicity of description, only the first pad 2101 is shown in detail in FIG. 3. Each of the second pad 2102 to the seventeenth pad 2117 can be arranged and/or implemented in the same manner as the first pad 2101. In addition, in order to simplify the description, only one word line WL is shown in FIG. 3, and the peripheral circuit 1300 shown in FIG. 1 is not shown.

The row decoder 2200 may select the row selection line CSL of each of the first pad 2101 to the seventeenth pad 2117 based on a write command or a read command received from the outside. Each row selection line CSL can be connected to a plurality of bit lines BL via a switch 2120. The switch 2120 can be implemented using the following transistors: N-channel metal oxide semiconductor (NMOS) transistor, P-channel metal oxide semiconductor (PMOS) transistor, or NMOS and Both PMOS transistors. Although the "8" bit lines BL shown in FIG. 3 are connected to the row selection line CSL via the switch 2120, in other embodiments of the inventive concept, it may be any number of bit lines greater than or less than 8. BL is connected to the row selection line CSL via the switch 2120.

As described above, the data registration/output associated with the first pad 2101 can be performed on the first pad 2101 via the first input/output pad DQ1. In an embodiment, 8-bit data can be input and output through the first input/output pad DQ1 through a write command or a read command. The number of data bits that are input/output via the input/output pad according to the write command or the read command is called "burst length bl". However, the burst length is not limited to the above number.

The row decoder 2200 may independently select the spare row selection line SCSL of each of the first pad 2101 to the seventeenth pad 2117 based on a write command or a read command received from the outside. The spare row selection line SCSL can be connected to a plurality of spare bit lines SBL via the switch 2120. The row decoder 2200 may select the spare row selection line SCSL instead of the row selection line CSL connected to the defective memory cell. That is, the row repair may mean an operation in which the row decoder 2200 selects the spare row selection line SCSL instead of the row selection line CSL.

FIG. 4 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. FIG. 5 illustrates a block diagram of the storage device shown in FIG. 4. FIG. 4 and 5, the storage device 3000 includes a storage cell array 3100 and a row decoder 3200. The storage cell array 3100 may include a first pad 3101 to a seventeenth pad 3117 (to simplify the drawing, only the first pad 3101, the eighth pad 3108, the ninth pad 3109, the sixteenth pad 3116, and the seventeenth pad are shown. 3117). The first pad 3101 to the seventeenth pad 3117 may perform the same functions as described with reference to FIGS. 1 to 3.

The row decoder 3200 includes a first repair circuit 3201 to 3217, a second repair circuit 3230, and a first sub-row decoder 3241 to a seventeenth sub-row decoder 3257 (to simplify the drawing, only the first sub-row decoder is shown) The eighth sub-row decoder 3248, the ninth sub-row decoder 3249, the sixteenth sub-row decoder 3256, and the seventeenth sub-row decoder 3257). The first repair circuits 3201 to 3217 are respectively connected with the first sub-row decoder 3241 to the seventeenth sub-row decoder 3257. The second repair circuit 3230 is connected to all the sub-row decoders from the first sub-row decoder 3241 to the seventeenth sub-row decoder 3257. The first sub-row decoder 3241 to the seventeenth sub-row decoder 3257 are connected to the first pad 3101 to the seventeenth pad 3117, respectively.

The first repair circuit 3201 may receive the row address CA from the peripheral circuit 1300 (refer to FIG. 1). The row address necessary for repair (hereinafter referred to as “repair row address RCA”) may be stored in the first repair circuit 3201 in advance. That is, the first repair circuit 3201 can be characterized as the first repair row address. The first repair circuit 3201 can check whether the received row address CA coincides with any one of the repaired row addresses RCA. If the received row address CA overlaps with any one of the repaired row addresses RCA, the first repair circuit 3201 can provide the first repair enable signal CREN1 to the first sub-row decoder 3241. If the first repair enable signal CREN1 is activated, the first sub-row decoder 3241 may select the spare row selection line SCSL instead of the row selection line CSL.

Each of the remaining first repair circuits 3202 to 3217 can be configured and/or implemented in the same manner as the first repair circuit 3201. Depending on the defective bit line of each of the first pad 3101 to the seventeenth pad 3117, the repair row address RCA stored in each of the first repair circuits 3201 to 3217 can pass the chip test, Predetermined by packaging and testing etc. Therefore, the repair row address RCA stored in each of the first repair circuits 3201 to 3217 may be the same or different from each other. Since the first repair circuits 3201 to 3217 are provided corresponding to different pads among the first pad 3101 to the seventeenth pad 3117, the row decoder 3200 can be independent of each of the first pad 3101 to the seventeenth pad 3117 Perform line repairs locally. That is, the row decoder 3200 may, for example, perform row repair on the first pad 3101, and independently perform row repair on the other of the second pad 3102 to the seventeenth pad 3117.

The second repair circuit 3230 can be implemented in the same manner as the first repair circuit 3201. That is, the second repair circuit 3230 can compare the received row address CA with the pre-stored repair row address RCA, and can generate the second repair enable signal CREN2. The second repair circuit 3230 may be characterized as storing the second repair row address. Different from the first repair circuit 3201, the second repair circuit 3230 can provide the second repair enable signal CREN2 to all the first sub-row decoders 3241 to the seventeenth sub-row decoder 3257. If the second repair enable signal CREN2 is activated, each of the first sub-row decoder 3241 to the seventeenth sub-row decoder 3257 may select the spare row selection line SCSL instead of the row selection line CSL.

Each of the plurality of sub-row decoders 3241 to 3257 may be set in the same manner as each other. Each of the plurality of sub-row decoders 3241 to 3257 may refer to the row address CA to select the row select line CSL or may refer to the first repair enable signal CREN1 and the second repair enable signal CREN2 to select a spare row select line SCSL. The detailed structure of the plurality of sub-row decoders 3241 to 3257 will be explained with reference to FIG. 7.

In an embodiment of the concept of the present invention, when the received row address coincides with the repaired row address stored in one of the first repair circuits 3201 to 3217, the row decoder 3200 can be One of the first pad 3101 to the seventeenth pad 3117 selects a bit line other than the bit line corresponding to the received row address. When the received row address coincides with the repaired row address stored in the second repair circuit 3230, the row decoder 3200 may select to divide the received row address from the first pad 3101 to the seventeenth pad 3117. Bit lines other than the bit line corresponding to the row address.

In FIGS. 4 and 5, as represented by "X", it is assumed that the first pad 3101, the eighth pad 3108, and the ninth pad 3109 are stored at the intersection of the word line WL and the row selection line CSL. There is a defect in the unit. In addition, it is assumed that there is a defect in the memory cell of the ninth pad 3109 disposed at the intersection of the word line WL and the spare row selection line SCSL (refer to FIG. 5).

The storage device 3000 may receive the start command before receiving the write command or the read command. The storage device 3000 may activate the illustrated word line WL based on the activation command. After that, the row decoder 3200 may select the shown row selection line CSL (shown by the solid line) based on the write command or the read command.

The storage cells selected by the word line WL and the row selection line CSL of the first pad 3101 to the seventeenth pad 3117 may be referred to as the “first plurality of target storage cells”. The first plurality of target storage units can be connected with the first plurality of target bit lines. The data corresponding to the codeword can be stored in the first plurality of target storage units or the data corresponding to the codeword can be read from the first plurality of target storage units. For example, the total number of the first plurality of target storage units may be 136 (17 (DQ) multiplied by 8 (bl)=136), and the code length may be 136 bits. Here, the code length may mean the size (ie, the size of the codeword) corresponding to the sum of the error correction coding results (parity data) of the normal data and the normal data.

As shown in FIG. 4, the storage units belonging to the first pad 3101, the eighth pad 3108, and the ninth pad 3109 among the first plurality of target storage units may have defects. Due to the aforementioned defects, the data errors stored in the first plurality of target storage units may exceed the correctable range. This may mean that the error is uncorrectable. Specifically, referring to FIG. 5, since there is a defect in the memory cell of the ninth pad 3109 disposed at the intersection of the word line WL and the spare row selection line SCSL, the first repair circuit 3209 and the ninth pad 3109 have defects. The fuse set corresponding to the spare row selection line SCSL (which will be explained in FIG. 6) may be unavailable.

According to an embodiment of the inventive concept, the row decoder 3200 may use the second repair circuit 3230 to repair (ie, replace with spare storage units) all the first plurality of target storage units. The row address corresponding to the row selection line CSL (ie, the repair row address) may be stored in the second repair circuit 3230 in advance. The row decoder 3200 can repair non-defective target storage units (for example, the target storage units of the sixteenth pad 3116 and the seventeenth pad 3117) and defective target storage units.

5, by using the second repair circuit 3230 to perform the repair operation of the row decoder 3200, the spare row selection lines SCSL (shown by solid lines) of the first pad 3101 to the seventeenth pad 3117 can be selected instead of the row selection line CSL (shown by the dashed line). Here, the second plurality of target storage cells may be storage cells connected to the word line WL and the spare row selection line SCSL (ie, the second plurality of target bit lines). The second plurality of target storage units may be connected with the second plurality of target bit lines. The second plurality of target bit lines may be connected with a spare row selection line SCSL (shown by a solid line) selected by the row decoder 3200.

5, there may be a defect in the spare storage unit belonging to the ninth pad 3109 among the second plurality of target storage units. Nevertheless, the number of defective storage cells in the second plurality of target storage cells may be less than the number of defective storage cells in the first plurality of target storage cells. That is, the number of errors in the data stored in the second plurality of target storage units may be smaller than the number of errors in the data stored in the first plurality of target storage units. Therefore, even if there is a defect in the spare storage unit of the ninth pad 3109, the data error stored in the second plurality of target storage units can be corrected through error correction encoding and decoding. This is shown in FIG. 1, for example, where the defective storage unit connected to the bit line BL in the ninth pad 1109 is replaced by a spare storage unit, and the data in the defective storage unit can be encoded and decoded by error correction. Amendment, so on the ninth pad 1109 it means "repair and correction"

The row decoder 3200 may use the first repair circuits 3201 to 3217 to perform row repair on each of the first pad 3101 to the seventeenth pad 3117, respectively. The row decoder 3200 may use the second repair circuit 3230 to perform row repair on all the first pad 3101 to the seventeenth pad 3117. The number of target storage units corresponding to the total size of the normal data and the co-located data can be simultaneously repaired by the second repair circuit 3230. Even if there may be defects in the target storage unit repaired by the row repair of the second repair circuit 3230, errors caused by the above-mentioned defects can also be corrected through error correction encoding and decoding. That is to say, defective spare memory cells (the memory cells arranged at the intersection of the word line WL and the spare row selection line SCSL shown in FIG. 5) can be made usable by the row repair according to the embodiment of the concept of the present invention. . According to the embodiment of the present invention, the yield of the storage device 3000 can be improved.

FIG. 6 illustrates a block diagram of the repair circuit shown in FIG. 4 and FIG. 5. In particular, FIG. 6 illustrates a block diagram of the first repair circuit 3201 shown in FIGS. 4 and 5. However, as previously described, the remaining first repair circuits 3202 to 3217 and the second repair circuit 3230 can be implemented and/or arranged in the same manner as the first repair circuit 3201. The first repair circuit 3201 shown in FIG. 6 includes a plurality of fuse sets 3201_1, 3201-2, and 3201_3 and a comparison circuit 3201_4.

The repair row addresses RCA1, RCA2, and RCA3 can be stored in the fuse sets 3201_1 to 3201_3, respectively. Each of the fuse sets 3201_1 to 3201_3 may include a plurality of fuses. The fuse can be selectively cut by referring to a corresponding one of the repair row addresses RCA1 to RCA3. For example, the fuses can be implemented using various non-volatile memories such as: electrically programmable fuses, laser programmable fuses, anti-fuse, and flash memory. The fuse sets 3201_1 to 3201_3 can provide repair row addresses RCA1 to RCA3 to the comparison circuit 3201_4, respectively.

The comparison circuit 3201_4 can compare the row address CA (the same as the row address CA shown in FIGS. 4 and 5) with the repaired row addresses RCA1 to RCA3. In an embodiment, the comparison circuit 3201_4 may utilize various logic circuits (for example, AND, NAND, OR, NOR, INV, exclusive OR (XOR) , And anti-mutual exclusion OR (XNOR) logic circuit) or switch to implement. If the row address CA coincides with one of the repair row addresses RCA1 to RCA3, the comparison circuit 3201_4 can activate the first repair enable signal CREN1. As described above, the first repair enable signal CREN1 of the first repair circuit 3201 can be provided to the first sub-row decoder 3241 shown in FIGS. 4 and 5.

The fuse sets 3201_1 to 3201_3 may respectively correspond to the spare row selection lines. For example, if the row address CA coincides with the repair row address RCA1 stored in the fuse set 3201_1, the spare row selection line corresponding to the fuse set 3201_1 can be selected instead of the row selection corresponding to the row address CA line. Therefore, in the case where there is a defect in the storage cell connected to the spare row selection line corresponding to the fuse group, the fuse group may be unusable.

In FIG. 6, the number of fuse sets 3201_1 to 3201_3 is "3". However, the number of fuse sets 3201_1 to 3201_3 is not limited to "3". For example, in other embodiments of the inventive concept, the number of fuse sets can be determined in consideration of the target yield of the storage device or the area of the storage device. The yield of the storage device can be increased as the number of fuse sets and the number of spare row selection lines increase, but the area of the storage device will increase.

FIG. 7 illustrates a block diagram of the sub-row decoder shown in FIG. 4 and FIG. 5. In particular, FIG. 7 shows a block diagram of the first sub-row decoder 3241 shown in FIGS. 4 and 5, but the second sub-row decoder 3242 to the seventeenth sub-row decoder 3257 can be combined with the first sub-row decoder 3257. 3241 is set up and/or implemented in the same way. The first sub-row decoder 3241 shown in FIG. 7 includes a row select line (CSL) decoder (ie, a first row select line decoder) 3241_1 and a spare row select line (SCSL) decoder (ie, a second row select Line decoder) 3241_2.

The row selection line decoder 3241_1 can refer to the row address CA (same as the row address CA shown in FIG. 4 and FIG. 5) to select any one of the row selection lines CSL. However, if any one of the first repair enable signal CREN1 and the second repair enable signal CREN2 is activated, the row selection line decoder 3241_1 may not select the row selection line CSL. To this end, the row select line decoder 3241_1 may first receive the first repair enable signal CREN1 and the second repair enable signal CREN2 before selecting any one of the row select lines CSL. The row selection line decoder 3241_1 can refer to the row control signal C_CTL to control the timing of the above operations. The row control signal C_CTL can be generated by the peripheral circuit 1300 (refer to FIG. 1). That is, the peripheral circuit 1300 can generate the row control signal C_CTL with reference to the read command or the write command.

The spare row select line decoder 3241_2 can select any one of the spare row select lines SCSL in response to the row control signal C_CTL and the first repair enable signal CREN1 and the second repair enable signal CREN2. The first repair enable signal CREN1 and the second repair enable signal CREN2 may store information about whether the row address CA is the same as that included in any one of the plurality of fuse sets 3201_1 to 3201_3 (refer to FIG. 6). Information that the repair row address (any one of the repair row addresses RCA1 to RCA3 shown in Figure 6) overlaps. The spare row selection line decoder 3241_2 can select the spare row selection line SCSL corresponding to the fuse group storing the same repair row address as the row address CA.

FIG. 8 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. Referring to FIG. 8, the storage device 4000 includes a storage cell array 4100, a row decoder 4200, and a column decoder 4300.

The storage cell array 4100 may include the first pad 4101 to the seventeenth pad 4117 arranged in the first row (to simplify the drawing, only the first pad 4101, the eighth pad 4108, the ninth pad 4109, and the sixteenth pad are shown. 4116 and 17th pad 4117). The additional rows of the first pad 4101 to the seventeenth pad 4117 are included in the memory cell array 4100 (to simplify the drawing, the pads of the additional row are not indicated by reference numerals). Each of the first pad 4101 to the seventeenth pad 4117 and the pads of the additional column may be the same as the first pad 1101 shown in FIG. 2. Each of the first pad 4101 to the seventeenth pad 4117 and the pads of the additional column include a shaded area and a non-shaded area. The shaded area represents the spare storage unit area as shown in FIG. 2. The non-shaded area represents the normal storage unit area as shown in FIG. 2.

The row decoder 4200 can select a row selection line CSL or a spare row selection line SCSL. The column decoder 4300 can select one of a plurality of word lines WL.

Referring to FIG. 8, the data stored in the first pad 4101 can be output to the first input/output pad DQ1 (refer to FIG. 1). In addition, data stored in any other pads that are provided in the same row as the first pad 4101 and share the row selection line CSL and the spare row selection line SCSL with the first pad 4101 can also be output to the first input/output pad DQ1 (refer to Figure 1). Similarly, the data stored in the rest of the pads except the above-mentioned pads can also be output in the same way.

Referring to FIG. 8, a plurality of segments SEG_1, SEG_2 to SEG_x are shown. Here, the segment means the unit of line repair, and "x" is a positive integer. In an embodiment, in the case where "x" is "1", in the first pad 4101 and all other pads arranged in the same row as the first pad 4101, the row decoder 4200 may select the spare row selection line SCSL Instead of the row selection line CSL.

In another embodiment, as shown in FIG. 8, if "x" is the same as the number of pads arranged in the row direction, the row decoder 4200 may independently select a spare row selection line in each pad arranged in the same row. SCSL is not the row select line CSL.

That is, "x" (the number of segments) can be determined based on the yield and area of the storage device. As "x" becomes larger and larger, row repair operations can be more and more subdivided. As "x" becomes larger and larger, the yield of the storage device can be improved; however, the area of the storage device will increase. Hereinafter, the segment-based line repair according to an embodiment of the inventive concept will be explained.

FIG. 9 illustrates a block diagram of the row decoder shown in FIG. 8. 9, the row decoder 4200 includes first repair circuits 4201 to 4217 (to simplify the drawing, only the first repair circuit 4201, the eighth repair circuit 4208, the ninth repair circuit 4209, the sixteenth repair circuit 4216 and The seventeenth repair circuit 4217), the second repair circuit 4230, the first sub-row decoder 4241 to the seventeenth sub-row decoder 4257 (to simplify the drawing, only the first sub-row decoder 4241 and the eighth sub-row decoder are shown) The row decoder 4248, the ninth sub row decoder 4249, the sixteenth sub row decoder 4256 and the seventeenth sub row decoder 4257), and the section decoder 4260. Different from the row decoder 3200 shown in FIGS. 4 and 5, the row decoder 4200 further includes a segment decoder 4260. The functions of the first repair circuits 4201 to 4217, the second repair circuit 4230, and the first sub-row decoders 4241 to the seventeenth sub-row decoder 4257 are the same as those of the first repair circuits 3201 to 3201 described with reference to FIGS. 4 and 5, respectively. 3217, the second repair circuit 3230, and the first sub-row decoder 3241 to the seventeenth sub-row decoder 3257 are the same.

The segment decoder 4260 can receive the column address RA. The column address RA can be provided by the peripheral circuit 1300 (refer to FIG. 1). The segment decoder 4260 can decode the column address RA and can generate the segment signal SEG<1:x> with reference to the column address RA in response to the decoding. The generated segment signal SEG<1:x> can be provided to the first repair circuits 4201 to 4217 and the second repair circuit 4230. The segment signal may be characterized as segment information, and the segment information includes information of the row address corresponding to the character line associated with the row address RA.

The segment decoder 4260 can refer to the column address RA to determine the activated word line and can determine the segment where the activated word line is located. In detail, if any one of the word lines WL connected to the first pad 4104 to the seventeenth pad 4117 is activated, since the activated character line is included in the segment SEG_1, the segment decoder 4260 can be activated The segment signal SEG<1:x> and the remaining segment signals SEG<2:x> can be activated. The first repair circuits 4201 to 4217 and the second repair circuit 4230 can perform row repair on the segment where the activated word line is located in response to the segment signal SEG<1:x>. Hereinafter, the repair circuit for receiving the segment signal SEG<1:x> will be explained.

FIG. 10 illustrates a block diagram of the repair circuit shown in FIG. 9. In particular, FIG. 10 illustrates a block diagram of the first repair circuit 4201 shown in FIG. 9. However, as previously described, the remaining first repair circuits 4202 to 4217 and the second repair circuit 4230 in FIG. 9 can be configured and/or implemented in the same manner as the first repair circuit 4201. The first repair circuit 4201 shown in FIG. 10 includes a plurality of fuse group arrays 4201_1, 4201_2, and 4201_3 and a comparison circuit 4201_4.

Each of the plurality of fuse set arrays 4201_1 to 4201_3 may include a plurality of fuse sets Fuseset<1:x>. The number of fuse sets Fuseset<1:x> may be the same as the number of the above-mentioned segments SEG_1 to SEG_x. That is, when performing row repair while subdividing according to segments, the number of fuse sets Fuseset<1:x> of repair circuit 4201 can be increased.

The repair row addresses RCA1<1:x>, RCA2<1:x>, and RCA3<1:x> stored in the fuse set Fuseset<1:x> may be the same or different from each other. The repaired row addresses RCA1<1:x>, RCA2<1:x>, and RCA3<1:x> can be based on the row address corresponding to the defective storage cell of the pad included in the corresponding segment, pass the chip test or Package testing to determine in advance. Any one of the fuse set Fuseset<1:x> can be activated according to the segment signal SEG<1:x>. The repair row address may be provided from the activated fuse set of each of the plurality of fuse set arrays 4201_1 to 4201_3 to the comparison circuit 4201_4.

The comparison circuit 4201_4 can perform the same function as the comparison circuit 3201_4 shown in FIG. 6. However, compared with the comparison circuit 3201_4 shown in FIG. 6, the comparison circuit 4201_4 can be provided from the plurality of first fuse set arrays 4201_1 to 4201_3 more than the repair row addresses RCA1, RCA2, and RCA3 shown in FIG. Repair row addresses RCA1<1:x>, RCA2<1:x>, and RCA3<1:x>. The comparison circuit 4201_4 can compare the row address CA (the same as the row address CA shown in FIG. 8) with the repair row address RCA1<1:x>, RCA2<1:x>, and RCA3<1:x>. If the row address CA coincides with any one of the repair row addresses RCA1<1:x>, RCA2<1:x>, and RCA3<1:x>, the comparison circuit 4201_4 can activate the first repair enable signal CREN1. The sub-row decoders 4241 to 4257 (refer to FIG. 9) may use the first repair enable signal CREN1 to perform segment-based row repair.

FIG. 11 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. 11, the storage device 5000 includes a storage cell array 5100, a row decoder 5200, and a column decoder 5300. FIG. 11 will be explained with reference to FIG. 1 and FIG. 8.

The storage cell array 5100 may include a first pad 5101 to an eighteenth pad 5118 (to simplify the drawing, only the first pad 5101, the second pad 5102, the ninth pad 5109, the tenth pad 5110, and the eleventh pad 5111 are shown. And the eighteenth pad 5118). Different from the first pad 1101 to the seventeenth pad 1117 shown in FIG. 1, the first pad 5101 to the eighteenth pad 5118 may not be connected to each other via a character line. Referring to FIG. 11, the first to ninth pads 5101 to 5109 (ie, the first plurality of pads) may be connected with the first word line WL1. The eighth pad 5110 to the eighteenth pad 5118 (ie, the second plurality of pads) may be connected with the second word line WL2. In FIG. 11, the first word line WL1 and the second word line WL2 may be arranged on the left side with respect to the column decoder 5300. However, in other embodiments, the first word line WL1 may be disposed on the left side of the column decoder 5300, and the second word line WL2 may be disposed on the right side of the column decoder 5300. In addition, for the sake of brevity of description, the first pad 5101 to the ninth pad 5109 and the tenth pad 5110 to the eighteenth pad 5118 are shown close to each other. However, in other embodiments of the inventive concept, the first pad 5101 to the ninth pad 5109 and the tenth pad 5110 to the eighteenth pad 5118 may be provided separately without sharing a sense amplifier (not shown in the figure), for example.

As in the aforementioned storage device, normal data can be stored in the first pad 5101 to the eighth pad 5108, and the parity data of this normal data can be stored in all or part of the ninth pad 5109. Similarly, normal data can be stored in the tenth pad 5110 to the seventeenth pad 5117, and the parity data of this normal data can be stored in all or part of the eighteenth pad 5118.

The storage device 5000 may receive a start command from the outside. Different from the storage device 1000 shown in FIG. 1, in the storage cell array 5100, the first word line WL1 and the second word line WL2 can be activated. That is, the storage device 5000 can activate (ie, select) at least two character lines of the storage cell array 5100 in response to a single activation command.

After the first word line WL1 and the second word line WL2 are activated according to the activation command, the storage device 5000 can receive a read command or a write command from the outside. Some storage cells (ie, target storage cells) connected to the first word line WL1 and the second word line WL2 activated by the read command or the write command can be selected. The data corresponding to the codeword can be stored in the selected target storage unit.

The row decoder 5200 may include first repair circuits 5201 to 5209 (to simplify the drawing, only the first repair circuit 5201, the second repair circuit 5202, and the ninth repair circuit 5209 are shown), a second repair circuit 5210, and a third repair circuit. The circuit 5220, and the first sub-row decoder 5241 to the ninth sub-row decoder 5249 (to simplify the drawing, only the first sub-row decoder 5241, the second sub-row decoder 5242, and the ninth sub-row decoder are shown 5249). Each of the first repair circuits 5201 to 5209, the second repair circuit 5210, and the third repair circuit 5220 can be configured and/or implemented in the same manner as the repair circuit 3201 shown in FIG. 6 or the repair circuit 4201 shown in FIG. 10 .

The repair row address corresponding to the defective bit line of the first pad 5101 may be stored in the first repair circuit 5201. The repair row addresses of the first pad 5101 to the ninth pad 5109 may be previously stored in the first repair circuits 5201 to 5209, respectively. In addition, the repair row addresses of the tenth pad 5110 to the eighteenth pad 5118 may be previously stored in the first repair circuits 5201 to 5209, respectively. The first repair circuits 5201 to 5209 may be connected to the first sub-row decoder 5241 to the ninth sub-row decoder 5249, respectively. That is, the row decoder 5200 may independently perform row repair on each pad by using the first repair circuits 5201 to 5209, respectively. Each of the first repair circuits 5201 to 5209 can be characterized as a third repair circuit.

The second repair circuit 5210 and the third repair circuit 5220 can be connected to the first sub-row decoder 5241 to the ninth sub-row decoder 5249. In detail, the second repair circuit 5210 can provide the second repair enable signal CREN2 to the first sub-row decoder 5241 to the ninth sub-row decoder 5249. The second repair circuit 5210 may be characterized as a second repair circuit. As in the second repair circuit 5210, the third repair circuit 5220 can provide the third repair enable signal CREN3 to the first sub-row decoder 5241 to the ninth sub-row decoder 5249. The third repair circuit 5220 may be characterized as a second repair circuit.

The second repair circuit 5210 may correspond to the segment in which the first word line WL1 is to be activated, and the third repair circuit 5220 may correspond to the segment in which the second word line WL2 is to be activated. That is, if the row address CA coincides with the repaired row address stored in the second repair circuit 5210, the row decoder 5200 can select the first word line from all the first pad 5101 to the ninth pad 5109. The storage cell connected to WL1 and the spare bit line SBL is not the storage cell connected to the first word line WL1 and the bit line BL. As in the above description, if the row address CA coincides with the repaired row address stored in the third repair circuit 5220, the row decoder 5200 can select the same from the tenth pad 5110 to the eighteenth pad 5118. The storage cell connected to the two word line WL2 and the spare bit line SBL is not the storage cell connected to the second word line WL2 and the bit line BL.

That is, the row decoder 5200 can independently execute the row of the row decoder 3200 shown in FIGS. 4 and 5 on the storage cells connected to the first word line WL1 and on the storage cells connected to the second word line WL2. Repair operation.

Referring to FIG. 11, it is assumed that there are defects (indicated by “X”) in the storage cells of the first pad 5101 and the second pad 5102, and it is assumed that there are defects in the spare storage cells of the second pad 5102. The number of defects (2) of the memory cells connected to the first word line WL1 and the bit line BL may be greater than the number of defects (1) of the memory cells connected to the first word line WL1 and the spare bit line SBL. In addition, it is assumed that there are no defects in the storage cells of the tenth pad 5110 to the eighteenth pad 5118. The storage cell connected to the first word line WL1 and the bit line BL and the storage cell connected to the second word line WL2 and the bit line BL may be referred to as “target storage cells”.

Due to the above-mentioned defects, the data error stored in the target storage unit may exceed the correctable range. This may mean that the error is uncorrectable. Specifically, since there are defects in the storage cells of the second pad 5102 connected to the first word line WL1 and the spare bit line SBL, the spare bit line SBL of the first repair circuit 5202 and the second pad 5102 is The corresponding fuse group may be unavailable.

The row decoder 5200 can use the second repair circuit 5210 to repair all the storage cells connected to the first word line WL1 in the target storage cell. In contrast, since there is no defect in the storage cell connected to the second word line WL2 in the target storage cell, the row decoder 5200 does not perform row repair on the storage cell connected to the second word line WL2.

Referring to FIG. 11, there may be a defect in the spare storage unit belonging to the second pad 5102 in the newly selected target storage unit. Nevertheless, the number of defects (1) of the newly selected target storage unit may be less than the number of defects (2) of the previous target storage unit. In other words, the number of data errors stored in the newly selected target storage unit may be less than the number of data errors stored in the previous target storage unit. Therefore, the data error caused by the defective spare storage unit of the second pad 5102 can be corrected by error correction encoding and decoding.

The first sub-row decoder 5241 to the ninth sub-row decoder 5249 may be connected to the first pad 5101 to the eighteenth pad 5118. In detail, the first sub-row decoder 5241 can be connected to the first pad 5101 and the tenth pad 5110. The second sub-row decoder 5242 to the ninth sub-row decoder 5249 may be connected to the two pads in the same manner as the first sub-row decoder 5241. Each of the first sub-row decoder 5241 to the ninth sub-row decoder 5249 may select the row selection line CSL or the spare row selection line SCSL in the same manner as the sub-row decoder 3241 shown in FIG. 7.

FIG. 12 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. 12, the storage device 6000 includes a first storage cell array 6100_1, a second storage cell array 6100_2, a third storage cell array 6100_3 to a k-th storage cell array 6100_k, a first row decoder 6200_1, a second row decoder 6200_2, The third row decoder 6200_3 to the k-th row decoder 6200_k, the first column decoder 6300_1, the second column decoder 6300_2, the third column decoder 6300_3 to the k-th column decoder 6300_k, and the peripheral circuit 6400. The functions of the first storage cell array 6100_1 to the k-th storage cell array 6100_k, the first row decoder 6200_1 to the k-th row decoder 6200_k, and the first column decoder 6300_1 to the k-th column decoder 6300_k can be the same as those in reference to FIGS. 1 to The functions illustrated in Figure 10 are the same. Here, "k" can be determined by agreement or specification. For example, "k" may mean the number of banks or may be a positive integer greater than the number of banks.

The first row decoder 6200_1 to the k-th row decoder 6200_k and the first column decoder 6300_1 to the k-th column decoder 6300_k may be required to drive the first storage cell array 6100_1 to the k-th storage cell array 6100_k, respectively. In detail, the first storage cell array 6100_1 can be driven by the first row decoder 6200_1 and the first row decoder 6300_1. The first row decoder 6200_1 can use a plurality of row selection lines CSL and a plurality of spare row selection lines SCSL to control the first memory cell array 6100_1. The first column decoder 6300_1 can use a plurality of word lines WL to control the first memory cell array 6100_1. The remaining second storage cell array 6100_2 to the kth storage cell array 6100_k can be controlled in the same manner as the first storage cell array 6100_1.

Each of the first storage cell array 6100_1 to the k-th storage cell array 6100_k may be the same as the storage cell array 1100 shown in FIG. 1. In the first memory cell array 6100_1, the first plurality of memory cells can be selected by the plurality of row selection lines CSL (not shown in the figure, and the memory cells arranged at the intersection of the word line WL and the row selection line CSL) unit). As in the previous description, the second plurality of storage cells can be selected by the plurality of spare row selection lines SCSL (not shown in the figure, the storage located at the intersection of the word line WL and the spare row selection line SCSL) unit).

In an embodiment of the concept of the present invention, the storage device 6000 may include a plurality of input/output pads (not shown in the figure) to increase the data bandwidth. To this end, the storage device 6000 can select (that is, active) the word line WL in each of the at least two storage cell arrays in response to a start command from the outside. After that, the storage device 6000 can receive a read command or a write command from the outside and can select any row selection line in the selected storage cell array. As shown in FIG. 3, multiple bit lines connected to any row selection line can be selected together. The selected (ie, active) storage unit in the storage cell array selected according to the start command and the read or write command may be referred to as a target storage unit. As mentioned above, the data corresponding to the codeword can be stored in the target storage unit.

In the case where there is a defect in the target storage unit, the storage device 6000 may perform a repair operation on the target storage unit. For this reason, in each of the selected storage cell arrays, the storage device 6000 can use the storage cells connected to the spare row selection line to repair the target storage cells at the same time. The row repair operation performed in each of the selected memory cell arrays may be similar to the row repair operation described with reference to FIGS. 1 to 11. However, the row repair operation described above can be performed independently in each of the selected memory cell arrays. In other words, all target storage units corresponding to the codeword can be repaired, or some of the target storage units can be repaired.

The peripheral circuit 6400 includes a command and address (CMD/ADD) pad 6410, a first input/output pad to a z-th input/output pad (DQ1 to DQz) 6420, and an error correction circuit 6430. The peripheral circuit 6400 in FIG. 12 may include more input/output pads than the peripheral circuit 1300 shown in FIG. 1 to increase the data bandwidth. In an embodiment, "z" may be 512, 1024, or 2048.

FIG. 13 illustrates a flowchart of a testing method of a storage device according to an embodiment of the inventive concept. FIG. 13 will be explained with reference to FIGS. 4 and 5.

In operation S110, it is determined whether there is a defect in the first plurality of target storage units. As mentioned earlier, the defect may be caused by damage to the hardware of the storage unit. Also as previously described, the data corresponding to the codeword can be stored in the first plurality of target storage units selected in response to the external write command, or can be selected from the external read command selected in response to the The data of the codeword is read from the first plurality of target storage units. The judgment in operation S110 may be made based on the test performed during the wafer-level test step, for example. The unique characteristics of the storage unit can be tested to test the first plurality of target storage units. For example, when the storage unit is a dynamic random access storage unit, tRCD (row address strobe (RAS) to row address strobe (CAS) delay), tRP can be tested (Column precharge delay), tWR (write recovery delay), tREF (refresh cycle), etc.

In operation S120, in the case that there are defects in the first plurality of target storage units, it is determined whether data errors stored in the first plurality of target storage units cannot be corrected by error correction encoding and decoding. First, the number of errors in the data stored in the first plurality of target storage units can be counted. Then, based on the counted number of errors, it is determined whether the data errors stored in the first plurality of target storage units can be corrected by error correction encoding and decoding. The error correction encoding and decoding can be executed outside the storage device (for example, on the host or storage controller) or by an error correction circuit on the chip of the storage device (for example, the error correction circuit 1330 shown in FIG. 1). According to operation S120, if the counted number of errors is too large, the data errors stored in the first plurality of target storage units may not be corrected by using spare storage units or error correction encoding and decoding. That is, if the counted number of errors is too large, even if a spare storage unit can be used to replace some of the first plurality of target storage units, and store them in the first plurality of target storage units The data error for may still not be able to be corrected with the error correction data.

When it is determined in operation S120 that the data stored in the first plurality of target storage units cannot be corrected, in operation S130, it is determined whether there are defects in the second plurality of target storage units. As previously described with respect to FIG. 5, the second plurality of target storage units may be storage units connected to the selected word line WL and the spare row selection line SCSL, and store data through one of the sub-row decoders 3241 to 3257. Codeword. Here, the number of the second plurality of target storage units may be the same as the number of the first plurality of target storage units. As in operation S110, the judgment in operation S130 may be performed in a wafer-level test step based on testing, for example. The aforementioned unique characteristics of the storage units of the second plurality of target storage units (as previously described for operation S110) may be tested.

In operation S140, in the case that there are defects in the second plurality of target storage units, it is determined whether the data errors stored in the second plurality of target storage units can be corrected by error correction encoding and decoding. First, the number of errors in the data stored in the second plurality of target storage units can be counted. In the case where there is no defect in the second plurality of target storage units, or an error in the data stored in the second plurality of target storage units even when there is a defect in the second plurality of target storage units In the case where it is correctable, the second plurality of target storage units may be usable. Similar to operation S120, the error correction encoding and decoding in operation S140 may be performed outside the storage device (for example, the host or storage controller) or by an error correction circuit on the chip of the storage device (for example, the error correction circuit shown in FIG. 1 1330) to execute.

In operation S150, the second plurality of target storage units may be used to replace the first plurality of target storage units. In other words, even if an error occurs in the data due to the defect of the second plurality of target storage units, the above-mentioned error in the data stored in the second plurality of target storage units can be corrected by error correction encoding and decoding. Correction, the second plurality of target storage units may be usable. Therefore, the test method according to the conceptual embodiment of the present invention can improve the yield of the storage device.

FIG. 14 illustrates a block diagram of an application example of a storage device according to an embodiment of the inventive concept. 14, the computer system 7000 includes a host 7100, a user interface 7200, a storage module 7300, a network module 7400, a memory module 7500, and a system bus 7600.

The host 7100 can drive the components of the computer system 7000 and the operating system. In an embodiment, the host 7100 may include a controller for controlling various components of the computer system 7000, an interface among other components, and a graphics engine. The host 7100 may be a system-on-chip (SoC).

The user interface 7200 may include an interface for inputting data or commands to the host 7100 or outputting data to an external device. In an embodiment, the user interface 7200 may include a user input interface, such as a keyboard, keypad, buttons, touch pad, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor (Gyroscope sensor), vibration sensor, and piezoelectric sensor (piezoelectric sensor). The user interface 7200 may further include, for example, the following interfaces: liquid crystal display (LCD), organic light-emitting diode (OLED) display device, and active matrix OLED (active matrix OLED) AMOLED) display device, light-emitting diode (LED), speaker, and motor.

The storage module 7300 can store data. For example, the storage module 7300 can store data received from the host 7100. Alternatively, the storage module 7300 can transfer the data stored therein to the host 7100. In the conceptual embodiment of the present invention, the storage module 7300 can be implemented using, for example, the following non-volatile storage devices: erasable programmable read only memory (erasable programmable read only memory, EPROM), electrically erasable programmable read only memory (EPROM), Programmable read only memory (electrically erasable programmable read only memory, EEPROM), reverse and flash memory, reverse or flash memory (NOR flash memory), phase change random access memory (PRAM), resistive random Access memory (ReRAM), ferroelectric random access memory (FeRAM), magneto-resistive RAM (MRAM), or thyristor random access memory (thyristor RAM, TRAM) Wait. The storage module 7300 may be a storage device according to an embodiment of the inventive concept.

The network module 7400 can communicate with external devices. In an embodiment, the network module 7400 can support, for example, the following wireless communications: code division multiple access (CDMA), global system for mobile communication (GSM), and broadband code division multiple access (GSM). Access (wideband CDMA, WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (Wimax), Wireless local area network (wireless LAN, WLAN), ultra wide band (UWB), Bluetooth, and wireless display (WI-DI), etc.

The memory module 7500 can operate as the main memory, working memory, buffer memory, or cache memory of the computer system 7000. The memory module 7500 may include: volatile memory, such as dynamic random access memory and static random access memory; reverse or volatile memory, such as reverse and flash memory, reverse or flash memory Volume, phase change random access memory, resistive random access memory, ferroelectric random access memory, magnetoresistive random access memory, and thyristor random access memory. The memory module 7500 may include at least one of storage devices 1000, 2000, 3000, 4000, 5000, and 6000 according to an embodiment of the inventive concept.

The system bus 7600 can electrically connect the host 7100, the user interface 7200, the storage module 7300, the network module 7400, and the memory module 7500 to each other.

The storage device according to the embodiment of the inventive concept can increase the repair efficiency by increasing the usable row redundancy.

Although the concept of the present invention has been described with reference to different embodiments, it should be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the concept of the present invention. Therefore, it should be understood that the above embodiments are not restrictive, but illustrative.

1000, 2000, 3000, 4000, 5000, 6000‧‧‧Storage devices 1100, 2100, 3100, 4100, 5100‧‧‧Storage cell array 1101, 2101, 3101, 4101, 5101‧‧‧First pad 1108, 2108, 3108, 4108‧‧‧Eighth pad 1109, 2109, 3109, 4109, 5109‧‧‧ Ninth pad 1116, 2116, 3116, 4116‧‧‧ Sixteenth pad 1117, 2117, 3117, 4117‧‧‧ Tenth Seven pad 5102‧‧‧Second pad 5110‧‧‧Tenth pad 5111‧‧‧Eleventh pad 5118‧‧ Eighteenth pad 1200, 2200, 3200, 4200, 5200‧‧‧ Row decoder 1300, 6400 ‧‧‧Peripheral circuit 1310, 6410‧‧‧Command and address pad 1320‧‧‧First input/output pad~17th input/output pad 1330, 6430‧‧‧Error correction circuit 2120‧‧‧Switch 3201, 3208, 3209, 3216, 3217, 4201, 4208, 4209, 4216, 4217, 5201, 5202, 5209‧‧‧First repair circuit 3201_1, 3201_2, 3201_3, Fuseset<1>~Fuseset<x>‧‧‧ Fuse sets 3201_4, 4201_4‧‧‧Comparison circuit 3230, 4230, 5210‧‧‧Second repair circuit 3241,4241‧‧‧First sub-row decoder/sub-row decoder 3248, 4248‧‧‧Eighth sub-row Decoder/sub-row decoder 3249, 4249‧‧‧ ninth sub-row decoder/sub-row decoder 3256, 4256‧‧‧ sixteenth sub-row decoder/sub-row decoder 3257, 4257‧‧‧ tenth Seven sub-row decoder/sub-row decoder 3241_1‧‧‧Row selection line decoder 3241_2‧‧‧Spare row selection line decoder 4201_1, 4201_2, 4201_3‧‧‧Fuse set array 4260‧‧‧Segment decoder 4300, 5300‧‧‧Column decoder 5220‧‧‧Third repair circuit 5241‧‧‧First subrow decoder 5242‧‧‧Second subrow decoder 5249‧‧‧Ninth subrow decoder 6100_1‧‧‧ One storage cell array 6100_2‧‧‧Second storage cell array 6100_3~6100_k‧‧‧Third storage cell array~kth storage cell array 6200_1‧‧‧First row decoder 6200_2‧‧‧Second row decoder 6200_3~ 6200_k‧‧‧The third row decoder~the kth row decoder 6300_1‧‧‧The first column decoder 6300_2‧‧‧The second column decoder 6300_3~6300_k‧‧‧The third column decoder~The kth column decoder 6420‧‧‧First input/ Output pad to z-th input/output pad 7000‧‧‧Computer system 7100‧‧‧Host 7200‧‧‧User interface 7300‧‧‧Storage module 7400‧‧‧Network module 7500‧‧‧Memory Module 7600‧‧‧System bus BL, BL2~BLn‧‧‧Bit line BL1‧‧‧First bit line/bit line C_CTL‧‧‧Row control signal CA‧‧‧Row address CREN1‧‧‧ The first restoration enable signal CREN2‧‧‧The second restoration enable signal CREN3‧‧‧The third restoration enable signal CSL‧‧‧Row selection line DQ1~DQz‧‧‧The first input/output pad ~ the zth input /Output pad DQ17‧‧‧Seventeenth input/output pad/Seventeenth pad RA‧‧‧Column address RCA1, RCA2, RCA3, RCA1<1:x>, RCA2<1:x>, RCA3< 1:x>‧‧‧Repair row address S110, S120, S130, S140, S150‧‧‧Operate SBL, SBL2~SBLy‧‧‧Spare bit line SBL1‧‧‧First spare bit line/spare bit line SCSL‧‧‧Spare row selection lines SEG_1, SEG2~SEG_x‧‧‧Segment SEG<1:x>‧‧‧Segment signals WL, WL3~WLm‧‧‧Word line WL1‧‧‧First word line/word Element line WL2‧‧‧Second character line/character line

The above and other objectives and features will become apparent by reading the following description with reference to the following drawings, where unless otherwise specified, the same reference numbers in all the various figures represent the same elements, and in the various figures: 1 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. FIG. 2 illustrates a block diagram of the first pad shown in FIG. 1 in detail. FIG. 3 is a block diagram illustrating the relationship between the row selection line and the bit line shown in FIG. 1 in detail. FIG. 4 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. FIG. 5 illustrates a block diagram of the storage device shown in FIG. 4. FIG. FIG. 6 illustrates a block diagram of the repair circuit shown in FIG. 4 and FIG. 5. FIG. 7 illustrates a block diagram of the sub-row decoder shown in FIG. 4 and FIG. 5. FIG. 8 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. FIG. 9 illustrates a block diagram of the row decoder shown in FIG. 8. FIG. 10 illustrates a block diagram of the repair circuit shown in FIG. 9. FIG. 11 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. FIG. 12 illustrates a block diagram of a storage device according to an embodiment of the inventive concept. FIG. 13 illustrates a flowchart of a testing method of a storage device according to an embodiment of the inventive concept. FIG. 14 illustrates a block diagram of an application example of a storage device according to an embodiment of the inventive concept.

1000‧‧‧Storage device

1100‧‧‧Storage cell array

1101‧‧‧First Pad

1108‧‧‧The eighth pad

1109‧‧‧Ninth Pad

1116‧‧‧Sixteenth Pad

1117‧‧‧The seventeenth pad

1200‧‧‧line decoder

1300‧‧‧peripheral circuit

1310‧‧‧Command and address pad

1320‧‧‧The first input/output pad ~ the seventeenth input/output pad

1330‧‧‧Error correction circuit

BL‧‧‧Bit Line

CSL‧‧‧row selection line

SBL‧‧‧Spare bit line

SCSL‧‧‧Alternate Row Selection Line

WL‧‧‧Character line

Claims (20)

A storage device includes: a storage cell array, including a plurality of pads and a plurality of bit lines connected to a word line; and a row decoder, including a first repair circuit and a second repair circuit, in the first repair circuit The first repair row address is stored in the second repair circuit, and the second repair row address is stored in the second repair circuit, where the first repair row address and the received row address in a read command or a write command are When coincident, the row decoder is configured to select from among the plurality of bit lines other than the plurality of bit lines corresponding to the received row address in one of the plurality of pads Other bit lines are selected, and wherein when the second repair row address coincides with the received row address, the row decoder is configured to divide the received row address from among the plurality of pads Select another bit line from the plurality of bit lines other than the bit line corresponding to the row address. According to the storage device described in claim 1, the storage cell array further includes: a first plurality of storage cells connected to the word line and from the first plurality of the plurality of bit lines Bit line; and a second plurality of storage cells connected to the word line and a second plurality of bit lines from the plurality of bit lines, wherein the first plurality of storage cells and the The second plurality of storage units are provided in each of the plurality of pads, wherein when the second repair row address does not coincide with the received row address, the row decoder is configured to A first plurality of target storage units is selected from the first plurality of storage units, and wherein when the second repair row address coincides with the received row address, the row decoder is configured to The second plurality of target storage units are selected from the second plurality of storage units. According to the storage device described in claim 2, the number of defects in the second plurality of target storage units is smaller than the number of defects in the first plurality of target storage units, and the number of defects stored in the first plurality is The data of one target storage unit cannot be corrected by error correction encoding and decoding, and the data stored in the second plurality of target storage units can be corrected by the error correction encoding and decoding. As for the storage device described in item 2 of the scope of patent application, the number of the first plurality of target storage units and the number of the second plurality of target storage units are normal data and error corrections associated with the normal data The sum of the encoded and decoded parity data corresponds in size. As described in item 4 of the scope of the patent application, the storage device further includes: an error correction code circuit configured to use the parity data to perform the error correction encoding and decoding. According to the storage device described in claim 1, the row decoder further includes: a plurality of sub row decoders respectively connected to the plurality of pads, and the plurality of sub row decoders are configured to refer to the Receive the row address to select the first plurality of bit lines and select the second plurality of bit lines with reference to the first repair enable signal provided by the first repair circuit or the second repair enable signal provided by the second repair circuit Bit line. According to the storage device described in claim 6, the first repair circuit is configured to compare the first repair row address with the received row address, and restore the first repair to The energy signal is provided to the plurality of sub-row decoders, and wherein the second repair circuit is configured to compare the second repair row address with the received row address, and the second repair The enabling signal is provided to the plurality of sub-row decoders. According to the storage device described in item 6 of the scope of patent application, each of the plurality of sub-row decoders includes: a first row selection line decoder, configured to act as the first repair enable signal and the first If the second repair enable signal is not activated, the first plurality of bit lines are selected with reference to the received row address; and the second row selection line decoder is configured to be configured when the first repair is enabled If the signal and the second repair enable signal are activated, the second plurality of bit lines are selected. According to the storage device described in item 6 of the scope of patent application, the first plurality of bit lines and the second plurality of bit lines are respectively divided into column addresses used to select the word lines A plurality of segments, and the row decoder further includes: a segment decoder configured to decode the column address and provide segment information for the first repair circuit and the second repair circuit, the The segment information includes information on the row address corresponding to the character line. According to the storage device described in claim 9, the first repair circuit includes: a first plurality of fuse sets, in which a first plurality of repair row addresses are stored and the first plurality of repair row addresses The number is the same as the number of the plurality of segments; and a first comparison circuit is configured to compare the received row address with the first plurality of fuse sets activated by the segment information The first repair row address in the first plurality of repair row addresses of the fuse group is compared to generate the first repair enable signal, wherein the first repair circuit is configured to The repair enable signal is provided to one of the plurality of sub-row decoders, wherein the second repair circuit includes: a second plurality of fuse sets, in which a second plurality of repair row addresses are stored, and the second The number of repaired row addresses is the same as the number of the plurality of segments; and a second comparison circuit is configured to combine the received row address with the second plurality of fuse sets by the The second repair row addresses of the second plurality of repair row addresses of the second fuse set activated by the segment information are compared to generate the second repair enable signal, and the second repair circuit is It is configured to provide the second repair enabling signal to the plurality of sub-row decoders. A storage device includes: a storage cell array, including a first plurality of pads connected with a first character line and a second plurality of pads connected with a second character line, wherein the first plurality of pads and the The second plurality of pads are connected to a plurality of bit lines, and a plurality of storage cells connected to the first word line and the second word line are selected through a single activation command; and a row decoder including a first word line A repair circuit and a second repair circuit. The first repair row address is stored in the first repair circuit, and the second repair row address is stored in the second repair circuit. When the first repair row address is When the received row address in the read command or the write command coincides, the row decoder is configured to match the received row address from a plurality of bit lines in the first plurality of pads. Select a different first bit line of the plurality of bit lines from the bit lines of the address, and wherein when the second repair row address coincides with the received row address, the row decoding The device is configured to select a second bit line in the second plurality of pads from the plurality of bit lines that are different from the bit line corresponding to the received row address. According to the storage device described in item 11 of the scope of patent application, the number of target storage units selected by the row decoder among the plurality of storage units is related to normal data and error correction encoding and decoding associated with the normal data The sum of the parity data corresponds to the size. The storage device described in item 12 of the scope of patent application further includes: an error correction code circuit configured to use the parity data to perform the error correction encoding and decoding. According to the storage device described in claim 11, the row decoder further includes: a third repair circuit, storing a third row address in the third repair circuit, wherein when the third row address When coincident with the received row address, the row decoder is configured to divide from one of the first plurality of pads and from one of the second plurality of pads and the The third bit line is selected from the plurality of bit lines other than the bit line corresponding to the received row address. As for the storage device described in item 11 of the scope of patent application, when the received row address coincides with the first repair row address, the first repair circuit generates a first repair enable signal, wherein when the received row address coincides with the first repair row address, When the received row address coincides with the second repair row address, the second repair circuit generates a second repair enable signal, and the row decoder further includes: a plurality of sub-row decoders, respectively The first plurality of pads and the second plurality of pads are connected, and the plurality of sub-row decoders are configured to select when the first repair enable signal and the second repair enable signal are not activated The bit line corresponding to the received row address, the first bit line is selected when the first repair enable signal is activated, and when the second repair enable signal is activated Select the second bit line. A storage device, comprising: a plurality of storage cell arrays; and a plurality of row decoders respectively connected to the plurality of storage cell arrays, each of the plurality of row decoders includes a first repair row address stored therein A first repair circuit and a second repair circuit storing a second repair row address therein, wherein each of the plurality of storage cell arrays includes a plurality of pads connected to a word line and a plurality of pads connected to the plurality of pads Of the multiple bit lines, wherein at least two memory cell arrays in the multiple memory cell arrays are selected based on a single activation command, wherein when the received row address in the read command or the write command and the first When a repair row address coincides with each other, each of the at least two row decoders connected to the selected at least two memory cell arrays from the plurality of row decoders is in the plurality of pads In one pad, other bit lines are selected from the plurality of bit lines other than the bit line corresponding to the received row address, and when the received row address and the second When the repair row addresses coincide with each other, each of the at least two row decoders connected to the selected at least two memory cell arrays is divided by the received row bits in the plurality of pads Selecting a second bit line from the plurality of bit lines other than the bit line corresponding to the address. According to the storage device described in item 16 of the scope of patent application, in the selected at least two storage cell arrays, the number of target storage cells selected by the at least two row decoders and normal data and the The sum of the error correction code and the decoded co-location data associated with the normal data corresponds in size. The storage device described in item 17 of the scope of the patent application further includes: an error correction code circuit configured to use the parity data to perform the error correction encoding and decoding. According to the storage device described in item 16 of the scope of patent application, each of the plurality of row decoders further includes: a plurality of sub row decoders configured to select the bit corresponding to the received row address Element line, wherein the number of the plurality of sub row decoders is the same as the number of the plurality of pads, wherein in each of the plurality of row decoders, when the received row address is When a repair row address coincides, the first repair circuit provides a first repair enable signal to one of the plurality of sub row decoders, and wherein in each of the plurality of row decoders, When the received row address coincides with the second repair row address, the second repair circuit provides a second repair enable signal to the plurality of sub-row decoders. For the storage device described in item 16 of the scope of patent application, the first repair row address is different from the second repair row address.

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