1311323 八、本案若有化學式時， 式： (無） 請揭示最能顯示發明特徵的 九、發明說明： 【發明所屬之技術領域】 種可法，1311323 VIII. If there is a chemical formula in this case, the formula: (none) Please reveal the features that best show the characteristics of the invention. 9. Description of the invention: [Technical field to which the invention belongs]
负二禋運作，讀取、抹除以及程式化。 说外垾赞性記憶體， 漏失。快閃記憶體主要 在讀取運作期間，係利 用分頁緩衝器（page buffer)將鎖存資料（分頁 二 並存到選擇的分頁，這稱為八¥矯 4)取出 J刀只绝稱為刀頁緩衝态的感應運作（sensine opemtmn)。在程式化運作期間’儲存資料（即程式資料）係來 自於外部’並先將儲存資料载人分衝器中，再於適當的時 =以及控制之下載人記憶體正確齡置，這稱為分頁緩衝器的 資，載入運作。此外’分頁緩衝器會提供機制避免禁止程式化 的曰曰胞（cell)或已程式化的晶胞被程式化。當驗證運作於檢查 程式化或抹除的記㈣晶胞是否達到其目標（或想要的）臨界 電[位準4 ’分頁緩衝器會侧選擇分頁之記㈣晶胞的資料 位元，並且鎖存㈣值。隨後，分頁緩衝时將其資料位 1311323 元送到通過/失敗檢查電路，以確認那些資料位元為告知成功 的程式化或抹除之通過資料位元。 此類的分頁緩衝器已揭露於美國專利公告第5790458、 5761132以及5712818號中。請參閱第一圖，係為習知分頁緩衝 器之電路圖，如圖所示：此分頁緩衝器係連接至一對位元線BLe 及BLo，且包含一對鎖存器LAT^LAT2 (主要及快取）c>NM〇s 電晶體M1-M4會組成位元線選擇及偏壓電路，這會將位元線中 的一條連接至感應節點SO，並且會使其他的位元線處於浮接 (floating)狀態。介於位元線BLe與感應節點SO之間的是會回 應控制訊號BLSHFe的NMOS電晶體]VQ，介於位元線BLo與感 應節點SO之間的是會回應控制訊號blshFo的NMOS電晶體 M2。NMOS電晶體M3係連接於位元線BLe與控制訊號線 VIRPWR之間，而NMOS電晶體M4係介於BLo與VIRPWR之 間。NMOS電晶體M3及M4會分別回應控制訊號VBLe& VBLo。電晶體Mi〜M4會組成位元線選擇及偏壓電路，以使位 元線中的條連接至感應郎點§〇，並且會使其他的位元線處於 浮接狀態。 介於電源供應電壓VCC與感應節點so之間的是會回應控 制訊號PLOAD的PMOS電晶體M5 ; PMOS電晶體M6係連接於 VCC與主要鎖存器LAT1的主要鎖存節點沾之間，娜係由訊號 PBRST所控制。在赫_沾與接地輕vss之卩摘是串接的 1311323 疋NMOS電晶體M7及M8 ’會分咖應感應節励的電壓位準 聰M。職㈣M__⑽輪出端 .· 之間，會回應主要鎖存節點B的邏輯狀態而導通或關 f ’而輸出端點·X)會形成如顯示於第二圖中的通過/失敗檢 查電路。輸被諸DO崎輯絲係·於主要鎖存節· 的邏輯狀態’如當主要細咖為低轉時，輸出端點伽〇 係連接至VCC，而當主要鎖存節點B設定為高位準時，輸出端 點nWDO會與VCC電性隔離(處於浮接狀態）。 連接於感應節點SO與主要鎖存節點3間的舰〇8電晶體 M10會回應訊號BLSLT ;介於内部節點麵與主要鎖存節點b 之間的是會回應訊號PBDO_M〇s電晶體則；連接於vcc 與快取鎖存氣LAT2的快取鎖存節點a之間的pM〇s電晶體皿 會回應訊號PBSET ’·連接於快取鎖存節點與感應節點s〇之間的 NMOS電晶體M13會回應訊號PDUMp ;主要鎖存節點a與vss 之間則串接有NMOS電曰曰曰體M14及M15，ffi^NMOS電晶體M14 及M15會分別回應感應節點s〇的邏輯狀態及訊號pBLCHc ;介 於内部節點腦與快取鎖存器LAT2的快取鎖存節f^(A的相 反節點)的是NMOS電晶體M16，而在内部節點ND1與快取鎖存 節點A之間則連接有NMOS電晶體M17，NMOS電晶體M16及 M17會分別回應互相互補的資料訊號〇]^及111)〇。 當將程式資料位元為「！」（如二進位碼）载入到第一圖的 1311323 分頁緩衝H電路巾時’資料訊號Du邏輯上會設定為高位準， 而資料訊號nDLi會設定成低位準。内部節點ND1係經由組成分 別回應行選擇訊號YA及YB的行閘極電路iNM〇s電晶體M i 8 及M19，而連接至資料線du。介於資料線DLi與接地電壓之間 的NMOS電晶體M20會回應訊號DLD。 顯示於第一圖的分頁緩衝器之程式化中，程式資料位元會 載入到鎖存器LAT2，例如程式資料位元為「丨」，則資料訊號 DLi會麦成尚位準，而資料訊號n〇Li會變成低位準，nm〇s電 晶體M16會導通，而NM0S電晶體M17會關閉。同時，nm〇s 電晶體M18及M19會藉由行選擇訊號γΑ及ΥΒ而導通，藉此，鎖 存節點ηΑ會經由Μ18及Μ19而連接至資料線DLi。對於載入程 式資料位元而言，資料線Dli會經由NMOS電晶體M20而連接至 接地電壓。因此，「1」的程式資料位元會載入到鎖存節點A。 若程式資料位元為「0」，則資料訊號DLi會變成低位準，而資 料訊號nDLi會變成高位準。當電晶體M17使鎖存節點a 連接到處於接地電壓的資料線DLi時，程式資料位元「〇」會载 入到鎖存節點A。經由以上程序，所有的程式資料位元會依序 載入到刀頁緩衝器。在完成將程式資料位元載入到快取鎖存器 LAT2的運作之後’資料位元會轉移到主要鎖存sLAT1。首先， 主要鎖存器LAT1會藉由NM〇S電晶體M6的導通而初始化，且 感應節點SO會藉由PMOS電晶體M5而充電到高位準。隨後， 7 1311323 NM〇S電晶體Ml3會導通，而將程式資料位元從LAT2轉移到 若1」的程式^料位元已載入到快取鎖存器，者 NMOS電晶體奶剔導通時，其會鎖存在⑽的節點b。I 之’當「〇」的程式資料位元載入到快取鎖存器LAT2中時，nm〇s 電晶體Μ?會關，顺顧咖電晶咖料通是否藉奸 制訊號PBLCHM，LAT1的節點_保持其初始狀態。 載入到主要鎖存器LAT1巾的程式轉位元會放入選擇記 憶體単搞要程式化的選擇位猶之程式運作中，而其他的非 Ϊ擇Ϊ憶體單元將會禁止程式化。在轉持於主要鎖存器LATi 的貧料位το程式化期間，當作快取的快取鎖存器漏會將下 個程式資料位元帶至此處，—躲式化的時間。 取運作或私驗證運作躺’主要鎖存11LAT1會偵測 :存:屬於選擇分頁之記憶體單元中的資料位元，而在反向複 ^式倾作絲除驗證__，餘鎖存乳at2亦會如此 運作。 應節式驗簡中…但位元線BL狼0及感 ϊ ΓΓ 1選擇位元線(如BLe)在已充電到預定電壓 盘於Γ接㈣’此時’位元線健將會降低或保持其先 ' WNM〇S電晶體M1導通時’電流會經由腿⑽電晶 so的節點S〇 ’若選擇記憶體單元為導通單元，則節點 的電流會赫馨記龍單摘财雜，並.點SO的 1311323 電壓降低在NMOS電晶體M7的臨界電壓之下。儘管NM〇s電晶 體鳩導通，但是鎖存器LAT1不會改變其電壓狀態。若選擇記 憶體單福關單元，則來自於NMOS電晶體M5的電流會使位 於節點SO的電舰步的增加到超過繼沉電晶體術臨界電廢 之較高為準。在NM0S電晶體M8導通的_，鎖存節點b會連 接至接地輕’贿主要齡^ΑΤ1的邏輯雜反向或保持主 要鎖存器LAT1賴輯狀態。在反向複製財化或齡驗證運作 期間，快取鎖存器LAT2會偵測儲存於選擇分頁之記憶體單元中 的資料位元，然後賴應的結果轉移啦要鎖存亂纽，即位 元線BLe與BLo及感應節點SO會放電，而選擇位元線(如BLe)在 充電到縣電驗，會變成浮接，使其電壓在短助不會有太 大的變動。由於NMOS電晶體M1的導通，電流會經由⑽⑽電 晶體M5而送到節點S0 ’若選擇記憶體單元為導通單元，則送 到節點so㈣流會麵_記舰單元，鱗致節點s〇的電 壓在選擇峨鮮摘臨界龍之下。儘管舰⑽電晶體mi5 會藉由控制峨PBLCHC從低鱗郝辦的漏而導通，但 ，要鎖存器LAT1會保持目前的狀態。若選擇記憶體單元為關閉 早70 ’則來自於PMOS電晶體M5的電流會對感應節點s〇逐步的 充電’亚導致節點so的電壓增加到超過職〇8電曰曰曰體MU的臨 界電壓。NM0S電晶體Ml5會導通，以使快取鎖存器[纽的遞 輯狀態反向，職取鎖存HLAT2會侧選擇記題的狀態，旅 1311323 將其轉移到主要鎖存器LAT1。 程式化或抹除會伴隨驗證運作來確認已程式化或抹除的記 憶體單元是否處於職之臨界電壓。程式化或抹除選擇分頁記 憶體單70之結果會藉由保持於主要鎖存H LAT1中的邏輯狀 態，以及顯示於第二圖中的通過/失敗檢查電路而決定。第二圖 的通過/失敗檢查電路2通常包括多個保險絲F1〜Fk、ΝΜ〇§電晶 體⑽卜反相器請5以及鎖存器LAT3。分頁緩衝器3係與記憶 體單元陣列1連接，絲會連制分魅3的輸出端點 nWDO ’每-個會連群分頁緩衝器，當其對應的位元線 中至少有一個缺陷時，保險絲會燒斷。 分配到每個分頁緩衝器的輸出端點nWD〇會藉由主要鎖存 器LATi_的鎖存節點a而設定，若儲存節點a設定為高準 位:PMOS電晶體M9會導通，而使輸出端·點nWD〇變成高準位， 並得知選擇記龍單元已完全程式化或抹除，此時，節點_ 會保持低辦’錢秘失敗喊PF變成低辦。若鎖存節點 A處於低辦’ pM〇s電晶體M9會咖，並 單元尚未完全_式或或齡’鱗，__高位準2 通過/失敗訊號PF變成高位準。 3义 因為-個保險絲會分配給一群分頁緩衝器或位元線，所以 對應此處之位元線中的—個有缺陷時，放棄多個連接至燒斷的 保險絲之分·細是何戟的,此_微絲結構會 1311323 降低佈局效率以及增加冗餘單元陣列的尺寸。 因此，在美國專利號6813184的專利中，提出一種於快閃記 憶裝置中’免祕_的方絲避免祕陷之位元線干擾其他 之位το線之程式化或抹除驗證。根據此篇專利所提丨的流程， 必須先將所有的位元線健掃描—次，—但發現是缺陷位元 線，則強造寫入驗證通過（verifypass)的：身料至其相對應的分 頁緩脑。此餘之_的是必聊描財的位元線位址，而 此數目遠大於可以被修補的數目（約為1%)，因此浪費許多時間。 此外’此篇專砸未提及連接位域有缺陷時該如何進行 防範的動作’因此無法全面的防止讀寫失敗。 ^鑑赴频閃錢财置之賴，本伽人有感其未至 、。遂竭盡、智’悉心研究克服，憑從事該項產業多年之 研發出—種可防謂寫失狀㈣記憶體裝置 ^寫方法，可達職牡避免有缺陷之位元軒擾其他之 4 70線之程式化或抹除驗證。 ❿ 【發明内容】 之快閃Ϊ憶體= 1於提供—種防止讀寫失敗 擾其他正常位轉之料化或齡=較有_植元線干 記憶=即Ϊ於提供—種防止讀寫失敗之快閃 ，、碩寫方法，猎以達到省時之功效者。 11 !311323 為達上述目的，本發明之技術實現如下： —種防止讀寫失敗之快閃記憶體讀 ==錯誤位址資訊，直接將缺_:=存 位，藉_行 址進行程触雜·料他正常行位 本發明之另-目的，即在於提供—餘止讀寫 其讀寫方法’藉以增加佈局效率以及減小冗餘單 為達上述目的，本發明之技術實現如下： 一種防止讀寫失敗之快閃記憶體裝置，係包含有 -種防止讀寫失敗之快閃記㈣裝置，係包含有：— 陣列與-冗餘晶胞陣列；-分頁緩衝器電路，係由複數個= 緩衝器所構成’該每-分衝ϋ係經由—主要以及冗餘位元 線與該主要以及冗餘晶胞_連接；—行雜f路與—冗餘間 極電路，係與該分賊衝器電路連接，肋選擇部份之分頁緩 衝器’以使被選擇到的該些分頁緩衝器連接至其對應的資料 線；-資料輸人緩衝器，係與該閘極電路以及該冗餘行間極電 路連接；-位址輸人缓衝n ’用以循序的產生行位址訊號；一 冗餘電路，用以儲存該主要晶胞陣列之行位址，且會將該位址 輸入緩衝器輸入之行位址訊號與一缺陷的行位址做比較；一行 解碼器，係與該行閘極電路以及該冗餘閘極電路連接，用以將 該行位址訊號與該缺陷的行位址所對應之分頁緩衝器主要以及 几餘位元線行位址解碼出來；一錯誤位元寫入電路，用以將該 12 1311323 應解碼出之該分頁緩衝壯要以及冗餘位元線行 一 麟1並轉該職魏之啸結果寫入 懂，述和其他目的、特齡優難更明顯易 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 =參閱第三®，係為本㈣之快閃記紐實施方塊圖，如 =示：雜閃記憶體主要包含有—主要晶輯_、冗餘晶 胞陣列12、分頁緩衝器電路13、行_電路14、冗餘閘極電路 ⑷、資料輸入緩衝器15、行解碼器16、錯誤位元寫入電路17、 位址輸人緩衝’以及冗餘冑路19。每個日日日胞陣舰由多組反 及串，組成，每組反及串均會連接耻要位元線以及冗餘位元 線。每組反及串係由一選擇電晶體、共同源極線、接地選擇電 晶體以及連接於選擇電晶體與接地選擇電晶體間之一串記憶體 晶胞所構成。 & 分頁緩衝器電路13係由複數個分頁緩衝器所組成，其一端 係經由主要以及冗餘位元線與主要以及冗餘晶胞陣列連接，另 一端則與分別與行閘極電路14以及冗餘行閘極電路⑷連接。位 址輸入緩衝器18會循序的產生行位址訊號，並輸入至行解碼器 16以及冗餘電路19。冗餘電路19會儲存用來指明主要晶胞陣列 11之行位址，且會將自位址輸入緩衝器18輸入之行位址訊號與 缺陷的行位址做比較；若二者匹配，則冗餘電路19會使冗餘選 擇訊號中的一個致能(enable)，以指明缺陷的行。行解碼器π、 13 1311323 行閘極電路14以及冗餘行閘極電路141則會選擇一部份的分頁 緩衝器’以使被選擇到的分頁緩衝器連接至其對應的資料線 DLi，再與資料輸入緩衝器15連接’而外部資料係經由資料輸入 緩衝器15而輸入。錯誤位元寫入電路π會於冗餘電路19使冗餘 選擇訊號中的一個致能(enable)時’將行解碼器16所對應解碼 出之分頁缓衝器缺陷行位址透過資料輸入緩衝器丨5寫入，，驗證 通過”的訊號；而餘冗餘電路19中之冗餘選擇訊號均未致能 (disable)時’錯誤位元寫入電路π會將行解碼器16所對應解碼 出之分頁緩衝器冗餘行位址寫入”驗證通過”的訊號。因此，利 用已儲存在冗餘電路19中的錯誤位址資訊，直接將有缺陷行位 址解碼出來，並將驗證通過之資料寫入其相對應之分頁緩衝器 内’即不需要將所有的位元線位址掃描一次，藉以節省行位址 的掃描時間，同時也可避免缺陷行位址影響其他正常行位址進 行程式化或抹除驗證的判斷。 請參閱第四圖（a)以及第四圖（b)，係均為第三圖中冗餘電 路之詳細電路圖，如圖所示：該冗餘電路主要係由一冗餘致能 訊號產生單元191以及一錯誤位址偵測單元192所構成。當電源 訊號Vcc—經啟動而穩定時，訊號PU則會被拉升為邏輯”丨，，的狀 態，若電源訊號Vcc尚未啟動或穩定時，訊號pu則會保持為邏 輯的狀態。當訊號PU為邏輯，，〇，，的狀態時，會將節點c之位準 利用PMOS電晶體P1設為邏輯”1 ”，並經由反相器I n 1使節點j)達到 邏輯的位準’如此，則PM〇s電晶體P2則形成通路，並使節點 c不會因為漏電而失去邏輯”丨，，之位準。當電源訊號Vcc經啟動而 穩定時’訊號PU則會被拉升為邏輯”1”的狀態，並將NM〇s電晶體 14 1311323 N1形成通路，此時，若保險絲(FUSE)為斷開的狀態時，則代表 此几餘電路已被用於修復有缺陷行位址，故節點C的邏輯位 準”1”將經過反相器INI、IN2而輸出，使訊號貺!)-611 (冗餘致能 訊號)達到邏輯”1”之位準，·若保險絲(FUSE1)為完好的狀態時， 則代表此冗餘電路尚未被用於修復有缺陷行位址，故節點c的邏 輯位準”1”將經過醒〇s電晶體N1漏掉而改變為邏輯位準，，〇，，，並 使訊號RED_en (冗餘致能訊號）成為邏輯，，〇”之位準。 φ 在錯誤位址偵測單元丨92中，節點E會經由PMOS電晶體P3將 其位準預設為邏輯”1” ’當執行正常之讀寫時，訊號FBW(錯誤位 元線寫入訊號）係設為邏輯之狀態，而訊號FBWn(錯誤位元線 寫入訊號之反相訊號)係設為邏輯”1”，此時，訊號CA(行位址輸 入訊號）、CAn(行位址輸入訊號之反相訊號）不論為邏輯”丨，，或邏 輯0來控制NMOS電晶體N3、N4之運作，只要其相對應之保險絲 FUSE2、FUSE3為斷開之狀態，則節點e之位準將保持為邏輯”j”， 若冗餘位元線有用於修復錯誤之位元線，則訊號服])—en (冗餘 致能訊號)係為邏輯”1”之位準，訊號FBWn、RED_en經過互斥反 或閘G1的運算後’其輸出端節點ρ將被設為邏輯”1”之位準，節 點E、F之位準經由一反及閘G2運算之後，其輸出得到節點G之位 準為邏輯節點G之位準再經由一反相器IN3輸入，而得到訊 號YR(匹配冗餘行位址訊號），因此訊號YR之位準為邏輯”丨，，，即 代表此行位址所對應到的位元線有缺陷或錯誤產生，而且有利 用冗餘行位址進行修復。 當執行錯誤位元線之寫入時，訊號FBW(錯誤位元線寫入訊 號）係設為邏輯”1”之狀態，而訊號FBWn(錯誤位元線寫入訊號之 15 1311323 反相訊號）係設為邏輯，，0”，若此時冗餘位元線有用於修復錯誤 之位元線，則訊號RED—en (冗餘致能訊號）係為邏輯I”之位 準，如此一來，透過鎖存器LAT4以及緩衝器BUF1，訊號FA(存於 ，餘保險絲之錯誤行位址訊號）將輸出保險絲^^见丨之邏輯狀 態，亦即錯誤行位址訊號。PM〇s電晶體p4係於此時提供讀取訊 號?A時所需的電源(PMOS電晶體P4導通而NMOS電晶體N7斷路）， 若訊號RED_en係為邏輯”1”之位準，則訊號{^會經由pM〇s電晶體 P4存器LAT4、_S電晶體N5、N6而讀出。PMOS電晶體P5係 用於餐取訊號YR’其原理等同第四圖（a)中之pM〇s電晶體p2。而 NMOS電晶體N5、N6以及N7係控制電路之導通或斷路，避免全導 通或全斷路之現象發生。 請參閱第五圖，係為第三圖中行解碼器之詳細電路圖，如 圖所示：該行解碼器主要係由一位址多工器單元丨61以及一行解 碼單元162所構成。位址多工器單元丨6丨係利用訊號丽來選擇外 部送入的行位址訊號CA或是存於冗餘保險絲之錯誤行位址訊號 FA ’其結果則送入行解碼單元M2，並經由行解碼單元M2内之 反及閘G3〜G6以及反或閘G9〜G10將行位址選擇訊號ya、yb解碼出 來。此外，為使行解碼單元162保持正常運算，則必須藉由一解 碼致能訊號YDEN來控制。解碼致能訊號YDEN之產生，係將訊號 RED_en以及訊號YR輸入至一及閘⑶後，再將其輸出與訊號FBW 輸入至一互斥反或閘G7 ’互斥反或閘G7之輸出即為訊號yden， 再將δίΐ號YDEN輸入至反及閘G6，如此便可以使行解碼單元162 保持正常運算。利用位址多工器單元161來選擇外部送入的行位 址机號CA或是存於冗餘保險絲之錯誤行位址訊號fa，再將結果 16 1311323 送入行解碼單元162 ’如此便能直接存取原來錯誤位元線的行位 址。 凊參閱第六圖’係為第三圖中行閘極電路以及冗餘行閘極 電路之詳細電路圖，如圖所示：行閘極電路14以及冗餘行閘極 電路141係均與一資料線DLi連接。行閘極電路μ中之行位址選 擇訊號YAO〜YA63係依序地被致動，同時，行位址選擇訊號 yBO〜YB31亦為依序地被致動。舉例來說，當任一行位址選擇訊 號ΥΒΟ〜YB31被致動時，行位址選擇訊號γΑ〇〜γΑ63亦依序地被致 動’因此’一資料位元將從2048個資料位元ρΒ〇〜ρΒ2〇47中被選 擇出來。冗餘行閘極電路141中之冗餘行位址訊號YR〇〜YR7亦為 依序地被致動。 同時請參閱第七圖，係為第三圖中分頁緩衝器之詳細電路 圖’如圖所示：該分頁緩衝器13係包含一相當於電源供應之pM〇s 電晶體P6 ’ 一相當於傳遞(pass)電晶體的丽〇8電晶體N9，一由 二反相器IN4、IN5所構成之鎖存器LAT5，以及控制鎖存器LAT5 之NM0S電晶體N10、Nil。於此分頁緩衝器中，資料會經由讀的 操作’將其自相對應的記憶體晶胞中載入節點Η，並可於程式化 的操作時’將節點H之資料寫人相對應的記憶體晶胞巾。節點Η 亦可當作與第六圖中之訊號DLi耦接，而進行讀寫之操作。 請參閱第八圖，係為第三圖中資料輸入緩衝器之詳細電路 圖，如圖所示：該資料輸入緩衝器15係由一反或閘G11以及一反 相器IN6串接而成。訊號FBW與訊號DI(資料輸入訊號)係輸入反 或閘G11，且反或閘Gl 1之輸出再輸入反相器IN6而獲得輸出訊號 DLi ’即為第六圖中之訊號DLi，亦可當作與第六圖中之節點11 17 1311323 耦接’而進行整體讀寫之操作。當訊號FBW為邏輯，，丨，，之位準時， 則不淪訊號DI之位準為何，均會將訊號DLi成為邏輯”丨”之位 準，並將邏輯”1”之位準寫入錯誤位元線中，即為將第三圖中行 解竭器16所對應解碼出之分頁緩衝器缺陷行位止寫人，，驗證通 過的訊號’使之不影響其他正常行位址進行程式化或抹除驗證 的判斷。 凊參閱第九圖，係為本發明之實施流程圖，如圖所示：在 程式化、反向複製之程式化(C〇py_back pr〇gram)以及抹除驗證 運作中，步驟S1會提供一冗餘電路中之冗餘初始位址，並在步 ,S2中判斷此冗餘初始位址是否用於修復缺陷行位址，若為 疋，則於步驟S3中將此冗餘初始位址所對應到之分頁緩衝器缺 陷位元線行位址解碼出來，並於步驟邡中將驗證通過的訊號寫 入該分頁緩衝器缺陷位元線行位址中；若為否，則於步驟以中 將此冗餘初始位址所對應到之分頁緩衝器冗餘位元線行位址解 碼出來，並於步驟S6中將驗證通過的訊號寫入該分頁緩衝器冗 餘位元線行位址中；於步驟S7中判斷是冗餘電路中之冗餘初始 位址是否為最後-位址，若為否，麟步獅巾將冗餘初始位 址加1(代表下一位址），並重複步驟步驟S1 ;若為是，則結^此 流程。 ' >σ 因此，本發明不回額外增加使用保險絲之數量，藉以妗加 佈局效率以及減小冗餘單元陣列的尺寸，且可確實達 寫失敗之功效者。。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍= 18 圍當視後附之 準叫發明之保魏 【圖式簡單說明】 第-圖係為習知分頁緩衝器之電路圖。Negative two operations, reading, erasing, and stylization. Say the external memory, missed. The flash memory mainly uses the page buffer to store the latched data (the page 2 is stored in the selected page, which is called the 8 ¥4). The J-knife is only called the knife page. Inductive operation of the buffer state (sensine opemtmn). During the stylization operation, the 'storage data (that is, the program data) is from the external 'and the data will be stored in the sub-injector first, and then at the appropriate time = and the controlled downloader memory is correctly aged. This is called The paging buffer is loaded and operated. In addition, the 'paged buffer' provides mechanisms to prevent stylized cells or stylized cells from being stylized. When the verification is performed to check whether the stylized or erased cell (four) cell reaches its target (or desired) critical power [level 4' page buffer will select the page header (four) cell data bit, and Latch (four) value. Subsequently, when paging, the data bits 1311323 are sent to the pass/fail check circuit to confirm that the data bits are the stylized or erased pass data bits that inform the success. A paged buffer of this type is disclosed in U.S. Patent Nos. 5,790,458, 5,761,132 and 5,712,218. Please refer to the first figure, which is a circuit diagram of a conventional page buffer, as shown in the figure: This page buffer is connected to a pair of bit lines BLe and BLo, and includes a pair of latches LAT^LAT2 (mainly Cache) c> NM〇s transistors M1-M4 will form a bit line selection and bias circuit, which will connect one of the bit lines to the sensing node SO and cause other bit lines to float (floating) state. Between the bit line BLe and the sensing node SO is an NMOS transistor VQ that responds to the control signal BLSHFe. Between the bit line BLo and the sensing node SO is an NMOS transistor M2 that responds to the control signal bShFFo. . The NMOS transistor M3 is connected between the bit line BLe and the control signal line VIRPWR, and the NMOS transistor M4 is between BLo and VIRPWR. The NMOS transistors M3 and M4 respond to the control signals VBLe& VBLo, respectively. The transistors Mi~M4 form a bit line selection and biasing circuit to connect the bars in the bit line to the sense point and cause the other bit lines to be in a floating state. Between the power supply voltage VCC and the sensing node so is a PMOS transistor M5 that responds to the control signal PLOAD; the PMOS transistor M6 is connected between the VCC and the main latch node of the main latch LAT1, Controlled by the signal PBRST. The pick-up of the 1311323 疋 NMOS transistors M7 and M8 ’ will be connected to the grounding light vs. The pass/fail check circuit as shown in the second figure is formed by the (4) M__(10) round-trip.., which will respond to the logic state of the main latch node B and turn on or off f' and the output terminal X). When the main latching node B is set to a high level, when the main latching node B is set to a high level, the main latching node B is set to a high level. The output terminal nWDO is electrically isolated from VCC (in a floating state). The port 8 transistor M10 connected between the sensing node SO and the main latch node 3 will respond to the signal BLSLT; between the internal node surface and the main latch node b, the response signal PBDO_M〇s transistor will be connected; The pM〇s transistor between vcc and the cache latch node a of the cache latch LAT2 will respond to the signal PBSET '·the NMOS transistor M13 connected between the cache latch node and the sense node s〇 It will respond to the signal PDUMp; the main latch nodes a and vss are connected in series with the NMOS devices M14 and M15, and the ffi^ NMOS transistors M14 and M15 will respectively respond to the logic state of the sensing node s and the signal pBLCHc; Between the internal node brain and the cache latch section f^ (the opposite node of A) of the cache latch LAT2 is the NMOS transistor M16, and between the internal node ND1 and the cache latch node A is connected The NMOS transistor M17 and the NMOS transistors M16 and M17 respectively respond to mutually complementary data signals 〇]^ and 111)〇. When the program data bit is "!" (such as the binary code) is loaded into the 1311323 page buffer H circuit towel of the first figure, the data signal Du is logically set to a high level, and the data signal nDLi is set to a low level. quasi. The internal node ND1 is connected to the data line du via the row gate circuits iNM〇s transistors M i 8 and M19 which form the response line selection signals YA and YB. The NMOS transistor M20 between the data line DLi and the ground voltage responds to the signal DLD. In the stylization of the page buffer shown in the first figure, the program data bit is loaded into the latch LAT2. For example, if the program data bit is "丨", the data signal DLi will be in the position of the data, and the data is The signal n〇Li will become low, the nm〇s transistor M16 will turn on, and the NM0S transistor M17 will turn off. At the same time, the nm〇s transistors M18 and M19 are turned on by the row selection signals γΑ and ,, whereby the latch node ηΑ is connected to the data line DLi via Μ18 and Μ19. For the load data bit, the data line Dli is connected to the ground voltage via the NMOS transistor M20. Therefore, the program data bit of "1" is loaded to the latch node A. If the program data bit is "0", the data signal DLi will become a low level and the data signal nDLi will become a high level. When the transistor M17 connects the latch node a to the data line DLi at the ground voltage, the program data bit "〇" is loaded to the latch node A. Through the above procedure, all program data bits are sequentially loaded into the tool page buffer. After the loading of the program data bit into the operation of the cache latch LAT2 is completed, the data bit is transferred to the main latch sLAT1. First, the main latch LAT1 is initialized by the turn-on of the NM〇S transistor M6, and the sensing node SO is charged to a high level by the PMOS transistor M5. Subsequently, 7 1311323 NM〇S transistor Ml3 will be turned on, and the program data bit is transferred from LAT2 to if the program bit of 1" has been loaded into the cache latch, and the NMOS transistor is turned on. It will be latched at node b of (10). When the program data bit of I's "〇" is loaded into the cache latch LAT2, the nm〇s transistor will be turned off, depending on whether the coffee chip is passed or not. PBLCHM, LAT1 Node_ keeps its initial state. The program index bits loaded into the main latch LAT1 will be placed in the selection memory, and the program selection will be programmed, while other non-selective memory units will be disabled. During the stylization of the lean bit το of the main latch LATi, the cache latch as a cache will bring the next program data bit here, the time of the escape. Take the operation or private verification operation. The main latch 11LAT1 will detect: save: the data bit in the memory unit of the selected page, and in the reverse complex mode, the verification is __, the remaining latch milk At2 will also work like this. It should be checked in the section...but the bit line BL wolf 0 and the ϊ ΓΓ 1 select the bit line (such as BLe) when it has been charged to the predetermined voltage plate at the connection (four) 'at this time' the bit line will be reduced or maintained When the 'WNM〇S transistor M1 is turned on, the current will pass through the node of the leg (10), and if the memory cell is selected as the conduction unit, the current of the node will be picked up by the singer. The voltage of 1311313 at point SO is lowered below the threshold voltage of NMOS transistor M7. Although the NM〇s transistor is turned on, the latch LAT1 does not change its voltage state. If the memory unit is selected, the current from the NMOS transistor M5 will increase the electric ship step at the node SO to a value higher than the critical electric waste of the sinking transistor. At the NMOS of the NM0S transistor M8, the latch node b will be connected to the grounded light or the main latch LAT1. During the reverse copying or ageing verification operation, the cache latch LAT2 detects the data bits stored in the memory cells of the selected page, and then shifts the result to latch the hash, ie, the bit Lines BLe and BLo and the sensing node SO will discharge, and the selected bit line (such as BLe) will become floating when charging to the county, so that the voltage will not change much in the short help. Due to the conduction of the NMOS transistor M1, the current is sent to the node S0 via the (10) (10) transistor M5. If the memory cell is selected as the conduction unit, it is sent to the node so(4) flow meeting _ the ship unit, the voltage of the node s〇 Under the selection of fresh picking critical dragons. Although the ship (10) transistor mi5 will be turned on by controlling the leakage of the 峨PBLCHC from the low level, the latch LAT1 will remain in its current state. If the memory cell is selected to be off 70' early, the current from the PMOS transistor M5 will gradually charge the sensing node s', causing the voltage of the node so to increase beyond the threshold voltage of the operating electrode MU. . The NM0S transistor Ml5 will be turned on, so that the cache latch [the recursive state of the button is reversed, the job capture latch HLAT2 will select the state of the note, and the trip 1311323 transfers it to the main latch LAT1. Styling or erasing is accompanied by a verification operation to confirm whether the programmed or erased memory cells are at the threshold voltage. The result of stylizing or erasing the selected page memory block 70 is determined by the logic state held in the main latch H LAT1 and the pass/fail check circuit shown in the second figure. The pass/fail check circuit 2 of the second figure typically includes a plurality of fuses F1 to Fk, an electric crystal (10), an inverter 5, and a latch LAT3. The page buffer 3 is connected to the memory cell array 1, and the output terminal nWDO of each of the ciphers 3 is connected to each of the corresponding grouped page buffers. When at least one of the corresponding bit lines has a defect, The fuse will blow. The output terminal nWD〇 assigned to each page buffer is set by the latch node a of the main latch LATi_, if the storage node a is set to a high level: the PMOS transistor M9 is turned on, and the output is made The end point nWD becomes a high level, and it is known that the selected dragon unit has been completely programmed or erased. At this time, the node _ will remain low. If the latch node A is in the low-level 'pM〇s transistor M9, and the unit is not yet fully _ or or the age' scale, the __high level 2 pass/fail signal PF becomes a high level. 3 Because a fuse will be assigned to a group of page buffers or bit lines, so when the corresponding one of the bit lines here is defective, give up the connection of multiple fuses to the blown fuse. This _ microwire structure will 1311323 reduce layout efficiency and increase the size of redundant cell arrays. Therefore, in the patent of U.S. Patent No. 6,831,184, a stylized or erased verification of the bit line of the 'silent-free' in the flash memory device is prevented from interfering with other bits of the το line. According to the process proposed in this patent, all the bit lines must be scanned first—time, but if it is found to be a defective bit line, then the verification pass (verifypass) is made: the body material corresponds to its corresponding The paging is slowing down the brain. The rest of the _ is the bit line address of the must-see, and this number is much larger than the number that can be repaired (about 1%), so a lot of time is wasted. In addition, this article does not mention how to prevent the connection when the connection bit field is defective. Therefore, it is impossible to comprehensively prevent read and write failure. ^In the light of the strobe money, the Benja people feel that they have not arrived.遂 尽 、 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Stylized or erased verification of the line. ❿ 【Abstract】 The flash flash memory = 1 in the provision of a kind of prevention of reading and writing failures disturbing the normalization of other normal bits or age = more than _ plant line dry memory = that is to provide - prevent reading and writing The flash of failure, the mastering method, and the hunting to save time. 11 !311323 In order to achieve the above purpose, the technical implementation of the present invention is as follows: - Flash memory read to prevent read/write failure == Error address information, directly _:= save, borrow _ address to touch The other purpose of the present invention is to provide a method for reading and writing the read and write vocabulary, thereby increasing the layout efficiency and reducing the redundancy. To achieve the above object, the technical realization of the present invention is as follows: A flash memory device that prevents read and write failures includes a flash memory (four) device that prevents read and write failures, and includes: - an array and a redundant cell array; - a page buffer circuit, which is composed of a plurality of = The buffer constitutes 'the per-divided impulse is connected to the primary and redundant unit cells via the primary and redundant bit lines; the line-and-redundant interpole circuit is associated with the branch The thief circuit is connected, the rib selects a portion of the page buffer 'to connect the selected page buffers to their corresponding data lines; - the data input buffer, the gate circuit and the redundancy Inter-line circuit connection; - address input buffer n ' For sequentially generating a row address signal; a redundant circuit for storing the row address of the main cell array, and inputting the address into the buffer input row address signal and a defective row address Comparing; a row decoder is connected to the row gate circuit and the redundant gate circuit, and the paging buffer corresponding to the row address signal and the defective row address is mainly and several bits The line row address is decoded; an error bit write circuit is used to decode the page buffering strong and the redundant bit line line 1 1 1311323 and transfer the result to the Wei Zhixiao. The other embodiments and the special features are more obvious. The preferred embodiments are described below, and the detailed description is as follows. [Embodiment] = Refer to the third ®, which is the block diagram of the (4) flash flash, as shown in the figure: the flash memory mainly contains - the main crystal _, the redundant cell array 12, the page buffer circuit 13. Line_circuit 14, redundant gate circuit (4), data input buffer 15, row decoder 16, error bit write circuit 17, address input buffer ', and redundant circuit 19. Each day and day cell is composed of multiple sets of anti-strings, each of which will connect the shame bit line and the redundant bit line. Each set of reverse and string is formed by a selection transistor, a common source line, a ground selection transistor, and a string memory cell connected between the selection transistor and the ground selection transistor. & page buffer circuit 13 is composed of a plurality of page buffers, one end of which is connected to the main and redundant cell arrays via main and redundant bit lines, and the other end and row gate circuit 14 respectively The redundant row gate circuit (4) is connected. The address input buffer 18 sequentially generates row address signals and inputs them to the row decoder 16 and the redundancy circuit 19. The redundancy circuit 19 stores a row address indicating the main cell array 11, and compares the row address signal input from the address input buffer 18 with the row address of the defect; if the two match, The redundancy circuit 19 enables one of the redundant selection signals to indicate the row of the defect. The row decoder π, 13 1311323 row gate circuit 14 and the redundant row gate circuit 141 select a portion of the page buffer 'to connect the selected page buffer to its corresponding data line DLi, and then The data is input to the data input buffer 15 and the external data is input via the data input buffer 15. The error bit write circuit π will enable the buffer decoder defect row address decoded by the row decoder 16 to pass through the data input buffer when the redundancy circuit 19 enables one of the redundant selection signals. The device 写入5 writes, and verifies the signal passing through; and when the redundant selection signal in the redundancy circuit 19 is not enabled, the error bit writing circuit π decodes the row decoder 16 correspondingly. The paging buffer redundant row address is written with the "verify pass" signal. Therefore, the defective row address is directly decoded by using the error address information stored in the redundancy circuit 19, and the verification is passed. The data is written into its corresponding paging buffer. That is, it is not necessary to scan all the bit line addresses once, so as to save the scanning time of the row address, and also avoid the defective row address affecting other normal row addresses. For the judgment of stylization or erase verification, please refer to the fourth figure (a) and the fourth figure (b), which are detailed circuit diagrams of the redundant circuit in the third figure, as shown in the figure: the redundant circuit is mainly Produced by a redundant enable signal The element 191 and an error address detecting unit 192 are formed. When the power signal Vcc is stabilized by the startup, the signal PU is pulled up to a logic "丨," state, if the power signal Vcc has not been activated or stabilized. The signal pu will remain in a logical state. When the signal PU is in the state of logic, 〇, ,, the position of the node c is set to logic "1" by using the PMOS transistor P1, and the node j) is brought to the logic level via the inverter I n 1 . 'In this case, the PM〇s transistor P2 forms a path, and the node c does not lose logic due to leakage. The level is normal. When the power signal Vcc is activated and stabilized, the signal PU will be pulled up. It is in the state of logic "1", and the NM〇s transistor 14 1311323 N1 forms a path. At this time, if the fuse (FUSE) is in the off state, it means that the circuit has been used to repair the defective line. The address, so the logic level "1" of node C will be output through the inverters INI, IN2, so that the signal 贶!)-611 (redundant enable signal) reaches the level of logic "1", if the fuse When (FUSE1) is in a good state, it means that this redundant circuit has not been used to repair the defective row address, so the logic level "1" of node c will be changed to logic after waking up s transistor N1. The level, 〇,,, and the signal RED_en (redundant enable signal) becomes the logical, 〇" level. φ In the error address detection unit 丨92, the node E will preset its level to logic "1" via the PMOS transistor P3. When performing normal reading and writing, the signal FBW (error bit line write signal) The system is set to the logic state, and the signal FBWn (the inverted signal of the error bit line write signal) is set to logic "1". At this time, the signal CA (line address input signal), CAn (row address) The inverting signal of the input signal) whether it is logic "丨," or logic 0 to control the operation of the NMOS transistors N3, N4, as long as the corresponding fuses FUSE2, FUSE3 are in the off state, the level of the node e will remain For the logic "j", if the redundant bit line has a bit line for repairing the error, the signal service])-en (redundant enable signal) is the level of the logic "1", and the signals FBWn, RED_en pass After the operation of the exclusive reversal or gate G1, the output node ρ will be set to the logic "1" level, and the positions of the nodes E and F will be operated by the inverse gate G2, and the output will be the position of the node G. The level of the logical node G is then input through an inverter IN3, and the signal YR is obtained (matching the redundant row address) The signal), therefore, the level of the signal YR is logical "丨,", that is, the bit line corresponding to the address of the line is defective or incorrectly generated, and the redundant row address is used for repair. When the writing of the error bit line is performed, the signal FBW (error bit line write signal) is set to the logic "1" state, and the signal FBWn (the error bit line write signal 15 1311323 inverted signal) Set to logic, 0", if the redundant bit line has a bit line for repairing the error, the signal RED_en (redundant enable signal) is the level of logic I", thus Through the latch LAT4 and the buffer BUF1, the signal FA (stored in the error line address signal of the remaining fuse) will output the logic state of the fuse, that is, the error line address signal. The PM〇s transistor p4 provides the power required to read the signal A at this time (the PMOS transistor P4 is turned on and the NMOS transistor N7 is turned off). If the signal RED_en is at the logic "1" level, the signal is {^ will be read via pM〇s transistor P4 register LAT4, _S transistor N5, N6. The PMOS transistor P5 is used for the meal signal YR' and its principle is equivalent to the pM〇s transistor p2 in the fourth figure (a). The NMOS transistors N5, N6 and N7 are connected or disconnected from the control circuit to avoid full conduction or full open circuit. Referring to FIG. 5, it is a detailed circuit diagram of the row decoder in the third figure. As shown in the figure, the row decoder is mainly composed of an address multiplexer unit 丨61 and a row of decoding unit 162. The address multiplexer unit 利用6丨 uses the signal to select the externally sent row address signal CA or the error row address signal FA of the redundant fuse, and the result is sent to the row decoding unit M2, and The row address selection signals ya, yb are decoded by the inverse gates G3 to G6 and the inverse gates G9 to G10 in the row decoding unit M2. In addition, in order for the row decoding unit 162 to maintain normal operation, it must be controlled by a decoding enable signal YDEN. The decoding enable signal YDEN is generated by inputting the signal RED_en and the signal YR to the gate (3), and then inputting the output and the signal FBW to a mutually exclusive inverse gate G7 'mutually exclusive or the output of the gate G7 is The signal yden, and then the δί ΐ YDEN is input to the inverse gate G6, so that the row decoding unit 162 can maintain the normal operation. The address multiplexer unit 161 is used to select the externally sent row address machine number CA or the error row address signal fa stored in the redundant fuse, and then the result 16 1311323 is sent to the row decoding unit 162 ' Directly access the row address of the original error bit line.第六 Refer to the sixth figure' for the detailed circuit diagram of the row gate circuit and the redundant gate circuit in the third figure. As shown in the figure, the row gate circuit 14 and the redundant gate circuit 141 are both connected to a data line. DLi connection. The row address selection signals YAO to YA63 in the row gate circuit μ are sequentially activated, and the row address selection signals yBO to YB31 are also sequentially activated. For example, when any row address selection signal ΥΒΟ~YB31 is actuated, the row address selection signals γΑ〇~γΑ63 are also sequentially activated. Therefore, a data bit will be from 2048 data bits. 〇~ρΒ2〇47 was selected. The redundant row address signals YR〇~YR7 in the redundant row gate circuit 141 are also sequentially activated. At the same time, please refer to the seventh figure, which is the detailed circuit diagram of the page buffer in the third figure. As shown in the figure, the page buffer 13 includes a pM〇s transistor P6' equivalent to the power supply. Pass) The transistor 8 of the transistor, N9, a latch LAT5 consisting of two inverters IN4, IN5, and the NM0S transistors N10, Nil of the control latch LAT5. In this page buffer, the data will be loaded into the node from the corresponding memory cell via the read operation, and the data of the node H can be written to the corresponding memory during the stylized operation. Body cell towel. The node 亦可 can also be used as a read/write operation by coupling with the signal DLi in the sixth figure. Please refer to the eighth figure, which is a detailed circuit diagram of the data input buffer in the third figure. As shown in the figure, the data input buffer 15 is formed by a reverse gate G11 and a reverse phase inverter IN6. The signal FBW and the signal DI (data input signal) are input to the inverse gate G11, and the output of the inverse gate Gl 1 is input to the inverter IN6 to obtain the output signal DLi ', which is the signal DLi in the sixth figure, and can also be The operation of the overall read and write is performed by coupling with the node 11 17 1311323 in the sixth figure. When the signal FBW is logic, 丨,, and the timing is correct, the signal DLi will become the level of the logic "丨" and the logic "1" level will be written into the error. In the bit line, the page buffer buffer row corresponding to the row decompressor 16 in the third figure is decoded, and the passed signal 'is verified to not affect other normal line addresses for stylization or Erasing the judgment of verification. Referring to the ninth figure, it is a flowchart of the implementation of the present invention, as shown in the figure: in the stylization, reverse copy stylization (C〇py_back pr〇gram) and erase verification operation, step S1 will provide a Redundant initial address in the redundant circuit, and in step S2, it is determined whether the redundant initial address is used to repair the defective row address, and if 疋, the redundant initial address is used in step S3. Corresponding to the page buffer defect bit line row address is decoded, and in step 将 the verification passed signal is written into the page buffer defect bit line address; if not, then in the step Decoding the page buffer redundant bit line row address corresponding to the redundant initial address, and writing the verified signal into the page buffer redundant bit line address in step S6 In step S7, it is determined whether the redundant initial address in the redundant circuit is the last address, and if not, the Linshi Shi towel adds 1 to the redundant initial address (representing the next address) and repeats Step S1; if yes, the process is completed. ' > σ Therefore, the present invention does not add an additional amount of fuses, thereby increasing the layout efficiency and reducing the size of the redundant cell array, and can indeed achieve the effect of writing failure. . Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any skilled person skilled in the art, without departing from the spirit and scope of the invention, [Simple diagram of the diagram] The first diagram is a circuit diagram of a conventional paging buffer.
第二圖係為習知通戰敗檢查電路圖。 f三圖係為本發日此_記憶體實施方塊圖。 _均為本發明冗餘電路 第，係為本發卿之詳細電關。圖。 ^圖係為本發明行閘極電路以及冗餘行閘極電路之詳細電路 第七圖係為本發縣胃緩補之詳細電路圖。 第八圖係為本發明資料輸人麟H之詳細電路圖 第九圖係為本發明之實施流程圖。 【主要元件符號說明】 11主要晶胞陣列 13分頁緩衝器電路 141冗餘行閘極電路 16行解碼器 162行解碼單元 18位址輸入緩衝器 191冗餘致能訊號產生單元 IN1-IN6反相器 !2冗餘晶胞陣列 14行閘極電路 15資料輸入緩衝器 161位址多工器單元 17錯誤位元線寫入電路 19冗餘電路 192錯誤位址偵測單元 FUSE1-FUSE3 保險絲 19The second picture is a circuit diagram of the Xizhitong defeat test. f Three diagrams are the implementation of this _ memory implementation block diagram. _ are the redundant circuit of the present invention, which is the detailed electric switch of the present. Figure. The figure is the detailed circuit of the gate circuit and the redundant gate circuit of the invention. The seventh figure is the detailed circuit diagram of the stomach relief of the county. The eighth drawing is a detailed circuit diagram of the information input of the present invention. The ninth drawing is a flowchart of the implementation of the present invention. [Main component symbol description] 11 main cell array 13 page buffer circuit 141 redundant row gate circuit 16 row decoder 162 row decoding unit 18 address input buffer 191 redundancy enable signal generating unit IN1-IN6 inversion 2 redundant cell array 14 row gate circuit 15 data input buffer 161 address multiplexer unit 17 error bit line write circuit 19 redundancy circuit 192 error address detection unit FUSE1-FUSE3 fuse 19