JP2551017B2 - Data correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] When a phase error detection signal is not defined in the interface between a recording / reproducing device and a control device and a phase error is detected in read data, it is easy to correct error data in the control device. The data correction method to be used for the purpose of supplying an error pointer signal capable of surely correcting the error data to the ECC circuit, and the data demodulated by the phase error detection signal and the re-reading instruction signal to the recording / reproducing device. Inverted signal creating means for inverting, a synchronizing means, and a data inverting means are provided, and a CRC for calculating a data error by calculating using a cyclic code
A circuit, a selection means for selecting a calculation result for the re-read data of the CRC circuit, and a calculation result for the data read before, a storage means for respectively storing the selection result of the selection means, and a storage means When the recording / reproducing apparatus detects a phase error from the data read again from the recording medium, a bit corresponding to the position where the phase error is detected is provided. Is inverted and sent to the control device so that the calculation result of the CRC circuit sent by the sending means is used for error correction of the ECC circuit.

[Industrial applications]

The present invention relates to a recording / reproducing device for reading data from a recording medium and a control device for controlling the recording / reproducing device, and particularly there is no transfer regulation of a phase error detection signal on the interface, and a phase error is detected in the read data. At this time, the present invention relates to a data correction method which facilitates error data correction in a control device by inverting and transferring a bit corresponding to a phase error detection position of read data.

For example, in a miniaturized magnetic tape device, the number of interface signal lines is limited due to restrictions on its physical size, etc. ing.

Therefore, the magnetic tape device cannot notify the magnetic tape control device of a data error due to a phase error. Even if a phase error occurs in the data read from the magnetic tape due to noise or peak shift, this phase error Some data is sent to the magnetic tape controller as it is.

By the way, the data transferred to the magnetic tape controller is corrected by an ECC circuit or the like which corrects the error using an error correction code. However, if the error correction is not successful, the magnetic tape controller Instructs the magnetic tape device to reread the data.

However, the data read again in the same state may not be able to be corrected again by the magnetic tape control device, and the reading of the required data may fail. Therefore, it is necessary that the error data based on the phase error can be easily corrected without changing the interface specification.

[Conventional technology]

Even if a phase error is detected from the data read from the magnetic tape between the magnetic tape device and the magnetic tape control device of the interface that cannot transfer the phase error detection signal,
The magnetic tape device sends this data as it is to the magnetic tape control device, and the magnetic tape control device corrects the data error by an ECC circuit or the like. If the ECC circuit cannot correct the error, the magnetic tape device is requested to reread.

[Problems to be solved by the invention]

As described above, conventionally, even if a magnetic tape device detects a phase error, the phase error cannot be notified to the magnetic tape control device, and the erroneous data is sent to the magnetic tape control device as it is. Although it is corrected by the ECC circuit, if it cannot be corrected, the magnetic tape device is instructed to reread.

However, if a phase error occurs due to the peak shift due to the pattern effect, even if the data is read again, the data read again in the same state as the previously read data will be corrected by the ECC circuit under the same conditions. Then, like the last time, it may not be possible to correct, and there is a problem that the system operating by connecting the magnetic tape device stops.

Therefore, it is an object of the present invention to supply an error pointer signal to the ECC circuit, which can surely correct error data.

[Means for solving problems]

 FIG. 1 is a block diagram of the principle of the present invention.

The head 3 of the recording / reproducing device 26 reads out data from the recording medium and sends it to the demodulation circuit 5 via the amplification circuit 4. The demodulation circuit 5 creates a reference clock from the read data, demodulates the data with this reference clock, sends the reference clock to the synchronizing means 29 and the register 11 of the control device 27, and simultaneously demodulates the synchronizing means 29. Send to.

The synchronizing means 29 sends the input data to the data inverting means 30 in synchronization with the reference clock.

When neither the phase error detection signal transmitted by the demodulation circuit 5 nor the re-reading instruction signal transmitted by the drive control circuit 7 is input, the inversion signal generation means 28 does not transmit a signal to the synchronization means 29, and the synchronization means 29 Since the data inverting means 30 is not instructed to invert the data, the data inverting means 30 sends the input data as it is to the register 11 of the control device 27.

The register 11 of the control device 27 is controlled by the control circuit 13,
The skew of the input data is adjusted by the reference clock sent from the demodulation circuit 5, and the data is sent to the bus 25.

The CRC circuit 12 calculates the data sent to the bus 25 using a cyclic code, and sends the result to the selecting means 31. Since the error retry signal is not sent from the control circuit 13 to the selection means 31, the calculation result of the CRC circuit 12 is stored in the storage means 32.

The data sent from the register 11 is stored in the buffer 23 via the bus 25 by the control signal sent from the control circuit 13. The ECC circuit 22 corrects any error in the data stored in the buffer 23.

If this error correction is correctly performed, the data error signal indicating the error correction failure is not stored in the register 21,
The control circuit 13 causes the data in the buffer 23 to be sent out via the register 24.

If the ECC circuit 22 fails to correct the data error, a data error signal is sent from the register 21 to the control circuit 13,
As described above, the control circuit 13 sends a data rereading signal to the drive control circuit 7 and sends an error retry signal to the selecting means 31.

When the re-read data is input to register 11, CR
The C circuit 12 sends the calculation result to the selecting means 31. Selection means 3
1 stores the calculation result in the storage means 32 based on the error retry signal so as not to destroy the previous calculation result.

Therefore, the previous operation result remains in the storage means 32, and the sending means 33 exclusively ORs the previous operation result left in the storage means 32 and the operation result of the reread data. It is sent to the ECC circuit 22.

Therefore, the ECC circuit 22 uses the CRC circuit 12 sent by the sending means 33.
The error correction of the data can be performed by using the exclusive OR of the calculation result of the last time and the calculation result of the re-read data as the error pointer signal.

[Action]

With the above configuration, when the control device 27 instructs the rereading of the data, the phase error is detected again, and when the phase error detection signal is input to the inversion signal creating means 28, the inversion signal creating means 28 synchronizes with the synchronization means. Data inversion means 30 via 29
In order to instruct the data to be inverted, the bit "1" corresponding to the position where the phase error of the data synchronized with the reference clock is detected by the synchronizing means 29 is inverted to "0" and "0" to "1". It becomes possible.

Therefore, since it is possible to invert the bit in which the phase error has occurred from the recording / reproducing device 26 to the control device 27 and to send it out, the CRC circuit 12 of the control device 27 has the bit inverted, so Sends a different calculation result to the selection means 31, stores the previous calculation result and the calculation result of the re-read data in the storage means 32, and the sending means 33 excludes the previous calculation result and the re-read calculation result. In order to send the result of the logical OR and cause the ECC circuit 22 to perform the error correction operation,
Error correction can be facilitated.

[Embodiment] FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

In the magnetic tape device 1, the drive control circuit 7 is controlled by the control circuit 13 of the magnetic tape control device 2 to drive the magnetic tape (not shown), and data is read from the magnetic tape by using the head 3 as in FIG. Is read out and sent to the demodulation circuit 5 via the amplification circuit 4.

The demodulation circuit 5 sends the reference clock to the T terminals of the D flip-flops 8 and 9 and outputs the data to the D terminal of the flip-flop 8.
Send to the terminal. Therefore, the flip-flop 8 sends the data synchronized with the reference clock from the Q terminal to the exclusive OR circuit 10.

Since the flip-flop 9 is sending "0" from the Q terminal when the AND circuit 6 is sending "0", it is an exclusive OR.
The circuit 10 sends the input data as it is to the register 11 of the magnetic tape controller 2.

When the magnetic tape control device 2 instructs rereading of data as in FIG. 1, the drive control circuit 7 inputs the rereading instruction signal “1” to the AND circuit 6. Then, when a phase error occurs due to peak shift or noise in the data read from the demodulation circuit 5 from the magnetic tape, the demodulation circuit 5 inputs the phase error detection signal “1” to the AND circuit 6.

Therefore, the AND circuit 6 sends "1" to the D terminal of the flip-flop 9, and the flip-flop 9 sends "1" to the exclusive OR circuit 10 from the Q terminal in synchronization with the reference clock.

Therefore, the exclusive OR circuit 10 inverts it to "0" when the bit of the data transmitted by the flip-flop 8 is "1" and inverts it to "1" when it is "0" and transmits it to the register 11.

Therefore, the bit at the position where the phase error occurs is inverted and sent to the register 11.

The register 11 of the magnetic tape control device 2 is a reference clock sent by the demodulation circuit 5, adjusts and stores the skew of the data sent by the exclusive OR circuit 10, and sends it to the bus 25 according to an instruction from the control circuit 13.

The CRC circuit 12 calculates the data sent to the bus 25 using a cyclic code, and the result is tristate gate circuit 14
And send to 16. As the error retry signal from the control circuit 13, "0" is NOT circuit 15 and tri-state gate circuit 16
Therefore, the tristate gate circuit 16 does not operate, the tristate gate circuit 14 opens the gate, and the operation result of the CRC circuit 12 is stored in the register 17.

The operation result stored in the register 17 is the exclusive OR circuit 19
And stored in the register 20.

At this time, since the register 18 has been cleared by the control circuit 13, the exclusive OR circuit 19 stores the same contents as the contents of the register 17 in the register 20.

The data sent from the register 11 is stored in the buffer 23 via the bus 25 by the control signal sent from the control circuit 13. The ECC circuit 22 uses the operation result of the register 20 as an error pointer signal, and corrects the data stored in the haffer 23 if there is an error.

If this error correction is correctly performed, the data error signal indicating the error correction failure is not stored in the register 21,
The control circuit 13 causes the data in the buffer 23 to be sent out via the register 24.

When the ECC circuit 22 fails to correct the data error, a data error signal is sent from the register 21 to the control circuit 13,
As described above, the control circuit 13 sends the data re-reading signal to the drive control circuit 7, sets the error retry signal to "1", and sends it to the NOT circuit 15 and the tri-state gate circuit 16.

When the re-read data is input to register 11, CR
The C circuit 12 outputs the operation result to the tri-state gate circuits 14 and 16
To send to. The NOT circuit 15 is sending out "0", the tri-state gate circuit 14 does not operate, the tri-state gate circuit 16 opens the gate, and the operation result is stored in the register 18. The previous operation result remains in the register 17, and the exclusive OR circuit 19 exclusively ORs the operation results of the registers 17 and 18 and stores the result in the register 20.

Therefore, the calculation result corresponding to the bit in which the phase error has occurred remains in the register 20. Therefore, the ECC circuit 22 can correct the data error by using the calculation result left in the register 20 as the error pointer signal.

[Effects of the Invention] As described above, according to the present invention, when there is no transfer regulation of the phase error detection signal on the interface between the magnetic tape device and the magnetic tape control device, the ECC circuit surely corrects the error data. Since it is possible to send an error pointer signal, it is possible to easily correct error data.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention. In the figure, 1 is a magnetic tape device, 2 is a magnetic tape control device, 3 is a head, 4 is an amplification circuit, 5 is a demodulation circuit, 6 is an AND circuit, 7 is a drive control circuit, 8 and 9 are flip-flops, 10, 19 is an exclusive OR circuit, 11,17,18,20,21,24 are registers, 12 is a CRC circuit, 13 is a control circuit, 14,16 is a tri-state gate circuit, 15 is a NOT circuit, 22 is an ECC circuit, 23 is a buffer, 25 is a bus, 26 is a recording / reproducing device, 27 is a control device, 28 is an inverted signal creating means, 29 is a synchronizing means, 30 is a data inverting means, 31 is a selecting means, 32 is a storing means, 33 is a sending means. It is a means.

Claims (1)

(57) [Claims] 1. A recording / reproducing apparatus (26) comprising a circuit for detecting a phase error of data read from a recording medium, and transmitting the data after detecting a phase error of the data, and the recording / reproducing apparatus (26). ), And corrects the data transmitted by the recording / reproducing apparatus (26) using an error correction code (2).
In the control device (27) provided with 2), the recording / reproducing device (26) is provided with a signal of the phase error of the data detected by the phase error detection circuit and the data sent from the control device (27). With the signal to instruct re-reading,
An inversion signal generating means (28) for transmitting a signal instructing data inversion, a data inversion instruction signal transmitted by the inversion signal generating means (28), and data read from the recording medium are synchronized with a reference clock. When the synchronizing means (29) and the data synchronized with the reference clock and the data inversion instruction signal are inputted from the synchronizing means (29), "1" of the bit of the data is set to "0" and "0" is set to "0". A data inverting means (30) for inverting to "1" is provided, and the control device (27) is provided with a CRC circuit (12) for performing arithmetic operation using a cyclic code and detecting a data error, and the CRC circuit (12). ), Selection means (31) for selecting the calculation result for the reread data and the calculation result for the data read before, and storage means (32) for storing the selection result of the selection means (31). ) And the contents stored in the storage means (32) And a sending means (33) for sending a logical sum of the data and sending it, and when the recording / reproducing device (26) is instructed by the control device (27) to reread the data, the phase is read from the data read again from the recording medium. When an error is detected, "1" of the bit corresponding to the position where the phase error is detected is inverted to "0", "0" is inverted to "1", and the result is sent to the control device (27). By that,
In the control device (27), the calculation result of the CRC circuit (12) sent by the sending means (33) is used for error correction of the ECC circuit (22).