JP2550286B2 - Method for forming contact hole for metal wiring in semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates relates to a method for forming a contact hole for the metal wiring in semiconductor devices, in particular, contact
It relates to a method enabling an improved integrity of the barrier metal on the tactile surface .

[0002]

2. Description of the Related Art In the conventional method for forming metal wiring of a semiconductor device, the shadow effect of the contact hole in the sputtering process of the barrier metal to be deposited on the contact surface increases the aspect ratio of the contact hole. The integrity of the barrier metal is reduced.

FIG. 3 is a partial sectional view of a semiconductor for explaining a conventional method for forming metal wiring of a semiconductor device. First, as shown in FIG. 1A, a gate silicon oxide film 12, a gate polysilicon film 13 and a cap gate silicon oxide film 14 are sequentially deposited on a silicon substrate 11.
Next, as shown in FIG. 2B, the cap gate silicon oxide 14, the polysilicon film 13, and the gate silicon oxide film 12 are etched by photolithography to form the gate 1
3'is formed, a part of the silicon substrate 11 is exposed, ions are implanted into the exposed portion, and heat treatment is performed to form a source / drain junction. Then, as shown in FIG. 3C, the surface, that is, the cap gate silicon oxide.
A silicon oxide layer is deposited on the side of the gate 13 'of layer 14 and on the source / drain junction.

Next, a sidewall spacer is formed on the side surface of the gate 13 ', and the silicon oxide film 16 is anisotropically etched to form a cap gate silicon oxide 14. Although not shown in the figure, when the bit line and the capacitor are formed after forming the sidewall spacer 16, undulations having a height of 1 μm or more occur between the circuit portion and the cell portion. Therefore, BPSG 17 or 03‐USG (ozone‐u
n-doped silicate glass: a silicate glass that is not doped with ozone) is deposited and planarization is performed to remove undulations, thereby ensuring the depth of focus for photolithography.

Next, as shown in FIG. 3D, an insulating film 17 is formed on the circuit portion to a thickness of 1 μm or more.

[0006] Next, as shown in (E) of FIG, on the source / drain, by photolithography, the contact hole. Where the diameter of the contact hole is 0.5
When the thickness is less than μm, the aspect ratio of the contact hole 18 becomes 2 or more.

Next, as shown in FIG. 1F, a barrier metal 19 is formed in the contact hole 18 and on the insulating film 17 by the sputtering method. Here, as the barrier metal, any one of Ti, TiN, TiW, MoSi _{2 and the} like is used.

When the aspect ratio of the contact hole is 2 or more, the barrier metal 19 on the source / drain 15 is formed.
The step coverage of is reduced by the shadow effect of the contact hole 18, and the integrity of the barrier metal at the corner portion 19 'of the contact hole is reduced. In some cases, the barrier metal does not sputter on the corners, and the metal formed in the next step is in direct contact with the silicon surface.

Since the silicon of the source / drain 15 and the metal of the metal wiring (not shown, for example, Al) are in direct contact with the outer periphery of the source / drain 15 where the barrier metal is not deposited, a spiking phenomenon occurs, This results in poor connection characteristics.

[0010]

In order to solve the above-mentioned problems of the prior art, the present invention improves the maintainability of the barrier metal at the bottom of the contact hole even when the aspect ratio is 2 or more. Improve the contact characteristics of the metal wiring.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a contact hole for connecting metal wiring to a semiconductor substrate through the contact hole, the method including the following steps: A step of forming a contact surface to be connected to a metal wiring; a step of forming a small hole having a side surface insulated from a conductive layer on the contact surface; a step of forming a barrier metal contact portion on the bottom surface and the side surface of the small hole; a semiconductor substrate A step of forming an insulating film on the entire surface of the step; a step of forming a contact hole by removing a predetermined part of the insulating film on the barrier metal contact portion.

Another object of the present invention is to provide a method of forming a contact hole for connecting a metal wiring to a semiconductor substrate through the contact hole, the method including the following steps: a gate silicon oxide film on a semiconductor substrate. , a polysilicon film for a gate, a step of sequentially depositing a cap gate silicon oxide film; and etching the cap gate silicon oxide film, a polysilicon film, the gate silicon oxide film in order to create a gate electrode pattern, the semiconductor by photolithography Exposing a predetermined portion of the substrate; forming a source / drain junction in the exposed portion of the semiconductor substrate by ion implantation and thermal diffusion; depositing a silicon oxide film on the surface, etching back, and gate and cap gate silicon oxide Of forming side wall spacers on the side surface of the cap; Step of depositing a first insulating film on the barrier metal film; over preparative depositing a barrier metal film on the side surfaces and the source / drain junctions on the silicon oxide film on a sidewall spacer process by photolithography, the first insulating film And a step of forming a barrier metal protective film that sufficiently covers the contact surface; a step of etching the barrier metal film using the barrier metal protective film as a mask to form a barrier metal contact portion; cap gate silicon oxide A step of depositing a second insulating film on a surface having etching selectivity with respect to silicon oxide on a sidewall spacer and a barrier metal; a step of forming a cell on a silicon substrate;
A step of forming a third insulating film on the surface; a step of forming a contact hole on the barrier metal contact portion by etching the third, second and first insulating films .

A third object of the present invention is to provide a method of forming a contact hole to a metal wiring of a semiconductor device, the method comprising the steps of: gate silicon oxide, polysilicon on a semiconductor substrate; Step of sequentially depositing cap gate silicon oxide; step of forming a gate by etching cap gate silicon oxide, polysilicon, gate silicon oxide to expose a predetermined portion of the semiconductor substrate; ion implantation and thermal diffusion of the semiconductor substrate A step of forming a contact surface on the exposed part; a step of depositing a first insulating film on the contact surface and etching back to form a small hole in which two gate electrodes are insulated by an insulator side wall; Forming a barrier metal contact on the substrate; forming a bit line and a capacitor on the substrate; silicon Forming a contact hole for connecting metal wires to the contact surface through the contact hole; forming a second insulating film on the substrate.

Another object of the present invention is to provide a semiconductor device having a contact hole structure for connecting metal wiring to a semiconductor substrate, which comprises:
"U" shaped barrier metal contact part whose bottom surface contacts the contact surface of the semiconductor substrate and is insulated from the surroundings except the contact part; insulating film from the upper end of the "U" shaped barrier metal contact part An insulating film that surrounds the contact hole up to the surface of. Here, the bottom surface of the barrier metal is made larger than the surface of the contact surface.

[0015]

1 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to the present invention, particularly a method of forming a contact hole and a barrier metal contact portion.

First, as shown in FIG. 1A, a gate silicon oxide film 22, a gate electrode polysilicon 23, and a cap gate silicon oxide film 24 are sequentially deposited on a silicon substrate 21. Next, as shown in FIG. 3B, the cap gate silicon oxide film 24, the polysilicon film 23, and the gate silicon oxide film 22 are etched by photolithography to form a gate 23 'pattern. Next, the source / drain junction 25 is formed on the exposed surface of the silicon substrate 21 by ion implantation and thermal diffusion.

Next, as shown in FIG. 3C, a silicon oxide film 26 is deposited on the surface, that is, on the side surface of the gate 23 'on the cap gate silicon oxide film 24 and on the source / drain junction 25. Then, by depositing the silicon oxide film 26 and anisotropically etching back,
A side wall spacer 26 for insulating the gate 23 'is formed on the side surface of the gate 23' and the cap gate silicon oxide 24, and a small hole composed of the following three planes, that is, the surface of the source / drain and two surfaces of the side wall spacer. Form G.

Then, as shown in FIG. 3D, on the entire surface, that is, on the side surface of the cap gate silicon oxide 24 upper sidewall spacer, on the source / drain junction 25, that is, in the small hole.
A barrier metal film 29 is deposited on the inner surface of the G region by the sputtering method. Here, as the barrier metal 29, any one of Ti, TiN, TiW, and MoSi ₂ is used. The aspect ratio equal to or smaller than 1 reduces the shadow effect, and the barrier metal 29 can be sufficiently deposited even on the inner surface of the small hole G, thus improving the integrity of the barrier metal. Note that a silicide can be used instead of the barrier metal.

Next, as shown in FIG. 2A, an insulating film 210 (first insulating film ) made of silicon nitride is deposited on the barrier metal film 29.

Next, a photoresist is coated on the first insulating film 210, and a photoresist pattern 211 used as a mask for etching the first insulating film 210 is formed by exposure and development. Where the baseline is slightly longer than the length of the source / drain junction 25 photoresist pattern
211 is formed on the overlapping surface that is depicted by looking at the surface of the source / drain junction through the bottom surface of the barrier metal 29. Here, the base line is parallel to the direction of the eyelet.

Next, as shown in FIG. 1B, the first insulating film 2 is formed using the photoresist pattern 211 as an etching mask.
Anisotropically etch 10 to form a barrier metal protector 210 'of the first insulating film 210 to be used as an etching mask. Then, the photoresist pattern 211
Is removed.

Next, as shown in FIG. 3C, the first insulation
The contact surface (source / drain region 25) is covered by anisotropically etching the barrier metal film 29 using the barrier metal protector 210 ′ of the film 210 as a mask and the cap gate silicon oxide 24 as an etching stop layer. Form a barrier metal contact 29 '.

Next, the barrier metal contact portion 29 'of the barrier metal 29 is arranged inside the small hole, that is, on the source / drain junction 25 and on the side surface of the spacer 26. Here, the bottom of the barrier metal contact 29 ′ covers the surface of the source / drain junction 25 very large, but is protected by the sidewall spacer 26.

Thus, the overcoating on the source / drain junction 25 causes the barrier metal contact to isolate the silicon from the metal interconnect, so that between the metal interconnect and the semiconductor contact (which will be formed in a later step). Contact is protected from the "spiking" phenomenon.

Alternatively, the barrier metal contact portion 29 'of the barrier metal 29 can be formed by simultaneously etching the first insulating film 210 and the barrier metal 29.

As shown in FIG. 3D, the cap gate silicon oxide 24, the side wall spacer 26, the barrier metal contact portion 2 are formed.
The second insulating film 212 is formed on the 9 ′ and the first insulating film 210 and on the side surface.
Deposit. As the material of the second insulating film 212, a material having etching selectivity such as silicon nitride or polyimide is used.

Next, as shown in FIG. 3E, a third cell insulation film 27 is formed on the second cell insulation film 212 after a general cell forming process is performed. Here, the general cell forming process includes forming a bit line, forming a capacitor, and planarizing an insulating film.

Next, as shown in (F) of the figure, the third insulating film 27 is anisotropically etched until the second insulating film is exposed, and the barrier metal contact portion 29 'is used as an etching stop layer. By etching the second insulating film 212 and the first insulating film 210, the contact hole 28 is formed on the contact surface included in the bottom surface of the barrier metal contact portion 29 ′ of the source / drain junction 25. The etching of the first insulating film is preferably wet etching.

[0029]

As described above, according to the present invention,
Even if the aspect ratio is 2 or more, by forming a barrier metal on the contact surface and improving the integrity of the barrier metal at the bottom of the contact hole, the metal wiring and the source can be improved.
It is possible to prevent instability of the integrity of the barrier metal on the contact surface between the / drain junction and the contact characteristics of the metal wiring and the reliability of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device for explaining a method for forming metal wiring of a semiconductor device according to the present invention.

FIG. 2 is a partial cross-sectional view of a semiconductor device (following FIG. 1) for explaining a method for forming metal wiring of a semiconductor device according to the present invention.

FIG. 3 is a partial cross-sectional view of a semiconductor device for explaining a conventional method of forming a contact hole for metal wiring of the semiconductor device.

[Explanation of symbols]

11, 21 ... Semiconductor substrate, 12, 22 ... Gate oxide film , 13, 23,
13 '... Gate polysilicon, 14, 24 ... Gap oxide film , 1
5, 25 ... Junction, 16, 26 ... Sidewall oxide film , 17, 27 ... Insulation
Film, 18, 28 ... contact hole 19, 29 ... barrier metal, 210 ... first insulation layer, 19 '... defective portion, 211 ... photoresist, 212 ... second insulating film.

Continuation of front page (56) Reference JP-A-4-352356 (JP, A) JP-A-1-39749 (JP, A) JP-A-4-256358 (JP, A) JP-A-3-1559 (JP , A) JP-A-4-264720 (JP, A) JP-A-1-175245 (JP, A) JP-A-4-134858 (JP, A)

Claims (11)

(57) [Claims] 1. A contact characterized by including the following steps:
Method of forming towhole. (A) A first insulating film, a polysilicon film, a capacitor on the semiconductor substrate.
Step of sequentially stacking a gate oxide film, (B) To form the first contact portion, the first insulating film and the polysilicon
Selective etching of con-film and cap gate oxide film
Process, (C) A step of forming an insulating film side wall on the side surface of the first contact portion, (D) A barrier metal is formed on the cap gate oxide film and the first contact portion.
A step of forming a film, (E) On the barrier metal film of the first contact part, the barrier metal film
Forming the protector, (F) Barrier metal protector is used as a mask.
A step of etching the Tal film, (G) On barrier metal protector and cap gate oxide film
Forming a second insulating film on the (H) a step of forming a third insulating film on the second insulating film, (I) In order to expose the barrier metal film of the first contact portion,
The third insulating film, the second insulating film, and the barrier film corresponding to one contact portion.
Etch the tal protector to form the second contact
Process. 2. A contact, comprising the following steps:
Method of forming towhole. (B) Gate oxide film on the semiconductor substrate, polysilicon for gate
A step of sequentially depositing a cap film and a cap gate oxide film, (B) In order to form the gate electrode pattern, photolithography
Using the Luffy method, the gate oxide film, polysilicon film, and
A process to expose the substrate by etching the cap gate.
、、 (C) Exposure of semiconductor substrate by ion implantation and thermal diffusion
Sauce / dray in part Process of forming a junction, (D) Side of gate electrode and part of source / drain junction
Forming an oxide film side wall spacer on the region, (E) Cap gate oxide film, source / drain junction, acid
Depositing a barrier metal film on the oxide film sidewall spacer, (F) a step of depositing a first insulating film on the barrier metal film, (G) The first insulating film is a barrier film in the source / drain junction region.
The photolithography method is used so that the Ta film is sufficiently covered.
Etch the first insulating film using
The step of forming the tector, (H) Using the barrier metal protector as a mask,
A step of etching the Tal film, (B) Barrier metal protector and cap gate oxide film
Forming a second insulating film on the (E) A step of forming a third insulating film on the second insulating film, (L) Exposing the barrier metal in the source / drain junction area
The third insulation layer corresponding to the source / drain junction region.
Etching the edge film, second insulating film, and barrier metal protector
And forming a contact portion. 3. A silicide is used as the barrier metal.
The shape of the contact hole according to claim 2, wherein
How to do it. 4. The second insulating film is made of silicon nitride.
The shape of the contact hole according to claim 2, wherein
How to do it. 5. The second insulating film is made of polyimide.
The formation of the contact hole according to claim 2,
Method. 6. The barrier metal is formed by sputtering.
Contractor characterized by barrier metal deposited by
The method for forming a contact hole according to claim 2. 7. The cell producing process comprises the following steps.
The formation of the contact hole according to claim 2,
Method. Forming a bit line, A step of forming a capacitor, A step of depositing and planarizing an insulating film. 8. The barrier metal is Ti, TiN, TiW, MoSi
O ₂ 3. The method according to claim 2, characterized in that
Contact hole formation method. 9. In the step (l) above, before the contact portion is formed.
The second and third insulating films are flattened.
Item 2. A method of forming a contact hole according to Item 2. 10. In the step (e), the contact portion is formed.
The process according to claim 2, wherein the process includes the following steps.
Method of forming contact hole. The second insulating film is exposed
Up to the step of anisotropically etching the third insulating film,
Second insulation using the ametal layer as an etching stop layer
Etching the film and the via metal protector. 11. A second insulating film and a barrier metal protector.
The wet etching of the
The method of forming a contact hole according to claim 10.
Law.