JP2548180B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for inputting image data and storing the image data in a storage unit at a designated reduction ratio. Is.

2. Description of the Related Art As a conventional image scaling technique, a pixel clock used when writing image data to a temporary storage device (hereinafter referred to as a memory) and a pixel clock used when reading image data from the memory are set according to the magnification. There is known a technique in which the image is reduced or enlarged according to the relative change. That is, for example, the image can be reduced by thinning and reducing the number of pixel clocks when writing to the memory, and the image can be enlarged by reducing the number of pixel clocks when reading from the memory. You can

For example, the case of reducing the image to 4/5 times
A brief description will be given with reference to the drawings. In FIG. 4, a is a pixel clock at the time of writing and c is pixel data. In order to reduce the size to 4/5 times, the writing pixel clock may be thinned out by one clock every five clocks, so that the pixel clock as shown in FIG. However, if the data is written in the memory as it is, the image data at the point where the pixel clock is thinned becomes discontinuous and unsightly. In order to avoid this discontinuity of data, it is necessary to correct several pixels before and after the thinned pixel. As a circuit therefor, there is a circuit as shown in FIG. 5, for example. In FIG. 5, reference numerals 50 and 51 denote delay circuits which delay the data by the time of one clock. Therefore, the current pixel data is input to the multiplier 52, the pixel data one clock before is input to the multiplier 53, and the pixel data two clocks before is input to the multiplier 54. The multipliers 52-54 multiply the input signals by the coefficients x, y, z set by the coefficient control circuit 56 and output the multiplied signals, and the multipliers 52-54
The output signals of are added by the adder 55 and output. Also,
Coefficients x to z set in the multipliers 52 to 54 by the coefficient control circuit 56
Are chosen to satisfy the relationship x + y + z = 1. Then, by continuously changing the coefficients x to z between the thinned-out point and the next thinned-out point, it is possible to absorb the distortion due to the discontinuity of the image data.

Although the above description has been made in the horizontal direction, the same reduction is performed in the vertical direction. That is, for example, in the case of reducing to 4/5 times, the line to be written is thinned out by writing one line for every five lines, but the image in the thinned line is unsightly if it is left as it is. It is necessary to correct several lines in the same way as in the horizontal direction.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above configuration, a circuit for thinning out and a circuit for correction are necessary for both horizontal reduction and vertical reduction, and a high-speed arithmetic processing circuit is required. However, there is a problem in that the circuit becomes complicated and the circuit becomes complicated.

In view of the above point, the present invention has an object to provide an image processing apparatus capable of performing smooth reduction in a horizontal direction without correcting pixel data, with a simple circuit configuration.

Means for Solving the Problems The present invention operates with a two-phase clock generation circuit for generating two-phase clocks, a switching circuit for switching the two-phase clocks at a predetermined timing, and a clock switched by the switching circuit. The image processing apparatus includes an A / D conversion circuit for performing the above operation, and a unit that writes the data from the A / D conversion circuit into the memory at the switched clock.

The present invention has the above-described configuration, and when only image data is not reduced, only the first clock of the two phases is
When the reduction is performed by adding to the A / D conversion circuit and the memory, the first clock is added to the A / D conversion circuit and the memory during the period when the clock is not thinned, By adding the second clock to the A / D conversion circuit and the memory only during the period after the clock, two clocks of the timing to be thinned out of the first clock are replaced with one clock of the second clock. Since the clock is added to the A / D conversion circuit and the memory, smooth reduction can be performed without correcting the pixel data.

Embodiment FIG. 1 shows an example of a horizontal processing circuit in an image data writing circuit according to an embodiment of the present invention.
1 / (N + 1) times and N / (N + 1) times (N is a positive integer) can be reduced. In FIG. 1, reference numeral 18 is a vertical reduction processing circuit. This vertical direction reduction processing circuit may be the same as the conventional one, and therefore its explanation is omitted. The decode value setting input 1 is an input for setting the above N in the decoders 3 and 4, and the magnification switching input 2 sets the reduction magnification to either 1 / (N + 1) times or N / (N + 1) times. This is an input for switching. Also,
The outputs of the decoders 3 and 4 are input to the synchronous reset terminals of the counters 5 and 6, respectively, and when the count value of the counters 5 and 6 reaches the set value N, the count value is reset to 0 at the next rising edge of the clock. . FIG. 2 shows the operation waveforms of the respective parts of FIG. 1 in the case of N = 4 as an example.
The operation of the circuit shown in FIG. 1 will be described below with reference to FIG.

FIG. 2A shows a clock input to the two-phase clock generation circuit 7, which is a clock having a frequency twice as high as the write clock when writing to the memory without reduction. The two-phase clock generation circuit 7 generates two-phase clocks as shown in b and c of FIG. 2 and uses them as clock signals for the counters 5 and 6, respectively. Therefore, the count value of the counter 5 is N = 4
In the case of, the result is as shown in FIG. 2d, and the count value of the counter 6 is like h. The output of the decoder 8 becomes High level when the decode value of the counter 5 is 1, and
become that way. The output of the decoder 4 is at a high level when the count value of the counter 6 is N, so that when N = 4, it becomes as shown in FIG. Also, the inverting circuits 9 and 10 have 2
Since signals such as b and c generated by the phase clock generating circuit 7 are respectively input, the output signals are f and f, respectively.
It becomes like j and is added to the latch circuits 11 and 12. Since the latch circuits 11 and 12 latch the input signals e and i at the rising timing of the clocks f and j, their outputs are g and k, respectively.
become that way. Then, these two signals are input to the flip-flop 13, and the output of the flip-flop 13 is the second
As shown in FIG. 1, the signal at g rises to High level, and the signal at k rises to Low level. In the switching circuit 14, the signal from the flip-flop 13 is Hi.
When it is gh level, it switches to H side, and when it is Low level, it is L
It is a switch circuit that switches to the ow side, and 2 on the H side.
The clock b generated by the phase clock generation circuit 7 is added via the switching circuit 15, and the clock c is added to the L side. Therefore, when the switching circuit 15 is switched to the A side, that is, when the reduction ratio is designated N / (N + 1) times, the clock b is when the signal 1 is at the high level, and the clock c is when the signal 1 is at the low level. , The signal is output from the switching circuit 14, so that a signal as shown in FIG. As is clear from this figure, the number of pulses of the signal m is 4/5 times the number of pulses of the clock b or c. Further, when the switching circuit 15 is switched to the B side, that is, as the reduction ratio,
When 1 / (N + 1) times is specified, the output of the switching circuit 15 is always at the low level, so the output of the switching circuit 14 is at the low level when the signal 1 is at the high level, and the signal 1 is at the low level.
At the time of the level, the clock c is output and becomes a signal as shown in FIG. The pulse intervals of the signal n are equal, and the pulse number is 1/5 times the pulse number of the clock b or c. As described above, the switching circuit 14 outputs the 4/5 × reduction clock m or the 1/5 × reduction clock n, which is added to the A / D conversion circuit 16 and the memory 17. A / D conversion circuit 16
Then, the reduction clock is used to convert the input signal into a digital signal, which is supplied to the memory 17. In memory 17,
Data from the A / D conversion circuit 16 is written by using this reduction clock as a write clock. Therefore, the input signal is written in the memory 17 after being reduced by 4/5 times or 1/5 times.

FIG. 3 shows operation waveforms of each part in FIG. 1 when the decode value N is 3. FIGS. 3a-1 show the waveforms a-1 of FIG. 1, respectively. The output signal of the switching circuit 14 of FIG. 1 is shown in FIG. 3m when the switching circuit 15 is switched to the A side. When the switching circuit 15 is switched to the B side, it becomes as shown in FIG. That is, when the switching circuit 15 is switched to the A side by the magnification switching input 2, the switching circuit 14 outputs the 3 / 4-fold reduction clock m, and when the switching circuit 15 is switched to the B side, the switching circuit 14 outputs. A 1/4 reduction clock n is output. Then, this clock is used as the clock of the A / D conversion circuit 16 and the write clock to the memory 17, and the input signal to the memory 17 is 3/4.
Written after being reduced by a factor of 2 or 1/4.

As described above, in the present embodiment, the first clock is normally output from the two-phase clocks, and every Nth first clock, that clock and the next clock (2 clocks) are output as the second clock. By switching to the clock of 1 (1 clock), the clock with N / (N + 1) times the number of clocks of the original 1st clock is generated and used as the clock for A / D conversion and the write clock to the memory. By doing so, the input image can be smoothly reduced by N / (N + 1) times and written in the memory. Further, by simply stopping the output of the first clock with the same configuration, 1 / (N + 1) times reduction can be performed. Therefore, these N / (N
By using the reduction mode of +1) times and the reduction mode of 1 / (N + 1) times, smooth reduction can be performed over a wide range.

In this embodiment, every Nth first clock, the clock and the next clock are switched to the second clock. However, the Nth clock is not particularly limited to every Nth clock. It may be more irregular, such as alternating (N + 1) intervals or performing a more complicated pattern.

As described above, according to the present invention, smooth reduction processing in the horizontal direction can be realized by an extremely simple circuit without performing pixel correction calculation or the like. Therefore, the circuit scale of the entire device Can be made small, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an image data writing circuit of an image processing apparatus according to an embodiment of the present invention, FIGS. 2 and 3 are timing charts showing waveforms of respective parts in FIG. 1, and FIG. 4 is a conventional image. FIG. 5 is a timing chart for explaining the reduction processing of the processing device, and FIG. 5 is a block diagram showing an example of a pixel data correction circuit in the conventional image processing device. 5,6 ... Counter, 7 ... 2-phase clock generator, 14,15
...... Switching circuit, 16 …… A / D conversion circuit, 17 …… Memory.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Kada 1006 Kadoma, Kadoma City Matsushita Electric Industrial Co., Ltd. (56) References JP 59-119965 (JP, A) JP 61-262360 (JP) , A)

Claims (1)

(57) [Claims] 1. A two-phase clock generating circuit for generating a two-phase clock, and a switching circuit for switching between a first clock and a second clock generated by the two-phase clock generating circuit at a predetermined timing. , A / D that A / D converts the image input signal with the clock switched by the switching circuit
A conversion circuit and means for storing data from the A / D conversion circuit in the temporary storage device at the switched clock are provided, and the first signal is stored when the image signal is stored in the temporary storage device without being reduced. When the image signal is reduced and stored in the temporary storage device by setting only the clock of the first clock, the predetermined two pulses of the first clock are switched to the one pulse of the second clock according to the reduction ratio. An image processing device characterized by the above.