JP2548117B2 - Video signal processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a video signal processing device used in a video detection circuit of a satellite broadcasting receiver.

2. Description of the Related Art Conventionally, there have been the following video signal processing devices.

(1) The characteristics of the detection circuit for FM video signals such as the PLL method were improved, and the occurrence of white peak and black peak noise was alleviated even where the C / N value had deteriorated.

(2) The bandwidth of the IF and the detection circuit was narrowed to reduce noise generation.

(3) A combination of (1) and (2) above.

(4) No measures were taken to reduce white peak or black peak noise due to local deviation of LNB.

Problems to be Solved by the Invention However, the above-described configuration has the following problems.

That is, in the above (1), the C / N value is limited in relation to the bandwidth, and the generated noise cannot be reduced. Also,
In the above (2), the signal transmission characteristics (DG, DP, etc.) deteriorate. Further, in the above (4), white peak and black peak noises are generated and increased due to local deviation of LNB.

The present invention solves the above-mentioned problems, and an object of the present invention is to provide a video signal processing device capable of reducing noise even when white peak or black peak noise occurs.

Means for Solving Problems The present invention provides a counter for counting white or black peaks, and a white or black peak signal at an intermediate value of video signals when the count number of the counter exceeds a certain value within a certain period of time. The IF and the detection circuit have a band that is optimally kept from the viewpoint of signal transmission characteristics, and is clamped to an intermediate value of the video signal at the level of the generated noise.

Action The present invention has the above-described configuration, and thus white peak or black peak noise in the detection output appears as a pulse,
Counting the number, for example, when there are more than n in one field, the clump circuit is operated and both the white peak and the black peak are clamped to the gray level, that is, the intermediate value of the video signal. In that case, the noise will be inconspicuous.

Embodiment FIG. 1 shows a main part of a video signal processing apparatus according to an embodiment of the present invention, FIG. 2 shows an example of a screen according to this embodiment, and FIG. 3 shows an entire satellite broadcast receiver incorporating this embodiment. Composition, fourth
The figure shows the change in the signal waveform of this embodiment.

In FIG. 3, reference numeral 1 is a parabolic antenna that receives radio waves of satellite broadcasting, and 2 is an ultrahigh-frequency signal (for example, radio waves in the 12 GHz band and 4 GHz band) that is received by the parabolic antenna 1 in the 1 GHz band (here, 950 MHz to 1450 MHz is considered). It is a low noise converter (LNB) that converts to radio waves. Reference numeral 3 denotes a pillar of the parabolic antenna 1, and a mechanism for rotating the parabolic antenna 1 is attached when receiving radio waves from a plurality of satellites. 4 is a cable that has good high-frequency characteristics and does not attenuate signals in the 1 GHz band. The above components are installed outdoors. A satellite broadcast receiver 5 is also called an IDU (Indoor Unit). 6 is a tuner called 2nd mixer,
A signal of one channel in the 1 GHz band signal is converted to an IF frequency (for example, 402.75 MHz or 510 MHz). 7 is IF
Amplifier, 8 is an FM wideband detector, for example, bandwidth 30MHz
It has a good linearity characteristic over the above. Reference numeral 9 is a voice FM detector for demodulating voice. In the case of PCM, PCM demodulation, FM
In case of, FM detection is performed. Reference numeral 14 is a gray clamp circuit that clamps the white peak and black peak noise signals to a gray level. If this is a simple buffer amplifier, it will have the same configuration as a normal IDU. Reference numeral 11 is a base frequency band, and a buffer amplifier for outputting video and audio signals, and 10 is an RF converter for converting the outputs of the audio FM detector 9 and the gray clamp circuit 14 into RF signal outputs. The RF output of this RF converter 10 is VHF
This is connected to the antenna input of a normal television receiver 13 with a VHF band cable 12 to obtain an image as shown in FIG. 2 (A). When C / N deteriorates in the transmission system between the parabolic antenna 1 to the FM detector 8, noise N of white peak and black peak appears on the screen as shown in FIG.
If the local oscillator in LNB2 shifts, even if the C / N does not deteriorate, only white peak noise or black peak noise appears and it becomes unsightly. In the present embodiment, the above phenomenon is greatly reduced as shown in FIG.

The specific configuration of the gray clamp circuit 14 is shown in FIG.
This is indicated by the block. 8 is an FM detector, 15 is a pedestal clamp circuit, and a pedestal clamp pulse is formed by a clamp pulse creating circuit 18. Reference numeral 16 is a sync separation circuit, and its output synchronizes with the horizontal AFC circuit 17. 19 is a sync separation circuit 16
A vertical sync pulse generation circuit that integrates the output of to obtain a vertical sync pulse. The clamp pulse creation circuit 18 is a horizontal AFC
The output of the circuit 17 is appropriately shaped and delayed to form a pedestal clamp pulse having a phase as shown in FIG. 4 (B). The counter gate 20 forms a pulse which becomes low (or high) only during the vertical blanking period (VBL) or more by the output of the vertical synchronizing pulse generating circuit 19 and the output of the horizontal AFC circuit 17, as shown in φ ₃ in FIG. To do. The counter gate 20 can be easily configured by a counter and a flip-flop. This is because VBL inhibits the pedestal clamp of the pedestal clamp circuit 15, and the operation of the pulse counter 27 is stopped during VBL.
In FIG. 5, φ ₁ is a video signal viewed in vertical synchronization, and t ₀ ~
t ₃ is the vertical blanking period, and the 3H-width diagonal line portion starting from t _{1 of} φ ₁ is the vertical sync pulse. By integrating this, φ _{2 in} FIG. 5 is obtained as the output of the vertical sync pulse generation circuit 19. To be In this way, the signal of FIG. 4 (A) is pedestal clamped by the pedestal clamp circuit 15 between t ₃ and t ₀ shown in FIG. At this time, since a color burst is often superimposed on the pedestal portion, it goes without saying that so-called soft clamp is performed so as not to affect the burst signal during clamping. Fig. 4 (A),
In (B), for simplicity, the pedestal level V _P and the black level V _B are selected to be equal. Therefore, when the black level V _B is clamped to a constant level, the detection output value becomes constant, and the white level V _W also becomes constant. The buffer amplifier 21 is
It is DC coupled. 22 is a black peak detection circuit, and here is the fourth
A noise signal having a black level higher than V _{B in} FIG. A is detected, the level is converted by the next pulse shaping circuit 23, and shaped into a pulse. The output of the pulse shaping circuit 23 is shown in FIG. On the other hand, the white peak detection circuit 24 detects a noise signal exceeding V _W in FIG. 4 (A), and the pulse shaping circuit 25 converts the level of the noise signal to shape it into a pulse. The output of the pulse shaping circuit 25 is shown in FIG. 4C. When the logical sum of FIG. 4 (C) and (D) is formed by the OR gate 26, the output of the OR gate 26 becomes FIG. 4 (E). And in the next stage of the pulse counter, as described above, counting every field the output of the OR gate 26 between the Figure 5 t ₃ ~t _0. If the pulse counter 27 is configured as shown in FIG.
27C counts only between t ₃ and t ₀ because φ ₃ is at a low level. As the counter 27C, for example, a TTL binary counter
SN74LS93 is considered. The field counter 27R counts the output of the vertical sync pulse generation circuit 19,
A reset pulse is generated once every 96 fields (about 1.1 minutes) to reset the flip-flop 27F. When 16 or more noise pulses are applied to the counter 27C from the OR gate 26 during one field, the 2 ³ output of the counter 27C changes from high level "H" to low level "L".
This change is transmitted to the flip-flop 27F and the T terminal, the flip-flop 27F is set, and Q is "H",
Becomes "L", the analog gate 32A is cut off, and the analog gate 32B becomes conductive. The counter 27C is cleared between t ₀ and t ₃ every field, so 15
When the number of noise pulses is less than the number, the flip-flop 27F is not set, and the output of the clamp circuit 29 is the buffer amplifier.
Not transmitted to 32C. Approximately every minute, there is a time when most or one partial flip-flop 27F of one field is not set. However, if it is about one field, there is no practical problem. Also, when the satellites are switched, there is a delay of about 1 minute until the operation starts, but when the C / N improves, there is no problem because the output of the clamp circuit 29 is the same as the output of the delay 31.
When C / N becomes worse, OR gate 26 within 1 field
Since the output of 16 is more than 16 and the flip-flop 27F is set and the output of the clamp circuit 29 is transmitted to the buffer amplifier 32C, there is no problem even if the flip-flop 27F is reset about every one minute. The buffer amplifier 32C is a buffer for amplifying the output of the analog gate 32A or the analog gate 32B, and the output of the amplifier 32C is transmitted to the RF converter 10 and the output buffer 11 shown in FIG. On the other hand, in FIG.
Reference numeral 30 denotes a buffer amplifier, the output of which is supplied to the clamp circuit 29, and the clamp pulse generation circuit 28 generates a high-speed clamp pulse at the output of the OR gate 26, that is, the pulse portion of FIG. Supply it to 29 and clamp the part of the white peak and the black peak, and set it to the gray level. The output of the clamp circuit 29 is as shown in FIG. 4 (B), and noise is not noticeable on the screen as shown in FIG. 2 (B). In the above description, from the buffer amplifier 21 to the clamp pulse generating circuit 28
I think that the transmission delay time up to and the delay time in the buffer amplifier 30 are the same, but when the output of the buffer amplifier 30 is ahead, a delay circuit is required between the buffer amplifier 30 and the clamp circuit 29. It goes without saying that Reference numeral 31 is a delay circuit that compensates for the delay in the clamp circuit 29, and there is no problem even if it is omitted. However, there are alternating fields with and without noise, and the output of field counter 27R is 6
When it is generated every 0 fields, it is necessary to remove jitter. With the configuration as described above, the white peak and black peak noise can be clamped to the gray level.

Effects of the Invention As described above, the present invention can exert the following excellent effects.

(1) When a signal with bad C / N is received, noise can be made inconspicuous by clamping the white peak and black peak noise signals to a gray level.

(2) Even when white and black peak noise is generated due to the local deviation of the LNB, the noise can be made inconspicuous by clamping to the gray level.

(3) Since the bandwidth of IF and FM detection is not changed, there is no deterioration of signal characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a video signal processing device according to an embodiment of the present invention, and FIGS. 2 (A) and 2 (B) are front views showing screen comparison when the present invention is applied and when it is not applied, 3 is a block diagram of a satellite broadcast receiving system to which the present invention is applied, FIGS. 4 (A) to 4 (E) are waveform diagrams for explaining the operation of the present invention, and FIG. 5 is for explaining the operation of the present invention. Waveform diagram of
FIG. 6 is a block diagram of an essential part for explaining the operation of the present invention. 22 ... Black peak detection circuit, 23 ... Pulse shaping circuit, 24 ...
… White peak detection circuit, 25 …… Pulse shaping circuit, 26 …… OR gate, 27 …… Pulse counter, 28 …… Clamp pulse generation circuit, 29 …… Clamp circuit, 31 …… Delay circuit, 32… … Signal switching circuit.

Claims (1)

(57) [Claims] 1. In a device for detecting and amplifying a frequency-modulated video signal, a first waveform shaping circuit for shaping a white peak impulse noise signal generated during detection output into a pulse waveform, and during detection output. A second waveform shaping circuit for shaping a black peak impulsive noise signal generated in a pulse waveform into a pulse waveform, a pulse counter for counting pulse outputs of the first and second waveform shaping circuits for a certain period, and the first or The clamp pulse generating circuit formed by the pulse output of the second waveform shaping circuit and the detection output of the video signal are supplied, and the impulsive noise signal of the white peak and the black peak in the detection output is supplied to the clamp pulse generating circuit. A clamp circuit for clamping the detection output of the video signal at an intermediate level by the output of, a delay circuit for delaying the detection output of the video signal, An analog AND gate for inputting a signal from the ramp circuit and a signal from the delay circuit respectively is provided, and when the count value of the pulse counter reaches or exceeds a predetermined numerical value within a predetermined time, the delay circuit outputs The video signal processing device is characterized in that the output from the clump circuit is derived from the analog and gate instead of the output from.