KR100269366B1 - Apparatus for dc removal of digital tv - Google Patents

Abstract

PURPOSE: An apparatus for removing a DC(Direct Current) of a digital television is provided to calculate a DC value and to remove DC elements included in signals transmitted by a VSB(Vertical Sideband) method. CONSTITUTION: If analog data converted into digital data are inputted, a DC(Direct Current) remover detects a data section from the inputted data, and subtracts a DC value calculated via the data section from the inputted data to remove DC elements. A DC calculator(23) adds an output of the DC remover to a fed-back accumulation value, and makes an upper bit area value equal to the DC value to output the bit area value to the DC remover, then feeds back an entire bit area value to be added.

Description

DC removal device of digital television {APPARATUS FOR DC REMOVAL OF DIGITAL TV}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for receiving a digital TV broadcast signal such as a high definition television (HDTV), and in particular, a direct current (DC) component included in a signal transmitted in a residual side band (VSB) method. It relates to a device for removing it.

Since the launch of color TV broadcasting in the United States in the past 54 years, TV has played a pivotal role as the most intimate source of information and entertainment for people, and from a technical point of view, TV has been used to provide the best picture quality on the largest screen. It was a continuation. However, as household color TVs get bigger and bigger, the home appliance industry faces some technical limitations. That is, it is difficult to realize a clear screen on a 40-inch or larger TV by the existing analog broadcasting and receiver standards, and it is not suitable for home use because it is too large when using a CRT. In order to overcome these limitations, the HDTV development project started under the leadership of the global consumer electronics industry and broadcasting industry since the 1960s, is commercialized or will be commercialized in Korea, the US, Europe and Asia.

These HDTVs are trying to standardize their own broadcasting methods and standards in the United States, Europe and Japan. In the United States, the transmission format adopts the VSB method proposed by Zenith in the United States, the compression format adopts MPEG (MPEG) for video compression, and Dolby AC-3 for audio compression. It is specified to be compatible with the method.

That is, the transmitting side, such as a broadcasting station, passes a mapper that changes to a desired power level before transmitting a signal. In the case of 8 VSB for terrestrial broadcasting, the output level of the mapper is 8 symbol values (amplitude level), that is,- 168, -120, -72, -24, 24, 72, 120, 168. In addition, the mapper forcibly generates and inserts 4 symbol data segment sync signals for every 832 symbols by appointment, and creates and inserts a field sync signal at 313 data segment positions. 0, 0, 1, mapper output level is '120' when the synchronization is '1', '-120' when the '0'. Herein, the data segment synchronization signal corresponds to a horizontal synchronization signal in an NTSC signal, and the field synchronization signal corresponds to a vertical synchronization signal.

The mapper adds a constant constant to the output of the entire mapper and outputs the data as 10 bits. A constant constant added to the output of the mapper is DC, and is inserted to accurately demodulate a signal at the receiver. At this time, the frequency band of the data output from the mapper is a base band, the DC in the base band is changed to a carrier component in the IF, RF converter. That is, the output of the mapper is separated into I and Q signals of base bands having a phase difference of 90 degrees through the complex filter. The I signal is affected by DC and the Q signal is not affected by DC. At this point, IF conversion unit in the I, each of cos and sin the form of a sine wave the center as to the IF signal output by the IF signal of 6MHz bandwidth, and the RF converter comprises: an intermediate frequency 44MHz by Durham each other after multiplying to the Q signal cosW _R Multiply the sinusoidal wave by the t-shape to convert it into the high frequency of the desired channel, and then send it out in space through the antenna. Here, the W _R value varies depending on how many channels are to send a signal. In the base band, the DC is converted into a carrier of 46.69 MHz in the IF converter, and is converted into a carrier suitable for a predetermined channel in the RF band. In this case, since the frequency used for HDTV broadcasting uses the same frequency band as that of the current NTSC TV broadcasting, the power of the carrier is reduced and transmitted in order not to affect NTSC broadcasting. Here, a pilot is used to reduce the power of the carrier while keeping the frequency as it is. That is, the signal transmitted together with the RF signal is not a carrier but is exactly a pilot signal.

On the other hand, when a receiving side such as a television receives a VSB modulated RF signal through an antenna as shown in FIG. 1, the tuner 11 selects a frequency of a desired channel by tuning and converts it into an IF signal, and then converts it into an IF signal. ) Demodulates the IF signal output from the tuner 11 into I and Q signals of the base band to lock the frequency and phase. That is, the FPLL unit 12 is a circuit in which a frequency tracking loop and a PLL are integrated, and locks a frequency first and then locks a phase when the frequency is locked.

In addition, the FPLL unit 12 demodulates a pilot signal from the I and Q signals of the base band, recovers a carrier using the demodulated pilot signal, and outputs the carrier signal to the voltage controlled oscillator of the FPLL unit 12. . In this case, if the carrier recovery is not performed properly, the FPLL unit 12 malfunctions, and thus the accurate demodulation of the VSB signal is not performed.

The analog / digital (A / D) converter 13 converts the I signal of the FPLL unit 12 into digital data of a predetermined bit (for example, 10 bits). Here, the Q signal is used only for carrier recovery. The synchronization recovery unit 14 restores the data segment synchronization signal, the field synchronization signal, etc., which were inserted at the time of transmission using the digitally converted 10-bit data. These synchronization signals are designed to facilitate the recovery of the received data. When they are detected incorrectly, the recovery of the data is not performed properly, which greatly affects the whole system. The equalization and error correction unit 15 uses the data segment restored in the synchronization recovery unit 14, field synchronization signals as a training signal, linear distortion of amplitude causing interference between symbols, and ghosts generated by reflections from buildings or mountains. After the equalization is performed to correct the error, the error generated through the transmission channel is corrected. The video decoder 16 decodes the equalized and error corrected signal by an MPEG algorithm to make the signal visible to the viewer.

At this time, assuming that the ideal state unaffected by noise or the like during transmission or signal processing and 30 is inserted into the DC value at the transmitting side, the output of the A / D converter 13 has 8 symbol values ( Amplitude level), i.e., -138, -90, -42, 6, 54, 102, 150, 198, and the data segment synchronization signal is 150, -90, -90, 150. This is different from the original amplitude level. Therefore, if the received data is demodulated using this value as it is, an error occurs and the correct restoration of the data cannot be performed.

In order to remove such DC components, a conventional method of using only a field synchronization signal (ie, a vertical synchronization signal) among input signals is common. However, since a DC value is updated and removed once per period of the field synchronization signal, processing speed becomes slow. When the integrated circuit (IC) is integrated, there is a problem in that the IC size increases and the cost increases. In addition, the DC value should be calculated within a short time during the field synchronization period, and if the field synchronization signal is not properly detected due to noise or the like, the DC value cannot be properly calculated, which causes inaccurate DC removal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a DC removal device of a digital TV that accurately removes the DC component included in the input signal.

Another object of the present invention is to provide a DC removing device of a digital TV that calculates and removes a DC value in a data section.

1 is a block diagram of a typical HDTV receiver

2 is a block diagram of a DC removing device according to the present invention;

FIG. 3 is a graph showing an example of a time at which the average value of DC in FIG. 2 is decreased.

Explanation of symbols for main parts of the drawings

21: Subtractor 22,23-3: Limiter

23: DC calculation unit 23-1: the adder

23-2,24: flip flop

In order to achieve the above object, a DC removing apparatus of a digital TV according to the present invention includes a DC removing unit for subtracting a calculated DC value from data input when an analog signal output from a tuner is converted into digital and inputted, and the DC After the output of the remover and the previous value fed back are added, the value of the predetermined upper bit region is output to the DC remover, and the value of the entire bit region is configured as a DC calculator which feeds back for addition.

The DC calculator has a precision of 25 bits, and outputs the DC value to the DC remover using the upper 10 bits as the calculated DC value.

Hereinafter, the embodiment of the present invention will be further described with reference to the features of the present invention.

In general, the data changes at every moment, but the DC inserted here always has a constant value. However, since the DC value is input through a channel having various noises, the instantaneous value of DC included in the input signal does not always have the same value. Therefore, it is difficult to know the DC value directly from the instantaneous value of the input data. To this end, the present invention integrates the input data for a predetermined time, finds the DC value, and subtracts the DC value from the input signal, thereby removing the DC inserted during transmission. For example, although the instantaneous value of DC is not always the same value, the instantaneous value of DC can be integrated to know the DC value included in the input signal.

That is, the average of the data before the DC is inserted at the transmitting side is '0'. For example, in the absence of DC, the data is randomly inputted from -168 to 168. Therefore, if the integration is continued while accumulating the data for a predetermined time, the average value of the data is nearly zero. In this way, when the input data is integrated for a predetermined time, the average of the remaining data components except DC is '0', so that influence by the data is eliminated. In addition, the influence on the conversion of the instantaneous value of DC is also eliminated. At this time, the remaining information is the DC inserted in the transmitter, and if this DC value is removed from the input signal, the signal is finally a signal without DC. That is, since the DC is removed by subtracting the integral and the integral value from the input signal in the data section using the property of '0', the problem of the prior art, for example, the processing speed, is solved. In addition, the integral value has a precision of 25 bits, and only the value of the predetermined upper bit region is fed back so as to be subtracted from the input signal, thereby solving the problems of the prior art, for example, hardware.

The DC removing device of the digital TV according to the present invention for realizing this is shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2, a subtractor 21 subtracting a DC value calculated from input 10-bit digital data, a limiter 22 that limits the output of the subtractor 21 when it exceeds the limit of 10 bits, which is a data bit, After adding the output data of the limiter 22 and the previous cumulative value, the predetermined 10-bit value is output to the subtractor 21, and at the same time the value of all bits is fed back for the addition DC calculation unit 23, And a flip-flop 24 which aligns the timing of the data output from the limiter 22 and outputs the same for synchronous recovery and equalization.

The DC calculator 23 is a kind of accumulator or integrator, an adder 23-1 that continuously adds the output of the limiter 22 and a previously stored cumulative value, and has a precision of 25 bits to the reset signal. The flip-flop 23-2, which is reset by the adder 23-1, stores the output of the adder 23-1, and if the output of the flip-flop 23-2 exceeds the limit of 25 bits, the value of the upper 10 bits is limited. Is a calculated DC value and is output to the subtractor 21, and a 25-bit value is composed of a limiter 23-3 which feeds back to the adder 23-1.

In the present invention configured as described above, the 10-bit digital data Din [9: 0] output from the A / D converter 13 is input to the subtractor 21. The subtractor 21 subtracts the DC value calculated by the DC calculator 23 from the input data value and outputs it to the limiter 22.

At this time, the digital data and the calculated DC value input to the subtractor 21 each have a precision of 10 bits, and the output of the subtractor 21 has a precision of 11 bits by the subtraction process. Therefore, the limiter 22 limits the upper limit value or the lower limit value among the values of the 10 bit when the 11 bit signal output from the subtractor 21 exceeds the 10 bit limit. For example, if the signal input to the limiter 22 is signed data, values exceeding 512 cannot be represented by 10 bits, so the output is limited to 511, the upper limit of 10 bits, and values exceeding -513 are 10 bits. The output is limited to the lower limit of -512. In this way, the limiter 22 prevents the overflow or underflow of the data output from the subtractor 21. The output of the limiter 22 is output to the DC calculator 23 and to the flip-flop 24. The flip-flop 24 matches the timing difference caused by the gate delay and outputs the same for synchronous recovery.

The DC calculator 23 calculates a DC value from the digital data input through the limiter 22. Since the DC calculator 23 is configured in an infinite loop, it is necessary to first set an initial value. Therefore, when the reset signal initially informs the reset state, the flip-flop 23-2 of the DC calculator 23 is cleared to '0'. This is because the DC value is not known at the beginning of operation so that the input signal is output as it is.

Therefore, since the cumulative value fed back to the adder 23-1 is 0 initially, the input data is output to the flip-flop 23-2 through the adder 23-1 as it is, and the flip-flop 23-2. Is output to the subtractor 21 through the limiter 23-3 in synchronization with the symbol (= clock) and fed back to the adder 23-1.

At this time, the flip-flop 23-2 has a precision of 26 bits. This is to completely eliminate the influence of the data on the calculated DC values. That is, when the integration result is output to the subtractor 21 through the limiter 23-3, only the upper 10 bits are output as the DC value except for the lower 15 bits. Accordingly, the flip-flop 23-2 also serves as a buffer of about 15 bits. That is, data and DC are mixed in the signal output from the first limiter 22 to the adder 23-1 of the DC calculator 23, but the value subtracted from the subtractor 21 must be a pure DC value. By using the bit as a buffer to make the average of the data zero, the influence of the data is eliminated.

For example, assume that the DC value included in the received signal is '30'. At this time, since the flip-flop 23-2 of the DC calculator 23 is initially reset to 0 by the reset signal, the calculated DC value output to the subtractor 21 through the limiter 23-3 is '0'. 'to be. Since the calculated DC value is 0, the subtractor 21 outputs the input 10-bit data to the adder 23-1 of the DC calculator 23 through the limiter 22 as it is. The adder 23-1 outputs the input data to the flip-flop 23-2 as it is because the previous cumulative value fed back is zero. The flip-flop 23-2 operates in synchronization with a symbol, and the upper 10 bits of the output of the flip-flop 23-2 are output to the subtractor 21 through the limiter 23-3, and 25 bits It is fed back to the adder 23-1. In this case, since the upper 10-bit data value is 0, the 10-bit data transmitted is input to the adder 23-1 of the DC calculator 23 through the subtractor 21 and the limiter 22 as it is. The adder 23-1 adds the previous value fed back to the input data value and outputs it to the flip-flop 23-2. The previous value fed back to the adder 23-1 is not zero.

If this process is repeated repeatedly, the data value included in the input signal converges to 0 and only the DC value continues to increase.

Therefore, if the integration operation is continued and the number of symbols is 1093 symbols, the value stored in the flip-flop 23-2 is 30 × 1093 = 32790. If the lower 15 bits are removed from this value, the data value of the upper 10 bits output to the subtractor 21 through the limiter 23-3 becomes '1'. That is, the value divided by 2 ¹⁵ = 32 768 to the value stored in the flip-flop 23-2 is 1. Therefore, the subtractor 21 subtracts the calculated DC value '1' from the next transmitted signal. Therefore, the average of the DC values included in the signal input to the adder 23-1 of the DC calculator 23 through the limiter 22 becomes '29'. At this time, even if the average of the data is not '0', since the value is included in the lower 15 bits, it does not affect the DC value output to the subtractor 21 at all.

When the integration is continuously performed and the time has passed 2223 symbols from the beginning, the value stored in the flip-flop 23-2 becomes 30 × 1093 + 29 × 1130 = 65560. If the lower 15 bits of the value are removed, the DC value output to the subtractor 21 through the limiter 23-3 becomes '0000000010', that is, '2', and the subtracter 21 is applied to the input signal. If the value is removed, the average of the DC values included in the signal input to the adder 23-1 of the DC calculator 23 through the limiter 22 becomes '28'. That is, until the value stored in the flip-flop 23-2 becomes 65536, the DC value output to the subtractor 21 continues to be '1' and thus is included in the signal input to the DC calculator 23. The average value of the DC values continues to be maintained at '29', but when it exceeds 65536, the DC value output to the subtractor 21 is changed to '2' and the average of the DC values included in the signal input to the DC calculator 23. Also changes to '28'.

If the integration process continues, the output of the DC calculation unit 23 becomes '30', and when this value is removed from the subtractor 21, the adder 23 of the DC calculation unit 23 through the limiter 22. The average of the DC value included in the signal input as -1) becomes '0'. This means that the DC value inserted in the transmitter is 30. The adder 23-1 outputs the previous value fed back to the flip-flop 23-2 as the average of the DC value included in the signal output from the limiter 22 is 0, and the flip-flop 23-2. Outputs only the upper 10 bits of data, that is, '30' to the subtractor 21 through the limiter 23-3. Therefore, the DC component does not exist in the 10-bit data Dout [9: 0] that is output for synchronization recovery after timing alignment in the flip-flop 24.

At this time, the average of the DC value included in the signal output from the limiter 22 is reduced from '30' to '29', from '29' to '28', to '28' ... '0' Times n1, n2, n3, ... are shown in FIG. In other words, when 30 × n1 = 32768, the average of DC values changes from '30' to '29', and when 29 × n2 = 32768, it changes from '29' to '28' and when 28 × n3 = 32768, '28' It changes from 'to' 27 '. Therefore, n1 < n2 < n3 ... and, for example, the total time taken to change from '30' to '28' is n1 + n2. When the average value of the DC is 0, the multiplied value becomes 0, so no matter how much time progresses, the output becomes 0 and the average value of the DC remains '0'.

Here, the cumulative data fed back to the adder 23-1 has a precision of 25 bits, and the data input from the limiter 22 to the adder 23-1 has a precision of 10 bits. ) Output has a precision of 26 bits by the addition process, so the limiter 23-3 has a data exceeding the 25-bit limit through the adder 23-1 and the flip-flop 23-2. Write-out data is limited to the upper or lower limit of 25-bit values to prevent overflow or underflow.

Meanwhile, in the present invention, the precision of the flip-flop 23-2 of the DC calculator 23 is set to 25 bits, but this may be changed by the designer, and the calculated DC value output to the subtractor 21 is higher among them. Although limited to 10 bits, this may vary by designer.

As described above, according to the DC removing apparatus of the digital TV according to the present invention, when the input signal is accumulated for a predetermined time, the average of the data becomes '0' and the DC value does not become '0'. By calculating the DC value included in the signal transmitted in the interval, and then subtracting the calculated DC value from the data, the DC component included in the transmitted signal is removed to calculate and remove the DC value for a relatively long time. Calculation and DC elimination is performed, and DC calculation and elimination is performed in the data section, so that the processing speed is increased, and the optimal configuration is realized when IC is integrated with such DC eliminator so that the IC size is smaller and the cost is lowered. There is.

Claims (6)

In the device for removing the DC component inserted at the transmitting side, When the analog data output from the tuner is converted into digital input, the DC removal unit for detecting the data interval from the input data, subtracting the DC value calculated over the detected data interval from the input data to remove the DC component, After adding the output of the DC removing unit and the previous cumulative value fed back, the DC calculating unit outputs the predetermined upper bit region as the calculated DC value to the DC removing unit and feeds back the total bit region for the addition. DC remover, characterized in that configured to include. The method of claim 1, wherein the DC calculation unit An adder for adding an output of the DC removing unit and a previous cumulative value fed back; And storing the output of the adder in synchronization with a symbol and outputting the predetermined upper bit region as a calculated DC value to the DC removing unit and feeding back the total bit region to the adder. DC remover. The method of claim 2, wherein the storage unit The DC removal device having a precision of 25 bits and outputting the value of the upper 10 bits among the calculated DC values to the DC removal unit. The method of claim 2, wherein the storage unit And a limiter for limiting the output of the added value when the output of the added value exceeds the limit of the bit determined by the precision of the storage unit. The method of claim 1, wherein the DC removing unit DC removal device characterized in that it includes a limiter to limit the value of the DC component removed from the input data exceeds the limit of the data bit. When a high frequency (RF) signal is received through an antenna, a tuner selects a frequency of a desired channel by tuning and converts it into an intermediate frequency (IF) signal. An analog / digital conversion unit for demodulating the IF signal output from the tuner into I and Q signals of a baseband, locking the frequency and phase, and converting the IF signal into a digital signal of a predetermined bit; A data section detector for detecting only a data section from the digital data output from the analog / digital converter; A DC removal unit for subtracting a DC value calculated in the data interval detected by the data interval detection unit; After adding the output of the DC removing unit and the previous cumulative value fed back, the DC calculating unit outputs the predetermined upper bit region as the calculated DC value to the DC removing unit and feeds back the total bit region for addition. Wow, A digital data decoding unit for restoring a synchronization signal from the data output from the DC removing unit and decoding the data using the synchronization signal; And a display unit for displaying the decoded data.

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