KR100232145B1 - Apparatus for polarity correction of digital television - Google Patents

Abstract

The present invention relates to a device for determining and correcting polarity of data when demodulating data received by a VSB based on the characteristics of a demodulator. Particularly, a polarity correction unit outputs the digital data as it is or inverted according to a polarity control signal. A segment correlator for determining a shape of a data segment using only sign bits at an output of the polarity correction unit, first and second storage units for sequentially storing a result of the discrimination of the segment correlator, and first and second ones; A comparator for determining whether two outputs of the two storage units are the same; a confidence counter for checking reliability of the output of the comparator; and a polarity correction for generating a polarity control signal according to the output of the confidence counter and the output of the second storage unit; The controller is configured to determine the polarity of the input data and to compensate the polarity according to the determined result. By processing all the information in the digital domain, accurate polarity correction is performed to improve system performance. Also, the pattern of the data segment sync signal is determined using only the sign bits among the input digital data, and the pattern of the data segment sync signal is input. By determining the polarity of the data to be obtained, the circuit can be simplified, the degree of integration is easy, and the IC size can be reduced, thereby reducing the cost.

Description

Polarity correction device of digital television

The present invention relates to a receiving apparatus for receiving a broadcast signal for a digital TV such as a high definition television (HDTV). In particular, if the polarity of the data is inverted due to the characteristics of the demodulator during demodulation of the received broadcast data, It relates to a polarity correction device of a digital TV that is determined and corrected.

Since the launch of color TV broadcasting in the United States in the past 54 years, TV has played a pivotal role as the most intimate source of information and entertainment for people, and from a technical point of view, TV has been used to provide the best picture quality on the largest screen. It was a continuation. However, as household color TVs get bigger and bigger, the home appliance industry faces some technical limitations. That is, it is difficult to realize a clear screen on a 40-inch or larger TV by the existing analog broadcasting and receiver standards, and it is not suitable for home use because it is too large when using a CRT. In order to overcome these limitations, the HDTV development project started under the leadership of the global consumer electronics industry and broadcasting industry since the 1960s, is commercialized or will be commercialized in Korea, the US, Europe and Asia.

These HDTVs are trying to standardize their own broadcasting methods and standards in the United States, Europe and Japan. In the United States, the transmission format adopts the residual sideband (VSB) method proposed by Zenith in the United States, the compression format adopts MPEG (MPEG) for video compression, and Dolby AC-3 for audio compression. The display format is specified to be compatible with existing display methods.

That is, the transmitting side, such as a broadcasting station, passes a mapper that changes to a desired power level before transmitting a signal. In the case of 8 VSB for terrestrial broadcasting, the output level of the mapper is 8 symbol values (amplitude level), that is,- 168, -120, -72, -24, 24, 72, 120, 168. In addition, the mapper forcibly generates and inserts four symbol data segment synchronization signals for every 832 symbols (= 1 data segment), and forcibly creates and inserts a field synchronization signal at 313 data segment positions. The promised form of the signal is logically 1, 0, 0, 1, and the mapper output level is '120' when the sync is '1' and '-120' when the '0'. Herein, the data segment synchronization signal corresponds to a horizontal synchronization signal in an NTSC signal, and the field synchronization signal corresponds to a vertical synchronization signal.

On the other hand, when a receiving side such as a digital TV receives a VSB modulated high frequency (RF) signal as shown in FIG. 1 through an antenna, the tuner 11 selects a frequency of a desired channel by tuning and then an intermediate frequency (IF) signal. The FPLL unit 12 demodulates the IF signal output from the tuner 11 into baseband I and Q signals to lock frequency and phase. That is, the FPLL unit 12 is a circuit in which a frequency tracking loop and a PLL are integrated. First, the frequency is synchronized, and the frequency is synchronized, and the phase is synchronized.

The analog / digital (A / D) converter 13 converts the I signal of the FPLL unit 12 into 10-bit digital data. Here, the Q signal is used only for carrier recovery. The synchronization recovery unit 14 restores the data segment synchronization signal, the field synchronization signal, etc., which were inserted at the time of transmission using the digitally converted 10-bit data. These synchronization signals are designed to facilitate the recovery of the received data. When they are detected incorrectly, the recovery of the data is not performed properly, which greatly affects the whole system. The equalization and error correction unit 15 uses the data segment restored in the synchronization recovery unit 14, field synchronization signals as a training signal, linear distortion of amplitude causing interference between symbols, and ghosts generated by reflections from buildings or mountains. After the equalization is performed to correct the error, the error generated through the transmission channel is corrected. The video decoder 16 decodes the equalized and error corrected signal by an MPEG algorithm to make the signal visible to the viewer.

In this case, synchronization may be performed at a position where the phase of the signal is 0 degrees when demodulating data due to the algorithm characteristic of the FPLL unit 12, or synchronization may be performed at a position of 180 degrees. If the synchronization is made at the position of 0 degrees, there is no problem, but if the synchronization is made at the position of 180 degrees, the polarity of the signal is changed so that the receiver cannot operate normally. That is, the pattern of the data segment synchronization signal of 4 symbols inserted in every data segment is promised to have 1001. If the synchronization phase of the FPLL unit 12 is 0 degrees, it has the form 1001 as shown in FIG. If the synchronous phase of the FPLL unit 12 is 180 degrees, it has a form as shown in FIG. 2B. Therefore, the polarity of the signal must be corrected to correct the polarity of the received signal.

In the past, such polarity correction was performed in the FPLL section 12. However, since the FPLL unit 12 is an analog region using an analog element, polarity correction is inaccurate and degrades the performance of the receiver. In addition, the circuit is complicated, so it is difficult to integrate the integrated circuit (IC), and even if the IC is integrated, the volume becomes large. Therefore, the cost also rises.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a polarity correction apparatus of a digital TV for determining the polarity of the signal and performing all the polarity correction according to the determination result in the digital domain.

Another object of the present invention is to provide a polarity correction apparatus of a digital TV that detects a polarity by detecting a pattern of a data segment synchronizing signal using only code bits of input digital data.

Polarity correction device of the digital TV according to the present invention for achieving the above object, the polarity correction unit for outputting the digital data as it is or inverted in accordance with the polarity control signal, the code information from the output of the polarity correction unit It consists of a segment correlation unit for determining the shape of the data segment using only the most significant bits, two storage units of the serial connection, a confidence counter, and a polarity correction control unit that is input when the output of the segment correlation unit indicates information that the polarity is correct The polarity control signal for bypassing data is output to the polarity correction unit when the polarity control signal for inverting the input data is displayed when the polarity control signal indicates that the polarity is inverted.

The segment correlation unit may determine whether the inverted code bits of the segment sync signal interval are in the form of 1001 or 0110 and output a logic signal accordingly.

The confidence counter increases the reliability by one step when the output of the comparator has information that the two values stored in the first and second storage units are the same, and decreases the reliability by one step when the reliability information is higher than a certain threshold. When 1 is less than a specific threshold, 0 is output as an enable signal of the polarity correction controller.

If the output of the confidence counter is 0, the polarity correction controller outputs the newly input value as the polarity control signal and ignores the newly input value if it is 1, and outputs the previous value as the polarity control signal as it is. It features.

1 is a block diagram of a general digital TV receiver

Fig. 2A is a waveform diagram of a data segment synchronizing signal when the polarity of data is correct.

2B is a waveform diagram of a data segment synchronizing signal when the polarity of data is inverted;

3 is a block diagram illustrating a polarity correcting apparatus of a digital TV according to the present invention;

4 is a detailed block diagram of a segment correlation unit of FIG. 3.

Explanation of symbols for main parts of the drawings

31: polarity correction unit 32: segment correlation unit

33,34: storage 35: exclusive Noah gate

36: confidence counter 37: polarity correction control unit

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention detects the shape of the data segment synchronizing signal using only the sign bits of the digital data to determine the polarity and corrects the polarity of the input digital data according to the determination result.

The polarity correction apparatus of the digital TV according to the present invention for realizing this is shown in FIG.

Referring to FIG. 3, the polarity correction unit 31 and the polarity correction unit 31 output the bypass or inverted 10-bit digital data output from the A / D converter 13 according to the polarity control signal. A segment correlator 32 for determining the shape of a data segment and outputting a logic signal according to the shape of the data segment using only the most significant bit (Din [9]) having the sign information among the data, operates in synchronization with the data segment synchronization signal. The storage units 33 and 34 of the serial connection sequentially storing the outputs of the segment correlation unit 32, and the outputs of the storage unit 33 and the output of the storage unit 34 are logically combined to form the storage unit 33, An exclusive Noah gate 35 for determining whether the two outputs of 34 are the same, a Confidence counter 36 for checking the reliability of the output of the exclusive Noah gate 35 and outputting the signal as an enable signal, and the impedance On counter 36 Generating a polarity control signal in response to the output of the output enable signal and a storage section 34 that is to be configured with the polarity corrector (31) correcting the polarity controller 37 outputs a.

The segment correlator 32 may use the one inserted in the block for detecting the data segment synchronizing signal, or may be configured separately in the polarity correction device as shown in FIG.

Referring to FIG. 4, three inverters 42, 43 and 44 of serial connection for sequentially delaying the output of the inverter 41 by one symbol are inputted to the inverter 41 which receives only the sign bits of 10-bit digital data. And, if the output of the inverter 41 and each of the delays (42, 43, 44) is a '1001' type AND gate 45 to output a 1, the inverter 41 and the delays (42, 43, 44) ) Is composed of an AND gate 46 that outputs 1 and an OR gate 47 that logically combines the outputs of the two AND gates 45 and 46.

The storage units 33 and 34 and the retarders 42, 43 and 44 may be configured as flip-flops.

In the present invention configured as described above, the shape of the data segment synchronization signal of 4 symbols inserted in every data segment is promised to have 1001. When the synchronous phase of the FPLL unit 12 is 0 degrees, the configuration shown in FIG. 1001, and the FPLL unit 12 has a synchronous phase of 180 degrees, has the form as shown in FIG. 2B. Therefore, the 10-bit digital signal output from the A / D converter 13 cannot know the polarity of the signal due to the inaccuracy of the FPLL unit 12.

Therefore, at the initial stage of operation, the FPLL section 12 is initialized to 0 degrees. That is, the polarity control signal output from the polarity correction control section 37 is set as in the case of being synchronized with 0 degree. In this case, the polarity correction unit 31 does not change the polarity of the input digital data.

In the present invention, the polarity correction unit 31 bypasses the input digital data without polarity correction if the input polarity control signal is '0', and inverts the polarity by multiplying the input data with '-'. It can be designed to output afterwards. The reverse is also possible, but in the present invention will be described as an embodiment.

In addition, since the polarity of the signal may be changed initially, the type of the data segment synchronization signal may be '0110'. Accordingly, the segment correlation unit 32 determines whether the data segment has the form of 1001 or 0110 by using only the most significant bit having the sign information among the outputs of the polarity correction unit 31.

That is, only the most significant sign bit of the 10-bit digital data output from the polarity correction unit 31 is input to the inverter 41 of the segment correlation unit 32. At this time, since the power level of the data segment synchronization signal is mapped to 120 and -120, the sign bit of 120 is 0 and the sign bit of -120 is 1. However, since the positive polarity of the data segment synchronization signal is 120, -120, -120,120 (i.e., 1001) and the negative polarity is -120,120,120, -120 (i.e. 0110), an inverter is used to make the sign bit the same as the data segment synchronization signal. (41) is used.

The signal inverted by the inverter 41 sequentially passes through three delayers 42, 43, and 44 that delay input data in symbol units. Therefore, if the input data type is 1001, the output of the AND gate 45 becomes '1', and if it is 0110, the output of the AND gate 46 becomes '1'; otherwise, the AND gate 45, The outputs of 46) are all '0'. Here, the outputs of the AND gates 45 and 46 are not all set to '1'. The outputs of the AND gates 45 and 46 are logically combined by the OR gate 47. Therefore, the probability that the output of the AND gate 46 is a and the output of the OR gate 47 is b is shown in Table 1 below.

a b Probability of coming out Positive polarity 0 One One Negative One One -One Etc 0 0 0

If a is a sign data in Table 1, the probability is 1, -1, 0.

In this case, the data segment synchronization signal is of two types, 1001 and 0110, but when the noise is interrupted, all of the data segment synchronization signals may come out from 0000 to 1111. However, since the data segment sync signal section is a repeating section for each data segment, the probability of 1001 or 0110 is very high, so only 1001 and 0110 are considered as the data segment sync signal in the present invention and the other values are ignored. Therefore, if a and b are both 0, it is ignored. Since b is always 1 in the data segment sync interval, the output of b is also ignored and only the output of a is used.

As a result, the segment correlation unit 32 outputs '0' when the shape of the code of the data segment section passes through the inverter 41 and has a value of '0' when it has a value of '110'.

The output of the segment correlation unit 32 is stored in the storage unit 33, the output of the storage unit 33 is stored in the storage unit 34 after one segment, and at the same time, the two outputs of the storage units 33 and 34 Is input to the exclusive Noah gate 35 to determine whether the two values are equal. The storage units 33 and 34 may record once every data segment.

The output of the exclusive NOR gate 35 is input to the confidence counter 36, which also checks the reliability only once per data segment. The confidence counter 36 outputs an enable signal to the polarity correction controller 37 when reliability is accumulated one or more times, and the polarity correction controller 37 generates a polarity control signal for correcting the polarity of data currently received. . When the polarity control signal is input to the polarity correction unit 31, the polarity correction unit 31 corrects the polarity by inverting the received data.

That is, the initial value of the polarity correction control unit 37 assumes that the polarity of the received signal is correct, and outputs a value corresponding thereto, for example, '0'. However, when the value stored in the storage unit 34 indicates that demodulation is completed at a phase of 180 degrees, the output of the polarity correction controller 37 is inverted to '1' and output. Therefore, the data input to the polarity correction unit 31 is output with the polarity reversed. In addition, the confidence counter 36 indicates that the output of the exclusive NOR gate 35 has the same information stored in the storage units 33 and 34, that is, outputting '1' increases the reliability by one step and indicates that the information is different. Lower the reliability by one step. The confidence counter 36 is designed to output an unconditional 1 as an enable signal of the polarity correction controller 37 when the reliability, that is, the count value is greater than or equal to a specific threshold value, and output 0 when the reliability counter is less than the specific threshold value. Here, the threshold value varies depending on the designer, and it is assumed in the present invention to be '1'. Therefore, when the confidence counter 36 is a 4-bit counter, 0 is output when the count value is 0, and 1 is output to the polarity correction control unit 37 when 1 to 15 are counted.

At this time, the data inputted to the polarity correcting unit 31 is outputted with the polarity corrected by the polarity control signal of the polarity correcting control unit 37, but the data inputted to the polarity correcting unit 31 continues to be inverted in polarity. Since the phase is not changed until the power is turned on / off or the channel is changed, the polarity correction control unit 37 must continuously output '1' as the polarity control signal. To this end, the polarity correction controller 37 outputs the value of the confidence counter 36, that is, if the enable signal is 0, ignores the old value and outputs a newly input value, and if the enable signal is 1, ignores the newly input value. It is designed to output the previous value as it is.

Therefore, the operation of the polarity correction unit 37 is shown in Table 2 below.

Previous value Entered value Output value Count value of confidence counter 36 = 0 One 0 0 0 One One Count value of confidence counter 36 = 1-15 One 0 One 0 One 0

For example, if the data segment synchronization type of the input data is 1001 having a positive polarity, the polarity correction controller 37 continuously outputs 0 to the polarity correction unit 31 since the initial state is not changed. ) Bypasses the input digital data as it is.

However, if the data segment synchronization type of the inputted data is 0110, the polarity is inverted and inputted, and the output of the segment correlation unit 32 is '1'. When this '1' is input to the exclusive Noah gate 35 through the storage units 33 and 34 of the serial connection, the output of the storage units 33 and 34 and the output of the exclusive Noah gate 35 also become '1'. The value of the confidence counter 36 changes from 0 to 1. In this case, since the input and output of the confidence counter 36 differ by one clock, the output value 0 is outputted when the count value of the confidence counter 36 changes to one. Accordingly, since the output of the confidence counter 36 is 0, the polarity correction controller 37 outputs an input value, that is, '1' to the polarity correction unit 31.

Since the polarity control unit 31 is a polarity control signal '1', the polarity control signal is inverted to correct the polarity and then output the polarity correction signal. The segment correlation unit 32 receives the data whose polarity is corrected. Outputs '0' because is positive. In addition, even when the output of the storage units 33 and 34 is all zero and the value input to the polarity correction control unit 37 is zero, the output of the confidence counter 36 is not zero. The correction controller 37 outputs the previous value, for example, '1' as it is. Therefore, the data input to the polarity correction unit 31 is corrected and output in the form of positive polarity by the control signal of the polarity correction control unit 37, but the data input to the polarity correction unit 31 continues to be inverted in polarity. Since the polarity correction control unit 37 keeps outputting '1' as the polarity control signal even though it is being input in the state, the output of the polarity correction unit 31 is always output with the correct polarity.

This is shown in Table 3 below.

a c d e f g One One One One 0 One 0 One One One One One 0 0 One 0 One One 0 0 0 One One One 0 0 0 One One One

As described above, according to the polarity correction apparatus of the digital TV according to the present invention, by determining the polarity of the input data and processing all the polarity correction according to the determined result in the digital domain, accurate polarity correction is performed to improve system performance. It works. Further, the circuit is simplified by detecting the pattern of the data segment synchronization signal using only the most significant bit having the sign information among the input digital data and determining the polarity of the digital data input in the pattern of the detected data segment synchronization signal. When IC is integrated, integration is easy and IC size is small, which lowers the cost.

Claims (7)

In the polarity correction device for determining and correcting when the polarity of the data is inverted due to the characteristics of the demodulator during demodulation of the received data, A polarity correction unit for outputting the digital data input as it is or inverted according to the polarity control signal; A segment correlation unit for determining the shape of the data segment using only the most significant bit having the sign information at the output of the polarity correction unit and outputting a logic signal according to the determination result; First and second storage units of a serial connection operating in synchronization with a data segment synchronization signal and sequentially storing an output of the segment correlation unit; A comparison unit determining whether two outputs of the first and second storage units are the same; A confidence counter that checks the reliability of the output of the comparator and outputs it as an enable signal; And a polarity correction control unit generating a polarity control signal according to the enable signal of the confidence counter and the output of the second storage unit and outputting the polarity control signal to the polarity correction unit. The method of claim 1, wherein the segment correlation unit An inverter for receiving and inverting only the most significant bit having sign information from the output of the polarity correction unit; Three delayers in series connected to sequentially delay the output of the inverter by one symbol, And a logic unit configured to output '0' when the outputs of the inverter and the retarder are in a 1001 form and '1' in a 0110 form. The method of claim 1, wherein the comparison unit Polarity correction device, characterized in that consisting of an exclusive Noah gate. The method of claim 1, wherein the confidence counter is If the output of the comparator has information that the two values stored in the first and second storage units are the same, the reliability is increased by one step, and if the information is different, the reliability is decreased by one step. And a zero value is output as an enable signal of the polarity correction controller if the threshold value is less than the threshold value. The method of claim 1, wherein the confidence counter is A polarity correction device, characterized in that the reliability is checked only once per data segment. The method of claim 1, wherein the polarity correction control unit If the output of the confidence counter is 0, the previous value is ignored and the newly input value is output as the polarity control signal. If the value is 1, the newly input value is ignored and the previous value is output as the polarity control signal. Device. When a high frequency (RF) signal is received through an antenna, a tuner selects a frequency of a desired channel by tuning and converts it into an intermediate frequency (IF) signal. An analog / digital conversion unit for demodulating the IF signal output from the tuner into I and Q signals of a baseband, locking the frequency and phase, and converting the IF signal into a digital signal of a predetermined bit; A polarity correction unit for outputting the digital data output from the analog / digital conversion unit as it is or inverted according to a polarity control signal; A segment correlation unit for determining the shape of the data segment using only the most significant bit having the sign information at the output of the polarity correction unit and outputting a logic signal according to the determination result; First and second storage units of a serial connection operating in synchronization with a data segment synchronization signal and sequentially storing an output of the segment correlation unit; A comparison unit determining whether two outputs of the first and second storage units are the same; A confidence counter that checks the reliability of the output of the comparator and outputs it as an enable signal; A polarity correction controller configured to generate a polarity control signal according to an enable signal of the confidence counter and an output of the second storage unit, and output the polarity control signal to the polarity correction unit; A digital data decoding unit for restoring a synchronization signal from the data whose polarity is corrected in the polarity correction unit and decoding the data using the synchronization signal; And a display unit for displaying the decoded data.

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