JPS61245769A - Video signal processor - Google Patents

Abstract

PURPOSE:To make noises unremarkable by clamping a noise signal with white and black peak to a gray level when a signal with a bad C/N is received. CONSTITUTION:The gray clamp circuit 14 clamping a white peak / black peak noise signal into the gray level is of the same constitution as a conventional IDU when a simple buffer amplifier is used. Since the white or black peak noise in a detected output appears pulsively, the number of peaks is counted, and when the number reaches, e.g., (n) or over in one field, the clamp circuit is activated to clamp both the white and black peaks to the gray level, that is, the intermediate value of a video signal. Thus, noise is not made remarkable on a TV pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal processing device mainly used in a video detection circuit of a satellite broadcasting receiver. There was something to show.

(1) Improved the characteristics of the detection circuit for FM video signals such as the PLL system, so that even when the C/N value has deteriorated, the white peak
(2) The bandwidth of the IF and detection circuit was narrowed to reduce the noise generation.

(3) Items related to the combination of (1) and (2) above.

(4) No measures were taken to reduce white peak or black peak noise due to local deviation of LNH.

Problems to be Solved by the Invention However, the above configuration has the following problems.

In other words, in (1) above, C/N
There is a limit to the value, and the generated noise cannot be reduced.

Furthermore, in (2) above, the signal transmission characteristics (DG, DP, etc.) deteriorate. Furthermore, in (4) above, white peak and black peak noises occur and increase due to the local deviation of the LNH.

The present invention solves the above-mentioned problems, and includes white peaks,
An object of the present invention is to provide a video signal processing device that can reduce noise even when black peak noise occurs.

Means for Solving the Problems The present invention includes a counter that counts white or black peaks, and when the count of the counter exceeds a certain value within a certain period of time, the white or black peak signal is converted to an intermediate value of the video signal. The band of the IF and detection circuit is kept optimal from the viewpoint of signal transmission characteristics, and the level of the generated noise is clamped to the intermediate value of the video signal.

Effect The present invention has the above-described configuration, so that the white peak in the detected output,
Alternatively, the black peak noise appears in a pulse-like manner, so when the number of noises is counted, for example, n or more in one field, the clamp circuit is activated, and both the white peak and the black peak are at the gray level, i.e. Since the image signal is clamped to the intermediate value of the video signal, noise becomes less noticeable when viewed as a TV screen.

Embodiment Fig. 1 shows the main parts of a video signal processing device according to an embodiment of the present invention, Fig. 2 shows an example of a screen in this embodiment, and Fig. 3 shows the entire satellite broadcasting receiver incorporating this embodiment. FIG. 4 shows changes in signal waveforms in this embodiment.

In Fig. 3, 1 is a parabolic antenna that receives satellite broadcast radio waves, and 2 is a parabolic antenna that receives ultra-high frequency signals (e.g., 12G, 1Z band or 4GH2 band radio waves) in the 1GHz band (here, 950 MHz to 1450MHz).
A low noise converter (L
NB). Reference numeral 3 denotes a column of the parabolic antenna 1, and a mechanism for rotating the parabolic antenna 1 is attached when receiving radio waves from a plurality of satellites. 4 is a cable that has good high frequency characteristics and does not attenuate I GHz band signals, and the above components are installed outdoors. 6 is a satellite broadcasting receiver, also called IDU (Indoor Unit). 6 is a tuner called 2nd mixer,
The signal of the - channel in the 10H2 band signal is set to an IF frequency (for example, 402.75MH2-?510MH2).
z). 7 is an IF amplifier, and 8 is an FM broadband detector, which has good linearity characteristics over a bandwidth of 30 MHz or more, for example. 9 is an audio FM that demodulates the audio
The detector uses PCM demodulation for PGM and F for FM.
Perform M detection. Reference numeral 14 denotes a gray clamp circuit that clamps the white peak and black peak noise signals to the gray level.If this circuit is simply a buffer amplifier, it will have the same configuration as a normal IDU. 11 is a base frequency band, a buffer 1 amplifier for outputting video and audio signals, and 10 is an RF converter that converts the outputs of the audio FM detector 9 and the gray clamp circuit 14 into RF signal outputs. The small RF output of this RF converter 1o is VHF, which is connected to the antenna input of a normal television receiver 13 via a VHF band cable 12 to obtain an image as shown in FIG. 2(A). In the transmission system between the parabolic antenna 1 and the FM detector 8, if the C/N deteriorates, noise N with white peaks and black peaks will appear as shown in Figure 2 (A).
appears on the screen and becomes unsightly. If the local oscillator in LNB2 shifts, even if the C/N ratio does not deteriorate, noise with only white peaks or only black peaks will appear, making it unsightly.

In this embodiment, the above phenomenon is greatly reduced as shown in FIG. 2(B).

The concrete configuration of the gray clamp circuit 14 is shown in FIG.
It is shown in 32 blocks. 8 is an FM detector, 16 is a pedestal clamp circuit, and the pedestal clamp pulse is formed by the clamp pulse generating circuit 18. Reference numeral 16 denotes a synchronization separation circuit, and its output synchronizes the horizontal FC circuit 17. 1
9 is a vertical synchronization pulse generation circuit that integrates the output of the synchronization separation circuit 16 to obtain a vertical synchronization pulse. The clamp pulse generating circuit 18 appropriately shapes and delays the output of the horizontal FC circuit 17 to form a pedestal clamp pulse having a phase as shown in FIG. 4(B). With the output of the vertical synchronization pulse generation circuit 19 and the output of the horizontal FC circuit 17, as shown in FIG. to form. The counter gate 2° can be easily constructed from a counter and a flip-flop. This is to prohibit the pedestal clamping of the pedestal clamp circuit 15 during VBL, and to stop the operation of the pulse counter 27 during VBL. Fifth
In the figure, φ1 is a video signal seen in a vertical period, t0 to t
, is the vertical retrace period, and the 3H width hatched part starting from tl of φ1 is the vertical synchronizing pulse.
φ2 in the figure is obtained as the output of the vertical synchronization pulse generation circuit 19. In this way, t, ~1. shown in FIG. During this period, the pedestal clamp circuit 16 pedestally clamps the signal shown in FIG. 4(m). At this time, since the color burst is often superimposed on the pedestal, it goes without saying that so-called soft clamping is performed to avoid affecting the burst signal during clamping.

In Figures 4 (M) and (B), for simplicity, the pedestal level vP and the black level v! 1 are chosen equally. Therefore, when the black level VB is clamped to a constant level,
Since the detection output value is constant, the white level V is also fixed. Buffer 1 amplifier 21 is DC coupled. 22 is a black peak detection circuit which detects a noise signal with a black level higher than the human VB in FIG. 4, converts the level in the next pulse shaping circuit 23, and shapes it into a pulse. Pulse shaping circuit 23
The output is shown in FIG. 4(D). On the other hand, the white peak detection circuit 24 detects a noise signal exceeding V in FIG. 4(A),
A pulse shaping circuit 25 converts the level and shapes the signal into a pulse. The output of the pulse shaping circuit 26 is as shown in FIG. 4C. When the logical sum of FIG. 4(C) and (Di is formed by the OR gate 26, the output of the OR gate 26 becomes the one shown in FIG. t,
~t.

The output of the OR gate 26 during the period is counted every field. If the pulse counter 27 is configured as shown in FIG.
The counter 270 counts only between t and to because φ is low. As the counter 27C, for example, TTL
A binary counter 5N74LS93 is considered. Vertical synchronization pulse generation circuit 1 with field counter 27R
The configuration is such that the flip-flop 27F is reset by counting the outputs of 9 and generating a reset pulse once every 4o96 fields (approximately 1.1 minutes), for example. When 16 or more noise pulses are applied from the OR gate 26 to the counter 27G during one field, the counter 2
7C's 25 output is from high level "H" to low level "L"
”, this change is transmitted to the T terminal of the flip-flop 27F, the flip-flop 27F is set, and the Q
becomes H'' and Q becomes 'L'', analog gate 32A is cut off, and analog gate 32B becomes conductive. The counter 270 is set to 1 for each field. , -1. Since it is cleared in the meantime, when there are 15 or less noise pulses in one field, the flip-flop 27F is not set and the output of the clamp circuit 29 is not transmitted to the buffer amplifier 320. Approximately every minute there is a time when most or a portion of one field is not set. However, if it is about one field, there is no practical problem. Also, when the satellite is changed, there is no problem because the output of the clamp) 9 and the output of the delay 31 are the same, and the C/
When N becomes bad, OR gate 2 is placed within one field.
The output of 6 becomes 16 or more and the flip-flop 27F
is set and the output of the clamp circuit 29 is transmitted to the buffer 1 amplifier 32G, so there is no problem even if the flip-flop 27F is reset approximately every minute. Buffer amplifier 320 is analog gate 32A or analog gate 3
Buffer 1 amplifies the output of 2B, and the output of this amplifier 320 is transmitted to RF converter 10 and output buffer 711 in FIG.
will be communicated to.

On the other hand, 30 in Figure 1 is a buffer 1 amplifier, and its output is
The clamp pulse generating circuit 28 generates a high-speed clamp using the output of the OR gate 26, that is, the pulse portion shown in FIG. Clamp and set to gray level.

The output of the clamp circuit 29 is as shown in FIG. 4 (8), and the noise becomes less noticeable on the screen as shown in FIG. 2 (B).

In the above explanation, it is assumed that the transmission delay time from the buffer amplifier 21 to the clamp pulse generation circuit 28 is the same as the delay time at the bath sofa amplifier 3o, but when the output of the buffer 7 amplifier 3o is ahead, Buffer amplifier 3
Needless to say, a delay circuit is required between 0 and the clamp circuit 29.

Reference numeral 31 is a delay circuit that compensates for the delay in the clamp circuit 29, and there is no problem even if it is absent. However, when fields in which noise occurs and fields in which it does not occur alternately and the output of the field counter 27H is generated every 60 fields, it is necessary to remove jitter. With the configuration as described above, the white peak and black peak noises can be clamped to the gray level.0 Effects of the Invention As described above, the present invention can achieve the following excellent effects.

(1) White peak when receiving a signal with poor C/N.

By clamping the black peak noise signal to the gray level, the noise can be made less noticeable.

(2) Even when white peak and black peak noise occurs due to a local deviation of the LNB, the noise can be made less noticeable by clamping it to the gray level.

(311F does not change the FM detection bandwidth, so there is no signal characteristic deterioration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a video signal processing device according to an embodiment of the present invention, and FIGS. 2(A) and 2(B) are front views showing a comparison of screens when the present invention is applied and when the present invention is not applied.
Figure 3 is a block diagram of a satellite broadcast receiving system to which the present invention is applied, Figures 4 (M) to (K) are waveform diagrams for explaining the operation of the present invention, and Figure 6 is a diagram for explaining the operation of the present invention. The waveform diagram and FIG. 6 are block diagrams of essential parts for explaining the operation of the present invention. 22... Black peak detection circuit, 23...
Pulse shaping circuit, 24...White peak detection circuit,
26... Pulse shaping circuit, 26... OR gate forming, 27... Pulse counter,
28...Krumfhals generation circuit, 29...
... Clamp circuit, 31 ... Delay circuit, 32
...Signal switching circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 4 (E) Figure 6

Claims (1)

[Claims] White peak or black peak noise that occurs in the detection output when the carrier wave (C) to noise (N) ratio (C/N value) in a device that detects and amplifies a frequency-modulated video signal deteriorates. A counter that counts one or both of the signals, and when the number of noise signals counted by the counter within a certain period of time exceeds a preset number, the white peak and black peak signals are clamped to the intermediate value of the video signal. A video signal processing device characterized by being provided with a clamp circuit.