JP2544012B2 - Data buffer parity check circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a parity check of data at an input / output port of a data buffer, facilitating detection of a cause when a parity error occurs when data is swapped in the data buffer. For this purpose, it is configured by providing means for controlling whether or not the parity check is performed at each port according to the data swap condition.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check method for a data bus of a small computer, and more particularly, it has a port for connecting a data bus between a plurality of devices and a corresponding device, It is configured to internally connect or switch between ports to set a route to relay control of data transfer between devices. Each port has a high side and a low side.
W) side, and relates to a parity check system of a data buffer having means for transferring high-side data to the low side or low-side data to the high side. In this specification, transferring high-side data to the low-side or low-side data to the high-side in the data buffer is called swap.

[Conventional technology]

FIG. 11 is a block diagram showing an example of a peripheral configuration of a data bus of a conventional small-sized computer, 51 is a CPU, 52 is a memory, 53 is an input / output device (I / O is indicated by an abbreviation in the figure). (Notation), 54 is an expansion input / output device (expressed as expansion I / O in the figure), 55-1 to 55-5 are buffers, 56 is a DB bus, 57 is an ED
B bus, 58 is an LD bus, and 59 is an MD bus.

In this configuration, the CPU 51 is connected to the DB bus 56 via the buffer 55-3, the memory 52 is connected to the buffer 55-4, and the expansion I / O 54 is connected to the DB bus 56 via the buffer 55-5. LD bus 58, MD bus 59,
The timing of data transfer between the EDB bus 57 and the DB bus 56 is adjusted.

In order to downsize these buffers in recent years, they have been
The conversion to I began to take place.

FIG. 12 is a block diagram showing an example of a configuration in which the buffer is made into an LSI, and 51 to 59 are the same as those in FIG.
Reference numeral 60 represents a data buffer, and 61-0 to 61-3 represent ports 0 to 3.

The data buffer 60 relays data transfer between devices by internally connecting the respective ports.

For example, port 0 indicated by numeral 61-0 and numeral 61-2
Expansion I / O device 54 by connecting port 2
And the EDB bus 57 from the memory 52 and the MD bus 59 from the memory 52 are connected to perform data transfer between the expansion input / output device 54 and the memory 52.

At this time, data parity check is performed at each port.

Each of these ports is, for example, 32 bits (4 bytes)
Width data transfer is possible. Then, the upper 16 bits (2 bytes) are set to the high-side byte (H-BYTE), and the lower 16 bits (2 bytes) are set to the low-side byte (L-BYTE).
As a result, data transfer using one of these can also be performed.

Also, in the data buffer, it is possible to swap the 2-byte data input from the high side to the low side and output it, or to swap the 2-byte data input from the low side to the high side and output it. Composed.

[Problems to be Solved by the Invention]

In the above data buffer, when the data input from a certain port is swapped in the data buffer and is output as the data on the side (high or low) different from the input side, the input / output port It is meaningless if the parity check of the data is not performed at an appropriate position, and when a parity error occurs, it is extremely difficult to determine where it occurred.

The present invention has been made in view of such conventional problems, and an object thereof is to provide means for rationally performing a parity check in a data buffer.

[Means for solving the problem]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims.

That is, the present invention has a port which is located between a plurality of devices and which connects a data bus with a corresponding device,
It is configured to internally set up a route by switching connections between ports to relay control of data transfer between devices. Each port consists of a high side and a low side, and a high side. In the data buffer having means for transferring the data of the low side to the low side or the data of the low side to the high side, each of the low side and high side ports has a parity check means on the input side and the output side, When transferring data from the high side port to the low side port, parity check is performed on the high side input side and the low side output side, and the parity check is not performed on the low side input side.
When transferring data from a port on the low side to a port on the high side, a means to perform a parity check on the input side on the low side and an output side on the high side, and not to perform a parity check on the input side on the high side. Is a parity check circuit of a data buffer.

[Work]

FIG. 1 is a diagram for explaining the principle of the present invention, in which 1 is a data buffer, 2 is an input port, and 2a is high.
Side, 2b is low (LOW) side, 3 is an output port, 3a is high (HIGH) side, 3b is low (LOW) side, 4-1 to 4-4 are buffers, and 5 is a swapper. .

In the figure, the data input from the high side 2a of the input port 2 is parity checked (P
After receiving C), take the path indicated by the letter A and go to buffer 4
-3 again receives the parity check (PC), is output to the high side 3a of the output port 3, and the output of the buffer 4-1 is swapped by the swapper 5 and passes through the path indicated by the letter B to the buffer 4-4. Check parity with (PC)
It is shown that the received signal is output from the row side 3b of the output port 3.

As shown in the figure, when the swapper 5 is operating,
The input from the row side 2b of the input port 2 is not relayed, so there is no point in performing a parity check in the buffer 4-2. (In the figure, a black square mark indicates that a parity check is performed, and a white square mark indicates that a parity check is not performed.) Although not shown in the figure, the low side 2b of the input port 2 is shown.
If the swapper 5 operates so as to take a path connected to the buffer 4-3 after the data input from the buffer 4-2 passes through the buffer 4-2, the parity check in the buffer 4-1 becomes meaningless.

On the other hand, when the input from the high side 2a of the input port 2 is directly output to the high side 3a of the output port 3 and the input from the low side 2b is directly output to the low side 3b of the output port, each buffer 4-1 is used. Parity check is required in all of 4-4.

The present invention controls whether or not to perform the parity check on the high side or the low side of each port according to such a swap condition.

As a result, the parity check can be reasonably performed, and the cause of the occurrence of the parity error can be easily identified.

〔Example〕

FIG. 2 is a diagram for explaining the determination as to whether or not to execute the parity check for each port for the data buffer according to the embodiment of the present invention.

Whether or not to perform the parity check at each port of the data buffer 6 depends on the IN signal of the data buffer or GA.
Determined by TE signal.

That is, the parity check is performed only on the port for which the IN signal or the GATE signal is ON.

In Fig. 2, the IN signal and GATE signal of port 1 are both OFF, so that the parity check is not performed is indicated by the cross mark. Port 0, port 2 and port 3 indicate either the IN signal or the GATE signal. The mark "○" indicates that the parity check is performed because it is ON.

FIG. 3 is a diagram for explaining the check condition of the high-side byte and the low-side byte of the port where the IN signal is ON,
(A) is when INPORT32 signal is ON, (b) is INPORT32
The case where the signal is OFF is shown, and the numeral mark 7 represents the data buffer 1 (DBF1) and the numeral 8 represents the data buffer 2 (DBF2). Also, D0 to D7 and D8 to D15 are digit 1 to 7 and digits 8 to 15 are each 1 byte of data on the low side, and D16 to D23 and D24 to D31 are each digit 16 to.
It represents data of 1 byte each on the high side of 23 and digits 24 to 31.

In FIG. 9A, if INPORT32 is ON, it means that the port can transfer 4 bytes, and BE (byte enable) is used to specify the byte. Therefore, the parity check also uses BE.

In the same figure (b), if INPORT32 is OFF, the port uses the lower 2 bytes (16-bit master or slave that uses D0 to D15), and the designation of that byte is A0 and BHE (bus High enable). Therefore, the parity check also uses A0 and BHE.

 Table 1 summarizes these conditions.

As described above, the parity check condition for the valid byte at that time is determined by the boat in which the IN signal is ON.

On the other hand, the data of the port in which the GATE signal is ON is controlled to pass through the word swap circuit through the HIGH word to the LOW word, the LOW word to the HIGH word, or through.

Therefore, depending on whether the word swap (SWAP signal) is ON or OFF, the data of the port where the GATE signal is ON is either the data swapped from the HIGH word, the data swapped from the LOW word, or the data passed through. It is necessary to identify and check the parity bit of each data under the same conditions as the port where the IN signal is ON.

FIG. 4 is a diagram for explaining the condition of the parity check of each byte of the input port and the output port. (A) shows the case where the data passes through between the ports in the data buffer, and (b) shows the HIGH word. From the LOW word to the LOW word, (c) shows the case from the LOW word to the HIGH word, and the black squares indicate the parity check (P
C), the white square indicates the parity check (P
C) is not performed.

Table 2 summarizes the check conditions for each byte of the input port and output port when the data shown in FIG.

The swap from the HIGH word to the LOW word as shown in FIG. 9B is performed by the SWAP signal of the input port. Therefore, the check condition of the LOW side byte of the output port is determined by the SWAP signal of the input port.

The conditions of the parity check in this case can be summarized as follows.
As shown in the table.

Swap from a LOW word to a HIGH word as shown in FIG. 7C is performed by the SWAP signal of the output port. Therefore, the check condition of the HIGH side byte of the output port is determined by the SWAP signal of the output port.

The conditions of the parity check in this case are summarized as follows.
As shown in the table.

FIG. 5 is a diagram showing a signal generation circuit of one embodiment of the present invention, in which (a) is a signal INPORT 32 generation circuit.
(B) and (c) are circuits for generating a signal indicating the check conditions for the HIGH side byte and the LOW side byte. (B) is a HIGH side byte, and (c) is a LOW side byte signal generation circuit. 10 is an AND gate, 11 is an OR gate, and 12 is an inverter. These are represented by similar numeral marks in the following figures without any particular notice.

In FIG. 7B, BE is used if the input port is a 32-bit port, and it is not checked if it is a 16-bit port.

 This circuit is common to all ports.

In FIG. 7C, the signal A0 or * BHE indicates that the LOW byte is valid when the level is "L".

This circuit uses BE when the input port is a 32-bit port, and A0 and * BHE when it is a 16-bit port.

 This circuit is also common to all ports.

FIG. 6 is a diagram showing a circuit for generating an INSWAPON signal indicating the swap condition of the input port.

In this circuit, whether the SWAP signal of the input port is ON or OF
It identifies whether it is F, and is common to all ports.

FIG. 7 is a diagram showing a parity check condition signal generation circuit at a port where the IN signal is ON. In the signal names in the figure, n corresponds to the port number.

 This circuit is provided independently for each port.

FIG. 8 is a diagram showing a parity check condition signal generation circuit for a port in which the GATE signal is ON.
Shows a case of a HIGH side byte, (b) shows a case of a LOW side byte, 10 is an AND gate, and 12 is an inverter.

In the HIGH side byte check circuit shown in FIG.
If the SWAP signal at the output port is OFF, check it as it is as the high-side parity bit. If ON, LO
Check as W side parity bit.

In the output signal of the figure, TH means through and SP means swap.

 This check is performed independently for each port.

In the LOW side byte check circuit shown in FIG.
If the SWAP signal at the input port is OFF, check the LOW side parity bit as it is. If ON, HIGH
Check as side parity bit.

 This check is also performed independently for each port.

FIG. 9 is a diagram showing a circuit at the final stage of the parity check, and the output signal PSTn is a signal showing the parity status for each port.

In the figure, the logical sum of the parity bit when the IN signal is ON, the parity bit when the GATE signal is ON, and the parity bit with the swap condition added is ORed, and finally the HIGH side byte is checked. Condition (HCHECK),
It is ANDed with the LOW side byte check condition (LCHECK).

 This circuit is provided independently for each port.

FIG. 10 is a diagram showing a parity error signal output circuit.

In the circuit shown in the figure, the logical sum of the parity status for each port obtained by the circuit shown in FIG. 9 is taken, and the signal * PE is output from the data buffer as the parity error signal.

〔The invention's effect〕

As described above, according to the present invention, it is possible to rationally perform a parity check in the case where data is swapped in the data buffer, and an error byte when a parity error occurs. There is an advantage that an error port etc. can be easily detected.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram for explaining the parity check of the data buffer of one embodiment of the present invention, and FIG. 3 is a diagram for explaining the check conditions of the port where the IN signal is ON. FIG. 4, FIG. 4 is a diagram for explaining check conditions of each byte of the input / output port, FIG. 5 is a diagram showing a signal generation circuit of each embodiment of the present invention, and FIG. 6 is a swap condition of the input port. FIG. 7 shows a circuit for generating a signal indicating
FIG. 8 is a diagram showing a parity check condition signal generation circuit for a port where the IN signal is ON, FIG. 8 is a diagram showing a parity check condition signal generation circuit for a port where the GATE signal is ON, and FIG. 9 is the final parity check FIG. 10 is a diagram showing a stage circuit, FIG. 10 is a diagram showing a parity error signal output circuit, FIG. 11 is a diagram showing an example of a configuration around a data bus of a conventional small-sized computer, and FIG. 12 is a buffer LSI. It is a figure which shows the example of a structure at the time of becoming. 1, 6-9 ... Data buffer, 2 ... Input port, 3 ...
... output ports, 4-1 to 4-4 ... buffers, 5 ... swappers, 10 ... AND gates, 11 ... OR gates, 12 ... inverters

Claims (1)

(57) [Claims] 1. Data between devices is provided by having a port located between a plurality of devices and connecting a data bus with a corresponding device, and internally setting a path by switching connection between the ports. It is configured to relay transfer, and each port consists of a high side and a low side.
In a data buffer having means for transferring high-side data to the low side or low-side data to the high side, each low-side and high-side port has a parity check means on the input side and the output side. However, when transferring data from the high-side port to the low-side port, the parity check is performed on the high-side input side and the low-side output side, and the parity check is not performed on the low-side input side. When data is transferred from the port on the high side to the port on the high side, the parity check is performed on the input side on the low side and the output side on the high side, and the means for controlling not to perform the parity check on the input side on the high side is provided. A parity check circuit for a data buffer characterized by the above.