JP2543271B2 - Time axis correction device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device for correcting a time shift between signals.

[0002]

2. Description of the Related Art With the advent of digital audio represented by compact discs (CDs), the sound quality of sources has been remarkably improved. Along with this, in order to improve the sound quality of the audio equipment, not only the circuit configuration but also the electronic parts (capacitors, resistors, etc.) constituting the circuit are being studied for higher sound quality. On the other hand, it is said that the reproduced sound has a difference in sound quality due to the difference in the material forming the CD. In this way, in comparison between signals having a very high degree of similarity reproduced from the same source, the deviation on the time axis at the time of measurement between the signals to be compared has a great influence on the comparison result.

Therefore, there has conventionally been a delay correction device used in a two-signal waveform similarity measuring device as described in Japanese Patent Publication No. 2-9360.

A conventional two-signal waveform similarity measuring device will be described below. FIG. 5 shows a conventional two-signal similarity measuring device.

In FIG. 5, reference numeral 51 is a first memory circuit, 5
2 is a second storage circuit, 53 is a delay correction device, 53a is a delay calculation device, 53b is a counting circuit, 53c is a third storage circuit, 53d is a fourth storage circuit, 54 is a calculation device, 55,
58 is an input terminal, 56 and 59 are sampling circuits, 5
7, 510 are analog / digital converters (hereinafter referred to as A /
(Abbreviated as D converter). 6 and 7 are operation explanatory diagrams of FIG.

Next, the operation of the conventional example will be described. The analog input signal x (voice signal) of the transmission system under measurement applied to the input terminal 55 (channel 1) is sampled at N = 1024 points every 20 μs by the sampling circuit 56, and the digital signal x by the A / D converter 57. _i (i = 0,
1, 2, ..., 1023). As the digital signal x _i , data of 1024 points corresponding to time T (20 μs × 1024) is converted from address 0 to address 1 of the first memory circuit 51 as shown in FIG. 6A.
It is stored in the memory locations up to 023. Further, the analog output signal y of the transmission system under test delayed by ΔT = 500 μs from the analog input signal x is added to the input terminal 58 (channel 2), and the sampling circuit 59 simultaneously outputs the input signal x at 1024 + 25 points ( 25 points are equivalent to a delay of 500 μs) and then A
The digital signal y _i (i = 0, 1,
2, ..., 1048). This digital signal y _i has 1049 points corresponding to the time T + ΔT in the state where ΔT = 500 μs is delayed with respect to the digital signal x _i , and the address of the second memory circuit 52 is set as shown in FIG. 6B. It is stored in the memory locations from the 0th address to the 1048th address. Next, the digital signals x _i and y _i are applied to the delay calculation device 53a, and first, the digital signal x _i is Fourier-transformed as shown in (Equation 1).

[0007]

[Equation 1]

(Where X _k is the spectrum at each frequency point, k = 0, 1, 2, ..., N-1, j
= (-1) ^1/2 ) Similarly, the digital signal y _i is then Fourier transformed as shown in (Equation 2).

[0009]

[Equation 2]

(However, Y _k is the spectrum at each frequency point, k = 0, 1, 2, ..., N-1, j
= (-1) ^1/2 ) Next, after calculating Z _k = X _k ^* · Y _k (* is a complex conjugate), Z ₀ (DC component) is calculated as shown in (Equation 3) for Z _k. Is set to zero and the inverse Fourier transform is performed.

[0011]

(Equation 3)

Thus, the cross-correlation function of the digital signals x _i and y _i as shown in FIG. 7, that is, the input / output signals x and y can be obtained. Therefore, in FIG. 7, the digital signal y _i recorded in the first and second storage circuits 51 and 52 is the digital delay value d = 25 or 50 with respect to the digital signal x _i .
0 μs (delay value 1 = 20 μs) is delayed. The digital delay value d = 25 thus obtained is added to the counting circuit 53b for counting, and as shown in FIG. 6 (b), the digital values stored from the 25th address to the 1048th address of the second storage circuit 52 are stored. Signal y _{i + 25}
(I = 0, 1, 2, ..., 1024) is read. The read digital signal y _{i + 25} is stored in the storage locations from the 0th address to the 1023rd address of the third storage circuit 53c as shown in FIG. 6D. Further, the digital signal x _i stored in the first storage circuit 51 is read and stored in the storage locations from the address 0th to the address 1023th of the fourth storage circuit 53d.
In this way, the digital signals x _i and y _{i + 25} stored in the third and fourth storage circuits 53c and 53d are output to the arithmetic unit 54 in a state where the phase difference is zero. The digital signal x _i stored in the third and fourth storage circuits and the delay-corrected digital signal y _{i + 25} are applied to the arithmetic unit 54. First, the arithmetic unit 54 calculates the waveform areas of the digital signal x _i and the delay-corrected digital signal y _{i + 25} using (Equation 4) and (Equation 5).

[0013]

[Equation 4]

[0014]

(Equation 5)

Next, the digital signal x _i is Fourier-transformed using (Equation 6).

[0016]

(Equation 6)

Next, after calculating A _k = X _k · X _k ^* , A _k
On the other hand, the inverse Fourier transform is performed by setting A ₀ (DC component) to zero as shown in (Equation 7).

[0018]

(Equation 7)

In this way, the autocorrelation function of the digital signal x _i is calculated to obtain the peak value P _xx of a _i . Similarly, Fourier transform is performed on the digital signal y _{i + 25} using (Equation 8).

[0020]

(Equation 8)

After calculating C _k = X _k ^* .Y _k , C _k
On the other hand, the inverse Fourier transform is performed according to (Equation 9) with C ₀ (DC component) set to zero.

[0022]

[Equation 9]

In this way, the cross-correlation function of the digital signal x _i and the delay-corrected digital signal y _{i + 25} is calculated to obtain the peak value P _xy of c _i . Using the waveform areas S _x and S _y and the peak values P _xx and P _xy thus obtained,

[0024]

[Equation 10]

The calculation of is performed. The similarity of the waveforms of the digital signals x _i and y _{i + 25} is measured with the value K obtained in this way.

The same effect can be obtained even if the Fourier transform and the inverse Fourier transform in this conventional example are calculated by using the fast Fourier transform (FFT) and the inverse fast Fourier transform (IFFT).

[0027]

However, in the above-mentioned conventional configuration, it is possible to detect and correct the time lag of the sampling circuit and the A / D converter in the unit of the sampling period. It has a problem that it cannot be detected or corrected.

The present invention solves the above-mentioned conventional problems, and it is possible to detect and correct a time lag less than the sampling period of the sampling circuit and the A / D converter or a time lag due to a variation of the sampling period. It is an object of the present invention to provide a time axis correction device.

[0029]

In order to achieve this object, a time axis correction device of the present invention stores two time discrete signals having a predetermined similarity and a time lag between them. First and second storage means, first signal extraction means for reading data of a predetermined length from a predetermined point of the data stored in the first storage means, and first signal from the second storage means. Second signal extracting means for reading out data of a predetermined length from data corresponding to the read start point of the data read out by the extracting means, and a predetermined time interval for the data of the predetermined length read by the second signal extracting means. The first arithmetic means for sequentially calculating the data having the time delay or the time advance phase, the third storage means for storing the data sequentially calculated by the first arithmetic means, and the first signal extracting means for reading the data. A predetermined length Second arithmetic means for sequentially calculating the correlation value between the data and a predetermined length of data stored in the third storage means, and a fourth arithmetic means for storing the correlation value sequentially calculated by the second arithmetic means. It is composed of a storage means and a third calculation means for calculating the maximum value of the correlation values stored in the fourth storage means, and a second calculation method of the correlation value determined by the third calculation means is the second. The data corresponding to the data used by the calculation means is output from the third storage means.

[0030]

The present invention has the following functions due to the above configuration. That is, the first and second storage means respectively store two time-discrete signals having a predetermined degree of similarity and having a time lag between them. Then, the first signal extraction means reads out data of a predetermined length from a predetermined point of the data stored in the first storage means. Further, the second signal extraction means reads out data of a predetermined length from the second storage means from the data corresponding to the reading start point of the data read out from the first storage means by the first signal extraction means. And
The first calculation means sequentially calculates data having a time delay or a time advance phase of a predetermined time interval with respect to the data of the predetermined length read by the second signal extraction means. The third storage unit stores the data sequentially calculated by the first calculation unit. Then, the second calculation means sequentially calculates the correlation value between the data of the predetermined length read by the first signal extraction means and the data of the predetermined length stored in the third storage means.
Then, the fourth storage means stores the correlation values sequentially calculated by the second calculation means. And the third calculation means
The maximum value of the correlation values stored in the fourth storage means is calculated. Then, the data used by the second calculating means for calculating the maximum correlation value determined by the third calculating means is output from the third storing means. That is, the time difference between the signal stored in the first storage means and the signal stored in the second storage means is removed from the signal stored in the second storage means to output the signal. ing.

[0031]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a time axis correction device according to the first embodiment of the present invention.

In FIG. 1, reference numerals 1 and 2 are input terminals for inputting two time-discrete signals having a predetermined degree of similarity and a time lag between them, and 3 and 4 are input from the input terminals 1 and 2. A memory for storing the generated signal, 5 is a signal extractor for reading a predetermined length of data from a predetermined point of the data stored in the memory 3, and 6 is a reading start point of the data read from the memory 3 by the signal extractor 5. A signal extractor for reading data of a predetermined length from the corresponding data from the memory 4, and 7 for sequentially calculating data having a time delay or a time advance phase of a predetermined time interval with respect to the data of the predetermined length read by the signal extractor 6. An operation unit, 8 a memory for storing data sequentially calculated by the operation unit 7, and 9 a correlation value between a predetermined length of data read by the signal extractor 5 and a predetermined length of data stored in the memory 8. To Calculator for next calculation, 10 calculator 9
A memory for storing the correlation values sequentially calculated in 11, a computing unit 11 for computing the maximum value of the correlation values stored in the memory 10, and a computing unit 12 for computing the correlation value determined by the computing unit 11 to be the maximum. An output terminal for outputting the data used in 9 from the memory 8. 2 is a block diagram showing an example of an apparatus for obtaining an input signal for explaining the operation of the first embodiment, 21 is a compact disc, 22 is a CD player for reproducing a CD 21, and 23 is a CD player 22. Convert the playback signal of the CD21 played back in step A into a digital signal A
The operation clock of the CD player 22 and the operation clock of the A / D converter 23 are asynchronous. FIG. 3 is an operation explanatory diagram of the arithmetic unit 7 in the first embodiment.

The operation of the time axis correction apparatus of the first embodiment of the present invention constructed as above will be described below.

A predetermined track of the CD 21 is reproduced by the CD player 22. The output of this CD player 22 is A / D
The converter 23 converts the digital signal. The output of the A / D converter 23 is input to the input terminal 1. The digital signal input to the input terminal 1 is stored in the memory 3. In addition, a predetermined track that is exactly the same as that of the CD 21 is recorded on the CD.
Play on the player 22. This reproduction signal is input to the A / D converter 23 and converted into a digital signal. The converted digital signal is input to the input terminal 2. The digital signal input to the input terminal 2 is stored in the memory 4. Here, the digital data stored in the memories 3 and 4 are the same even though the same track of the CD 21 is reproduced by the same CD player 22 and its output is converted by the same A / D converter 23. is not. That is, since the operation clocks of the CD player 22 and the A / D converter 23 are asynchronous and the A / D conversion is not performed at the same time, the digital data stored in the memory 3 and the memory 4 are mutually exchanged. The degree of correlation is high, and there is a time lag between the two.

Next, the signal extractor 5 reads out data having a predetermined time length from the correction start point for starting the time shift correction from the data stored in the memory 3. Further, the signal extractor 6 reads from the memory 4 the data corresponding to the data read by the signal extractor 5 from the memory 3.

Next, the calculator 7 sequentially calculates data having a time delay or a time lead phase of a predetermined time interval with respect to the data read by the signal extractor 6. The operation of the arithmetic unit 7 will be described with reference to FIG. The data input to the arithmetic unit 7 is a time discrete signal sampled at the sampling period (T _s ) of the A / D converter 23 shown by the white circles in FIG. Assuming that the time interval obtained by dividing the sampling cycle T _s into a predetermined interval is T _w (T _s = n · T _w , n: positive integer), the calculator 7 is based on the input signal and is shown in FIG. The signal as shown by the white circle, that is, m from the sampled point
Data obtained by sampling a signal delayed by T _w (m = 0, 1, 2, ..., N) at the sampling timing of FIG. 3A, that is, data indicated by black circles of FIG. 3B. To calculate. Next, an example of calculating the data indicated by the black circles in FIG. 3 will be described using formulas. The data read by the signal extractor 6 is x (i). However, i = 1, 2, ..., N
(N corresponds to a predetermined length). x (i) is data sampled at the sampling period T _s . Then, assuming that this sampling cycle is equally divided into n by the time interval T _w , the data X _m (i) delayed by the time m · T _w from the data x (i) is (Equation 11) and the time m · T _w time. The data X _-m (i) having the leading phase of can be calculated using (Equation 12).

[0038]

[Equation 11]

[0039]

(Equation 12)

The calculated signal is stored in the memory 8. Next, the calculator 9 determines a predetermined value based on the data read by the signal extractor 5 from the memory 3 and the output of the calculator 7 stored in the memory 8, that is, the data read by the signal extractor 6 from the memory 4. The correlation value between the signals with the time delay added is calculated. The memory 10 stores this output. Then, the calculator 11 calculates the maximum value of the correlation values stored in the memory 10. Then, the data corresponding to the data used for the correlation process that gives the maximum value, that is, the data stored in the memory 8 is output from the output terminal 12.

As described above, according to the first embodiment of the present invention, the sampling cycle is divided into n equal parts with respect to the second signal with the first signal as the reference, and the time difference is divided by the divided time. The added signal is calculated n sets including the signal without the time shift (the second signal itself), the correlation value with the first signal is calculated, and the signal most similar to the first signal is calculated. As a result, it is possible to detect and correct the time shift between the two signals with a fine precision equal to or less than the sampling period.

In the first embodiment, the arithmetic unit 7 uses linear interpolation to sequentially calculate data having a time delay or a time lead phase of a predetermined time interval with respect to the data read by the signal extractor 6. However, the same effect can be obtained by performing calculation using Lagrange interpolation, spline interpolation, or sampling theorem.

Although the arithmetic unit 7 divides the sampling cycle into n equal parts, it goes without saying that the accuracy of the time axis correction can be increased by increasing this n.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram of a time axis correction device according to the second embodiment of the present invention.

In FIG. 4, 41 and 42 are input terminals for inputting analog signals, 43 is a signal switcher for switching the signals input to the input terminals 41, 42, and 44 is the output of the signal switcher 43 to a digital signal. A / D
A converter, 45 is a signal switcher for switching and outputting the output of the A / D converter 44 in synchronization with the signal switcher 43, 4
Reference numerals 6 and 47 denote memories for storing the output of the signal switcher 45. The memory 46 stores a digital signal obtained by converting an analog signal input to the input terminal 41 into a digital signal. The memory 47 inputs the digital signal to the input terminal 42. A digital signal obtained by converting the generated analog signal into a digital signal is stored. 48 is an input device for inputting a digital signal, and 49
Is a memory for storing the output of the input device 48, 410 is a signal extractor for reading data of a predetermined length from a predetermined point of the data stored in the memory 49, 411 is a signal switcher for selecting the output of the memories 46, 47, 412 is the signal extractor 4
The signal extractor 413 reads out data of a predetermined length from the output of the signal switcher 411 from the data corresponding to the read start point of the data read from the memory 49 by the signal extractor 413 with respect to the data of the predetermined length read by the signal extractor 412. An arithmetic unit 414 for sequentially calculating data having a time delay or a time lead phase of a predetermined time interval, a memory 414 for storing data sequentially calculated by the arithmetic unit 413, and a data 415 having a predetermined length read by the signal extractor 410. And a memory 417 for storing correlation values sequentially calculated by the arithmetic unit 415 and a memory 417 for storing correlation values sequentially calculated between data having a predetermined length stored in the memory 414. The arithmetic unit 418 for calculating the maximum value of the correlation values is used by the arithmetic unit 41 to calculate the maximum correlation value determined by the arithmetic unit 417.
An output terminal for outputting the data used in No. 5 from the memory 414.

The operation of the time base correction apparatus of the second embodiment of the present invention constructed as above will be described below.

First, the analog signal reproduced from the digital source is input to the input terminal 41. Input switch 43
Inputs the analog signal input to the input terminal 41 to the A / D converter 44. The A / D converter 44 converts the input analog signal into a digital signal. The converted digital signal is switched by the signal switch 45,
It is stored in the memory 46. Next, an analog signal obtained by reproducing exactly the same portion as the above is input to the input terminal 42. The input switch 43 inputs the analog signal input to the input terminal 42 to the A / D converter 44. A / D converter 44
Converts the input analog signal into a digital signal. The converted digital signal is sent to the signal switch 4
5, and stored in the memory 47. further,
The digital signal stored in the digital source used for reproduction is input by the input device 48 and stored in the memory 49. Here, the digital data stored in the memories 46 and 47 is the same source reproduced and converted into a digital signal. However, the digital data independently converted into a digital signal by the A / D converter 44. Therefore, there is a time lag between each other and the digital signals stored in the source used for reproduction and stored in the memory 49.

Next, the signal extractor 410 reads out data having a predetermined time length from the correction start point for starting the time shift correction from the data stored in the memory 49. The signal switch 411 switches the outputs of the memories 46 and 47. That is, a signal for time axis correction is selected. Here, the operation will be described assuming that the memory 46 is selected. Then, the signal extractor 412 reads from the memory 46 the data corresponding to the data read by the signal extractor 410 from the memory 49.

Hereinafter, the arithmetic unit 413, the memory 414, the arithmetic unit 415, the memory 416, the arithmetic unit 417, and the output terminal 41.
8 performs exactly the same operation as the arithmetic unit 7, the memory 8, the arithmetic unit 9, the memory 10, the arithmetic unit 11, and the output terminal 12 in the time axis correction apparatus of the first embodiment. That is, the arithmetic unit 413 sequentially calculates data having a time delay or a time advance phase of a predetermined time interval with respect to the data read by the signal extractor 412. The calculated signal is stored in the memory 41.
4 is stored. Next, the arithmetic unit 415 is used by the signal extractor 4
Data read from the memory 49 by the memory 10 and the memory 416
Output of the arithmetic unit 415 stored in the memory, that is, the signal extractor 4
Based on the data read from the memory 46, 12 calculates a correlation value with the signal to which a predetermined time delay phase is added. The memory 416 stores this output. Then, the arithmetic unit 41
7 calculates the maximum value of the correlation values stored in the memory 416. Then, the data corresponding to the data used for the correlation processing that gives the maximum value, that is, the data stored in the memory 414 is output from the output terminal 418. That is, the output terminal 418 outputs a signal in which the time difference between the digital signal stored in the source and the signal obtained by converting the analog signal reproduced from the source into the digital signal is calculated and corrected. Even if the signal switch 411 selects the memory 47, the same processing is performed.

As described above, according to the second embodiment of the present invention, the digital signal stored in the digital source used for reproduction is used as a reference, and the sampling period for the reproduced signal of this digital source is n or the like. Then, n sets of signals including time-shifted signals (reproduced signals themselves) are calculated, and correlation values with the digital signals recorded in the source are calculated.
By calculating the signal most similar to the first signal to correct the time difference between the signal recorded in the source and its reproduction signal, the time difference with respect to the reference signal can be detected to a fine precision of the sampling cycle or less. , And it is possible to correct.

In the second embodiment, the signal switching units 43 and 45 are used for one A / D converter 44, but the number of A / D converters 44 corresponding to the input signal is used. The same effect can be obtained with the configuration in which the signal switching devices 43 and 45 are omitted.

Further, in the second embodiment, the A / D converter 44 and the input device 48 for inputting a digital signal are made asynchronous, but this is a synchronous operation, and in principle, there is no time lag. However, there is a time lag from the operating speed of the elements actually configured. However, according to the present invention, an effect of correcting this time shift can be obtained.

[0053]

As described above, according to the present invention, one of the two signals is used as a reference and a signal obtained by adding a predetermined time advance or delay phase to the other signal is calculated, and the one signal and the calculated signal are calculated. The correlation value of is calculated. Then, the signal having the maximum correlation value is used as the output signal to detect and correct the time lag between the two signals, thereby obtaining the effect of correcting the time lag below the sampling cycle of the A / D converter.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a time axis correction device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an apparatus for obtaining an input signal used for explaining the operation of the first embodiment.

FIG. 3 is a waveform diagram for explaining the operation of the first embodiment.

FIG. 4 is a block diagram showing a configuration of a time axis correction device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional two-signal waveform similarity measuring device.

FIG. 6 is a schematic diagram for explaining write / read operations in the memory circuit of the conventional example.

FIG. 7 is a characteristic diagram showing a correlation of input signals used for explaining the operation of the conventional example.

[Explanation of symbols]

 1, 2 input terminals 3, 4, 8, 10 memory 5, 6 signal extractor 7, 9, 11 arithmetic unit 12 output terminal

Claims (1)

(57) [Claims] 1. A first and second storage means for storing two time-discrete signals having a predetermined degree of similarity and having a time lag between them, and the first and second storage means. A first signal extracting means for reading a predetermined length of data from a predetermined point of the data, and a predetermined length from the data corresponding to the read start point of the data read by the first signal extracting means from the second storage means. Second signal extracting means for reading the data of the first data, and first data for sequentially calculating the data having the time delay or the time advance phase of the predetermined time interval with respect to the data of the predetermined length read by the second signal extracting means. An arithmetic means, a third storage means for storing data sequentially calculated by the first arithmetic means, a predetermined length of data read by the first signal extraction means, and the third storage means. The Second calculating means for sequentially calculating correlation values between data of a predetermined length, fourth storing means for storing correlation values sequentially calculated by the second calculating means, and fourth storing means And a third calculating means for calculating the maximum value of the stored correlation values, the data used by the second calculating means for calculating the correlation value determined to be the maximum by the third calculating means. A time axis correction device which outputs corresponding data from the third storage means.