JPH05122069A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To reduce the number of a multiplying step and the number of time sequential numerical data which is stored in ROM and also execute an interpolation with high accuracy. CONSTITUTION:A unit pulse response signal is divided into (m+1) partial signals by a time interval T, the respective partial signals are sampled by a cycle T/n so as to be stored in ROM 51a of a partial signal time sequential data generating part 51 and time sequential data of the whole partial signals are successively generated at every time interval T/n. A digital data storing part 52 successively stores the (m+1) latest kinds of data which are generated at specified time T, a digital arithmetic part 53 multiplies specified time sequential data in the respective partial signals by corresponding digital data at every T/n time so as to add multiplying result and output it, a digital data interpolating part 54 inserts one kind of interpolation data between data through the use of the four kinds of successive digital data outputted from the digital arithmetic part and a digital/analog converting part 60 converts digital data into analog data so as to output it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter, and more particularly to a digital / analog converter suitable for converting digital audio data into an analog signal.

[0002]

2. Description of the Related Art Compact disc players (CD players) and digital audio tape devices (DAT devices)
Then, the digital audio signal is converted into an analog signal and output from the speaker.

In a generally used digital-analog converter (DA converter) for reproducing music, digital data is converted into a direct current, and the current is converted into a voltage at each sampling cycle to be held. The hold voltage is shaped by a low-pass filter into a continuous smooth analog signal and is output. The most serious problem with such a DA converter for reproducing music is phase distortion due to a low-pass filter, which causes deterioration of sound quality.

Therefore, the inventors of the present invention have proposed the digital-analog converter shown in FIG. 5 as Japanese Patent Application No. 62-78878. This digital-analog converter includes a digital data generator 10 that generates digital data every predetermined time T, and a latest m + 1 generated every predetermined time T.
A shift register (11 _{0 to} 11 ₈ ) that stores (for example, m = 9) pieces of digital data V _{0 to} V ₈ while sequentially shifting them.
The digital data storage unit 11 having the configuration and the unit pulse response signal SP (see FIG. 6) are divided at a predetermined time interval T, and m + 1 analog partial signals S _{0 to} S ₈ obtained by the division are shown in FIG. As shown, the unit pulse response signal generator 12 is provided with partial signal generators (12 _{0 to} 12 ₈ ) that are repeatedly generated at each time T, each partial signal Sj, and the shift register corresponding to the partial signal. A multiplier 13 having multiplication DA converters (13 _{0 to} 13 ₈ ) for respectively multiplying predetermined digital data Vj, and a synthesizing section 14 for synthesizing output voltages of the multiplication DA converters and outputting an analog signal. Have

According to this method, it is possible to smoothly interpolate between the digital data of the period T using the pulse response signal without using a low-pass filter, and to generate a continuous analog signal without phase distortion. ..

However, the digital-analog converter of FIG. 5 requires a digital data storage unit, m + 1 analog partial signal generators, m + 1 multiplying DA converters, and an analog synthesizing unit. However, the number of parts is large and the size is large, which is not suitable for weight reduction and size reduction.
Furthermore, there is a problem that a special IC chip for a multiplication DA converter is required and the cost is considerably high. In addition, since the multiplication DA converter and the analog partial signal generator have many adjustment points by the variable volume, it requires skill for adjustment, and when readjusting due to aging or changing the unit pulse response signal waveform. Readjustment of was troublesome.

Further, since the adjustment point shifts depending on the temperature as well, if the adjustment is strictly performed according to the temperature, the adjustment work becomes more and more troublesome. In addition, each partial signal generator and multiplication type D
Since the A converter uses a large number of parts with large variations such as capacitors, there is a problem that variations easily occur, and this variation causes minute spike noise to be added to the analog signal.

Therefore, the inventors of the present application filed Japanese Patent Application No. 1-195.
724, digitally generate each partial signal obtained by dividing the unit pulse response signal into (m + 1)
The input digital data is interpolated by a plurality of digital data using the partial signal data, and the interpolated data is DA
We have proposed a digital-analog converter that outputs a continuous analog signal of input digital data by conversion. According to this digital-analog converter, it is possible to minimize the number of adjustment points and the number of variations in the analog circuit.

FIG. 8 is a block diagram of such a digital-analog converter, and 21 is the latest m generated every predetermined time T.
A digital data storage unit for storing +1 pieces of digital data Xj (j = 0 to m) while shifting them, and 22 is a unit pulse response signal SP (see FIG. 6) divided at a predetermined time interval T (m + 1) pieces. When the partial signal Sj (j = 0 to m) of
23. A partial signal time-series data generator that sequentially and repeatedly generates n time-series numerical data (see the table below) obtained by sampling each partial signal Sj (j = 0 to m) at a cycle T / n.
Is a digital arithmetic unit that multiplies the time-series numerical data of each partial signal output from the partial signal time-series data generation unit 22 and the digital data corresponding to the partial signal, and adds the multiplication results. It is a digital-to-analog converter that converts to.

[0010]

[Table 1]

In the digital data storage unit 21, M ₀
~Mm shift register for storing while sequentially shifting the m + 1 of the latest digital data Xj generated every time interval T, the digital arithmetic unit 23, K0~Km predetermined time T of the partial signals S ₀ to S ₈ The time-series numerical data c _0i , c _1i , c _2i , c _3i , ..., C _mi at i / n and the digital data X 0 to Xm stored in the shift register corresponding to each partial signal are timed. A multiplier that multiplies every T / n, and SUM is an adder that adds multiplication results,
From the adder, digital data Y _{i represented} by the following formula Yi = C _0i · X ₀ + C _1i · X ₁ + C _2i · X ₂ + C _3i · X ₃ + ... + C _mi · X _m (i = 1 to n) Is output every T / n.

Therefore, in FIG. 8, n = 4 and m = 2, and four time series numerical data of the three partial signals S _{0 to} S ₂ are S ₀ : c ₀₁ , c ₀₂ , c ₀₃ , c ₀₄ S. _{1: c 11, c 12,} c 13, c 14 S 2: if _{c 21, c 22, c 23} , c 24, by one unit the digital data input, Fig. 9
The time series data of the unit pulse response signal SP shown in (a) is sequentially output from the adder SUM of the digital operation unit 23.

When a digital data string Xj having a cycle T is input as shown in FIG. 9B, data strings Y _{1 to} Y interpolated at time intervals T / 4 as shown in FIG. 9C. ₄ is sequentially output from the adder SUM of the digital arithmetic unit 23. Assuming that the digital data in each time slot Tj for each time T is Xj, the continuous time signal AS for the input digital data is a pulse response signal MRj weighted by each digital data Xj input moment by moment along the time axis. Obtained by overlapping.

The data sequence MRj of the pulse response signal for each digital data Xj is the time-series numerical data (FIG. 9 (a)) of the unit pulse response signal multiplied by Xj (FIG. 9 (c)).
), If these are sequentially combined at every time T / 4, Y ₁
.., Y ₄ , the input data having the time width T can be interpolated at the time interval T / 4.

[0015]

As described above, in FIG. 8, the analog circuit portion can be minimized, that is, except for the digital-analog conversion portion 24, the rest can be configured by digital. Therefore, the digital storage unit 21, the partial signal time series data generation unit 22, and the digital operation unit 23 are configured by a digital signal processor (DSP).

By the way, the digital-to-analog converter is required to reproduce an original signal (for example, an audio signal) with high accuracy. Therefore, it is possible to interpolate between input digital data of a cycle T at a time interval T / 16. Is required. In order to create such high-precision multi-interpolation data with the digital-analog converter of FIG. 8, it is necessary to set m = 8 (unit pulse response signal is divided into 9) and n = 16 (each partial signal is 16 samples). is there.

Therefore, the digital-analog converter shown in FIG. 8 requires 16 × 9 multiplication steps during the time T, which causes a problem that the calculation speed of the DSP cannot be in time.

Further, each partial signal S₀~ S_mTime series of (m = 8)
As the column numerical data, the following c₀₁, C₀₂, C₀₃, ..., c_0n; C₁₁, C₁₂, C₁₃, ..., c_1n  c_{twenty one}, C_{twenty two}, C_{twenty three}, ..., c_2n  c₃₁, C₃₂, C₃₃, ..., c_3n  ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ C_m1, C_m2, C_m3, ..., c_mn n · (m + 1) (= 16 × 9) data when partial signal
Must be stored in the ROM in the series data generator 22
Therefore, a large ROM is required, resulting in high cost.

From the above, the object of the present invention is to provide a calculation step,
In particular, it is an object of the present invention to provide a digital-analog converter which can reduce the number of multiplication steps and the number of time-series numerical data stored in ROM and can perform highly accurate interpolation.

[0020]

SUMMARY OF THE INVENTION According to the present invention, the above-mentioned object is to provide a unit pulse response signal at a predetermined time interval T of (m +
1) a partial signal time-series data generating section that divides into n partial time-series data and digitally repeatedly generates n time-series data obtained by sampling each partial signal at a cycle T / n;
A digital data storage unit for sequentially storing the latest (m + 1) digital data generated at every predetermined time T, n time-series data in each partial signal, and digital data corresponding to each partial signal are T / n. By using the digital operation unit that multiplies at each time and adds and outputs the multiplication result, and the continuous four digital data output from the digital operation unit, one interpolation data is created between two intermediate data. This is achieved by at least one digital data interpolating unit that interpolates sequentially and a converter that converts the digital data output from the digital data interpolating unit into analog.

[0021]

The function of unit pulse response signal is (m
+1) partial signals, and each partial signal has a period T / n.
RO of the partial signal time series data generation section after sampling at
It is stored in M, and the time series data of all partial signals are sequentially and repeatedly generated from the ROM at every time interval T / n. Further, the digital data storage section sequentially stores the latest (m + 1) pieces of digital data generated every predetermined time T. The digital arithmetic unit multiplies predetermined time series data in each partial signal read from the ROM and digital data corresponding to the partial signal at every T / n time, adds the multiplication results, and outputs the result. The data interpolating unit interpolates one interpolation data between two intermediate data using four consecutive digital data output from the digital computing unit, and the DA converting unit outputs from the digital data interpolating unit. Converts digital data to analog and outputs.

According to this digital-analog converter,
In the digital operation unit, the time interval T /
n is interpolated, one interpolation data is interpolated between the data by the digital data interpolator, and the total time interval T / (2.
In n), it is possible to interpolate between the input data of cycle T. Therefore, to interpolate the input data with the time interval T / (2 · n),
Since it suffices to interpolate at the time interval T / 8 in the digital operation unit, n = 8 can be set, and the number of multiplications in the digital operation unit is 8
(M + 1) (72 times when m = 8), and the number of multiplication steps can be reduced as compared with the configuration of FIG. Further, the number of time-series numerical data stored in the ROM can also be set to 8 · (m + 1), which decreases. Further, since the digital data interpolating section uses two data each before and after the creation of the interpolated data, it can interpolate smoothly, that is, with high accuracy.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (a) Overall configuration of a first embodiment of the present invention FIG. 1 is a configuration diagram of a first embodiment of the present invention, in which a time interval T / 16 is interpolated between input data of a cycle T. is there. 5
0 is a DSP that interpolates between input data at time interval T / 16
A digital signal processing block having a configuration, 60 is a DA conversion unit for converting digital data output from the digital signal processing block into analog, and 70 is a buffer circuit.

In the digital signal processing block 50,
Reference numeral 51 denotes a partial signal time-series data generator, which divides the unit pulse response signal SP (see FIG. 2) into nine partial signals S _{0 to} S ₈ at a predetermined time interval T, and divides each partial signal into a cycle T. /
The time-series data (see the table below) obtained by sampling at n is stored in the built-in ROM 51a, and the time-series data of all partial signals are sequentially generated from the ROM at every time interval T / n. The digital signal processing block 50
First interpolates between input data at time interval T / 8, then interpolates one interpolation data between each data, and interpolates at total time interval T / 16. Therefore, n =
In the table below, each partial signal is sampled every T / 8.

[0025]

[Table 2]

Reference numeral 52 denotes a digital data storage unit for sequentially storing the latest 9 pieces of digital data X _{0 to} X ₈ generated at every predetermined time T, and the 9 pieces of latest digital data X _{0 to} X _8.
Shift registers M _{0 to} M ₈ for sequentially storing
Is equipped with.

Reference numeral 53 is a digital signal which multiplies predetermined time series data c _{0i to} c _8i in each partial signal and corresponding digital data X _{0 to} X ₈ every T / n time, adds the multiplication results, and outputs the result. an arithmetic unit, K0～Km each partial signal S ₀ to S ₈
Digital data X _{0 to} X stored in the time series numerical data c _0i , c _1i , c _2i , c _3i , ..., C _8i and the shift registers M _{0 to} M ₈ at a predetermined time T · i / 8 of SU, a multiplier for multiplying ₈ and ₈ at time T / 8
M is an adder for adding the multiplication results, which is expressed by the following formula Yi = C _0i · X ₀ + C _1i · X ₁ + C _2i · X ₂ + C _3i · X ₃ + ... + C _8i · X ₈ Numerical data is output at every time interval T / 8.

Reference numeral 54 is a digital data interpolating unit for sequentially interpolating one interpolation data between two intermediate data by using four continuous digital data output from the digital arithmetic unit 53. As shown in FIG. 3, data values of four consecutive points t _i−1 , t _i , t _{i + 1} , t _{i + 2} are g (t _i−1 ), g
When (t _i ), g (t _{i + 1} ), g (t _{i + 2} ), the two central points t _i , t
The interpolation value g (t _m ) at the intermediate point t _m of _{i + 1} is expressed by the following equation g (t _m ) = [g (t _i ) -g (t _i-1 ) + g (t _{i + 1} ) -g ( t _{i + 2} )] / 2 ² + [g (t _i ) + g (t _{i + 1} )] / 2 = + {1/2 ¹ +1/2 ⁴ } ・ g (t _i ) + {1/2 ¹ +1/2 ⁴ } ・g (t _{i + 1} )-{1/2 ⁴ } .g (t _{i + 2} )-{1/2 ⁴ } .g (t _i-1 ) ... (1)

By doing so, since four data near the interpolation point are used, highly accurate interpolation data can be obtained. That is, compared with the case where the weighted average value is used as the interpolation data using the data g (t _i ), g (t _{i + 1} ) of the two points t _i , t _{i +1} on both sides of the intermediate point t _m , Highly accurate interpolation data can be obtained. Therefore, the digital data interpolator 54 performs the calculation of the equation (1) to interpolate one interpolation data between the input data. It should be noted that the calculation of equation (1) requires four multiplication steps.

Overall Operation In advance, the unit pulse response signal SP (FIG. 2) is divided into nine partial signals S _{0 to} S ₈ at a predetermined time interval T, and each partial signal is sampled at a cycle T / 8. It is stored in the ROM 51a of the partial signal time series data generation unit 51, and the time series data of all the partial signals S _{0 to} S ₈ are sequentially and repeatedly generated from the ROM at every time interval T / n. That is, at time T / 8, c ₀₁ , c ₁₁ , c ₂₁ , c ₃₁ , ..., C ₈₁ are output, and at time 2T / 8, c ₀₂ , c ₁₂ , c ₂₂ , c ₃₂ ,. , C _82, and similarly, at times i · T / 8, c _0i , c _1i , c _2i , c _3i , ..., C _8i are output.

On the other hand, the digital data storage section 52 stores the latest nine pieces of digital data X _{0 to} X ₈ generated every predetermined time T.
Are sequentially stored in the shift registers M _{0 to} M ₈ while being shifted. The multipliers K _{0 to} K ₈ of the digital arithmetic unit 53 are the ROM 5
1a, time-series data c _0i , c _1i , c _2i , c _3i , ..., C _8i (i = 0 to 0) of the partial signals S _{0 to} S ₈
8) and the digital data X _{0 to} X ₈ corresponding to the partial signal are multiplied every T / n time, and the adder SUM adds the multiplication results and outputs the total value Yi. If the above processing is performed in the T / 8 cycle, the input digital data of the cycle T can be interpolated at the time interval T / 8.

The digital data interpolator 54 performs the operation of the equation (1) using the continuous four digital data output from the digital operation part 53 to obtain one interpolated data between the two intermediate data. Interpolate. Interpolation data is interpolated between any two pieces of data in the same manner.

As described above, the input digital data of the cycle T can be totally interpolated at the time interval T / 16. Thereafter, the DA converter 60 converts the digital data output from the digital data interpolator 54 into analog and outputs the analog data via the buffer circuit 70.

Examination of the number of multiplications According to the digital-analog converter of the present invention, the digital arithmetic unit 53 interpolates at the time interval T / 8, and the digital data interpolating unit 54 inserts one interpolation data between the input data. And interpolate at a total time interval of T / 16. Therefore, the number of multiplications n × (m + 1) in the digital arithmetic unit 53 is 8 × 9 (= 72), and the number of multiplication steps can be reduced by half compared to the configuration of FIG.

On the other hand, in the digital data interpolation section 54, 1
Four multiplication steps are required to interpolate one interpolation data, and eight interpolation steps are required during the time T, so a total of 4 × 8 (= 32) multiplication steps are required.

From the above, in the present invention, the time interval T /
The number of multiplications for interpolation by 16 is 72 + 32 = 104, and the number of multiplications 16 × 9 = 144 in the case of FIG.
Can be significantly reduced compared to times.

(B) Another Embodiment of the Present Invention In the embodiment shown in FIG. 1, the digital arithmetic unit 53 interpolates the input data of the period T at time intervals T / 8, and the digital data interpolating unit 54 makes one The interpolation data is interpolated and totally interpolated at the time interval T / 16, but as shown in FIG.
The digital arithmetic unit 53 interpolates at time intervals T / 4, the first digital data interpolating unit 55 interpolates one interpolation data, the second digital data interpolating unit 56 interpolates one interpolation data, Totally between input data of cycle T is T /
It can also be configured to interpolate with 16.

In this way, the number of multiplications is 4 × 9 = 36 in the digital arithmetic unit 53, 4 × 4 = 16 in the first digital data interpolating unit 54, and in the second digital data interpolating unit 55. 4 × 8 = 32 times are required, which is a total of 84 times, and the number of multiplication steps can be greatly reduced.

The present invention has been described above with reference to the embodiments.
The present invention can be variously modified according to the gist of the present invention described in the claims, and the present invention does not exclude these modifications.

[0040]

As described above, according to the present invention, the digital arithmetic unit interpolates the input data of the cycle T at the time interval T / n, and the digital data interpolating unit interpolates one interpolation data between the input data. Since the total interpolation is performed at the time interval T / (2 · n), the number of multiplications in the digital calculation unit can be significantly reduced, and the data interpolation processing can be performed with a margin.

Further, according to the present invention, since the interpolation cycle in the digital operation section can be doubled as compared with the conventional one, the number of time-series numerical data stored in the ROM of the partial signal time-series data generating section can be reduced by half, and the ROM capacity can be reduced. Can be reduced. Furthermore, according to the present invention, since the digital data interpolating section uses two pieces of data each before and after the creation of the interpolation data,
Interpolation data can be interpolated with a smooth connection, that is, with high accuracy. Further, if the digital data interpolating units are arranged in cascade, the number of multiplications and the number of time series numerical data can be further reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of time series numerical data in a partial signal.

FIG. 3 is an explanatory diagram when one interpolation data is interpolated between data.

FIG. 4 is a configuration diagram of another embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional digital-analog converter.

FIG. 6 is a waveform diagram of a unit pulse response signal.

FIG. 7 is a partial signal waveform diagram.

FIG. 8 is a configuration diagram of another conventional digital-analog converter.

FIG. 9 is an explanatory diagram of conventional digital-analog conversion.

[Explanation of symbols]

 50 .. Digital signal processing block 51 .. Partial signal time series data generation unit 52 .. Digital data storage unit 53 .. Digital operation unit 54 .. Digital data interpolation unit 60 .. DA conversion unit

Claims (1)

[Claims] 1. A unit pulse response signal is transmitted at a predetermined time interval T.
(M + 1) partial signals, each partial signal is sampled at a cycle T / n and stored in a memory, and the time-series data of all partial signals is sequentially stored from the memory at each time interval T / n. A partial signal time-series data generation unit that repeatedly generates, a digital data storage unit that sequentially stores the latest (m + 1) digital data that is generated at predetermined time intervals T, and n time-series data and partial data in each partial signal. Digital data corresponding to the signal is multiplied every T / n time, and the digital operation unit that adds and outputs the multiplication result and four consecutive digital data output from the digital operation unit are used to interleave the data. At least one digital data interpolating unit that sequentially interpolates one interpolation data, and a converter that converts the digital data output from the digital data interpolating unit into analog should be provided. Digital-to-analog converter according to claim.