JP2542375B2 - Operational amplifier - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary MOSFET operational amplifier having a large current drive capability and a wide output voltage range and having a sufficient phase margin.

[Prior Art] Recently, C has a simple process and consumes less current.
-Digital / analog devices using MOS process technology,
In particular, a so-called class AB or class B operational amplifier, which has a large current driving capability and consumes little current when there is no input, has been receiving attention.

FIG. 3 is a circuit example of a conventional class B operational amplifier. Third
In the figure, 81 to 91 are MOSFETs, and 92 and 93 are inputs.
Input terminal pair supplied with V _in − and V _in + respectively, 94
Is an output terminal for taking _{out the} output V _out , 95 is a terminal for supplying a bias voltage, 96 and 97 are positive and negative power supply lines, respectively, and 98 and 99 are capacitors and resistors for phase compensation, respectively.

In the circuit of FIG. 3, MOSFETs that form the output stage
The input voltage difference applied to 90, 91 is
The value is V _TN + V _TP + Δ. here
V _TN and V _TP are the threshold voltages of MOSFETs 87 and 88, and △ is MO
It is a voltage value determined by the current flowing through the SFETs 87 and 88.
That is, with such an output means, when no load is applied, the MO
Since V _TN + V _TP + △ is applied as an input between the input gates of SFET90 and 91, and △ which is obtained by subtracting the threshold voltage is the actual input gate voltage, it consumes a minute current. I'm just there.

However, when a load is present and current is supplied to this load, the voltage input to the output stage is a constant voltage difference V _TN + V
_{Since the} voltage level is shifted upward or downward while maintaining _TP + Δ, one of the MOSFETs 90 and 91 supplies a large current, but the other MOSFET is cut off. That is, the operational amplifier shown in FIG. 3 operates in a so-called quasi-B class.

However, due to the structural reasons of the MOSFETs 90 and 91 that constitute the output stage buffer section of the circuit of FIG. 3, the output voltage range is P-type MOSFET and N-type for the positive power supply V _DD and the negative power supply V _SS . Each threshold voltage of MOSFET as V _TP and V _TN
Limited to V _DD −V _TN −Δ ₁ to V _SS + V _TP + Δ ₂ . The reason is that P-type MOSFET 91, N-type which constitutes the output buffer section.
In the MOSFET 90, at a high output voltage, that is, at an output voltage near V _DD , the gate-source voltage of the MOSFET 90 becomes V _TN or less, and the MOSFET 90 is cut off and does not function as an output stage. That is, in the output stage, the output voltage is V _SS + V
There is a problem that it is limited to the range of _TP + △ ₂ to V _DD − V _TN − △ ₁ .

Here, Δ ₁ and Δ ₂ are given by the following equations (1) and (2).

Where C _OX is the gate-bulk capacitance, μ _n and μ _p are carrier mobilities, W is the gate width, L is the gate length,
i _n and i _p are currents flowing through the n-type MOSFET and the p-type MOSFET, respectively.

FIG. 4 shows a conventional circuit example of a class AB operational amplifier in which the output voltage range, which was a drawback of the circuit of FIG. 3, is improved.

In FIG. 4, 10 to 21 are MOSFETs, and 22 and 23.
Is a pair of input terminals supplied with inputs V _in − and V _in +, 24 is an output terminal for taking _out output V _out , 25 is a terminal for supplying bias voltage, 26 and 27 are positive and negative power supply lines, 28 and Reference numerals 29 are capacitors and resistors for phase compensation, respectively.

Here, MOSFETs 10-14 form a differential amplifier 60 for inputs V _in − and V _in +. MOSFETs 15-17 are MOSFET 11
A level inverting unit 61 that inverts the level of the output of the differential amplifier 60 taken out from the terminal 30 at the connection point with 13 is configured. MOSF
The ETs 18 and 19 configure a level shifter circuit unit 62 that changes the operating point level of the output from the level inverting unit 61. MOSFET
Numerals 20 and 21 are MOSFETs of opposite conductivity type, and the output terminal 30 of the differential amplifier section 60 and the output terminal 31 of the level shifter circuit section 62 are connected to each gate to form an inverting output amplifier section 63. , Output from its output terminal 24.

In the circuit of FIG. 4, the level inversion unit 61 including the MOSFETs _{15 to 17} has a current value i ₁₅ , i ₁₆ and i ₁₇ flowing through the MOSFETs _{15 to 17.}
Operates so as to maintain the relation that i ₁₇ = i ₁₅ + i ₁₆ . Here, since i ₁₇ is a constant value, if i ₁₅ increases, i ₁₆ decreases, i ₁₅
If decreases, i ₁₆ increases. Also, MOSFETs 16 and 18 and MOSFE
Since T19 and T21 respectively form a current mirror circuit, i ₁₆ and the current i ₂₁ flowing through the MOSFET ₂₁ are proportional to each other.

On the other hand, since the gate voltages of the MOSFETs ₁₅ and ₂₀ are common at the terminal 30, the current values i ₁₅ and i ₂₀ flowing through the respective MOSFETs are proportional.

That is, this operational amplifier operates in class B and can save current consumption.

[Problems to be Solved by the Invention] However, a MOSFET is generally inferior to a bipolar transistor in current mirror circuit characteristics and in matching between devices, and a current value as designed may not be achieved. For example, it is desirable that i ₂₀ and i ₂₁ are as small as possible when there is no signal, but since i ₂₀ is almost zero, i ₂₁ may be zero when i ₂₀ is almost zero. In this case, there is no phase margin at the output terminal 24, and if negative feedback is applied to the operational amplifier, the operational amplifier will oscillate or become unstable.

Further, if i ₁₇ is set to a large value in order to avoid the above problem, there is a drawback that the current consumption increases.

Therefore, an object of the present invention is to provide an operational amplifier having a large current drive capability, reducing current consumption under no load, having a wide output voltage range and having a sufficient phase margin.

[Means for Solving the Problems] In order to achieve the above-mentioned object, an operational amplifier according to the present invention is provided with a differential input, a differential amplifying means for amplifying the differential input, and the differential amplifier. Level inverting means for inverting the level of the output from the amplifying means; level shifter means for changing the operating point level of the output from the level inverting means when supplied with the output from the level inverting means;
An operational amplifier including: output of the differential amplification means and output of the level shifter means to each gate of the conductivity type MOSFET, and output amplification means for amplifying the output of the differential amplification means. Bias means for generating the bias current of the level inversion means, and adds the bias current to the current flowing through the level shifter means in accordance with the output of the level inversion means,
It is characterized in that a current corresponding to the bias current is passed through one of the MOSFETs.

[Operation] According to the present invention, the bias current is made to flow through the MOSFET in the level shifter means and one of the output amplification means by the bias means, so that the output amplification means can be provided in any input state of the operational amplifier. Constituting MOSFET
The value of the current flowing through either one of them is not always zero.
That is, when negative feedback is given to the operational amplifier, the pole that causes oscillation can be removed, and a stable operational amplifier with a sufficient phase margin can be provided.

[Examples] Hereinafter, the present invention will be described in detail with reference to the drawings.

 An embodiment of the operational amplifier according to the present invention is shown in FIG.

In FIG. 1, similar parts are designated by the same reference numerals, and detailed description thereof will be omitted here. Reference numerals 40 to 42 are MOSFETs, which form a bias circuit section 64.

That is, the circuit of FIG. 1 has the same configuration as that of FIG. 4 except that the bias circuit section 64 is newly added to the circuit of FIG. Therefore, the operational amplifier shown in FIG. 1 has the advantages that the current consumption can be saved when there is no input and the output voltage range can be widened, like the operational amplifier shown in FIG.

In the bias circuit section 64, the MOSFETs 40 and 41 form a current mirror circuit, and the bias of the current mirror circuit is given from the MOSFET 42. A constant level bias current extracted from the MOSFET 41 via the terminal 43 is supplied to the MOSFET 18 of the level shifter circuit unit 62 for changing the operating point level.
Supply at connection point 44 with 19. Here, since the MOSFETs 19 and 21 form a current mirror circuit, a bias current also flows to the one MOSFET 21 of the output amplifier 63.

As described above, since the circuit of the embodiment shown in FIG. 1 has the bias circuit section 64, the current flowing through the MOSFET 20 of the output amplification section 63 does not become zero in any state.
The reason is that the current through MOSFET 19 is
This is because the bias current is constantly flowing in the MOSFET 41 due to a constant bias voltage. Therefore, a current always flows through the MOSFET 21, which forms a current mirror together with the MOSFET 19, the output terminal 24 never enters the so-called high impedance state, and has a certain stable terminal potential V _out .

The operation of the operational amplifier of the present invention will be described in more detail with reference to FIG.

FIG. 2 is an equivalent circuit diagram of the operational amplifier of FIG. 1 or 4 at the time of a small signal. Each signal in the figure is the first
Description will be made in association with the circuit diagram of the operational amplifier in the figure.

g _m1,, g _m2 , g _m3 , g _m4 , g _m5 , g _m6 , g _m7 are MOSFET 13,1 respectively
5,16,18,19,20,21 transconductance (g _m = di _ds
/ dV _gs ). r _o1 , r _o2 , r _o3 , r _o4 , r _o5 , r _o6 , r _o7 are the output impedances (r _o = di _ds / dV _gs ) of _{MOSFETs 13,11,15,17,18,20,21} , respectively. . r ₁ and C _c are a resistor 28 and a capacitor 29 for phase compensation, respectively.

The ratio of the output signal V _out to the input signal V _in of this equivalent circuit, that is, the transfer function H (s) can be described as in Expression (1).

Here, D (s) and D _k (s) are expressed by the following equations (2) and (3), respectively.

D (s) = (g _m3 + r _o3 ^-1 + r _o4 ^-1 + sC ₂ ) [(sC _c + sC ₁ +
^{_{r o1 -1 + r o2 -1)}} (g m5 + r o4 -1 + sC 2) (r o6 -1 + r o7 -1 + s
C ₄ + sC _c ) + sC _c (g _m5 + r ₀₄ ^-1 + sC ₃ ) (g _m6 −sC _c )] + s
C _c g _m2 g _m4 g _m7 (2) D _k (s) = g _m1 {(g _m3 + r _o3 ^-1 + r _o4 ^-1 + sC ₂ ) (g _m5 + r
_o4 ⁻¹ + sC ₃ ) (g _m6 −sC _c ) + g _m2 g _m4 g _m7 } (3) In the formulas (2) and (3), g _m1 >> r _oi ⁻¹ (i = 1,2 ...,
Assuming 7), these equations (2) and (3) can be rewritten as the following equations (4) and (5).

D (s) = (g _m3 + sC ₂ ) [(sC _c + sC ₁ + r _o1 ^-1 + r _o2 ^-1 )
(G _m5 + sC ₃ ) (r _o6 ^-1 + r _o7 ^-1 + sC ₄ + sC _c1 ) + sC _c (g _m5
+ SC ₃ ) (g _m6 + sC _c )] + sC _c g _m2 g _m4 g _m7 (4) D _k (s) = g _m1 {(g _m3 + sC ₂ ) (g _m5 + sC ₃ ) (g _m6 −s
C _c ) + g _m2 g _m4 g _m7 (5) Here, in the circuit of FIG. 1, the differential input voltage at the input terminals 22 and 23 is applied, and as a result, the current i ₃ flowing through the MOSFET 16 becomes zero. I will describe the case.

At this time, the current i ₄ flowing through the MOSFET 18 also becomes zero. In equations (4) and (5), i ₃ = i ₄ = 0, that is, g _m3 = g _m4
The transfer function when = 0 is given by equation (6).

Here, if the influence of the phase compensation resistor r _c and the condition of r _c g _m6 = 1 are entered, H (s) can be expressed as in equation (7).

In general, since | s ₁ | <| s ₂ |, s ₁ is a dominant pole and s ₂ is an dominant pole, which characterizes the transfer characteristic when g _m3 = g _m4 = 0 in the operational amplifier of this embodiment. It will be.

Here, when i ₃ = i ₄ = 0, i ₁ = i ₂ = i depending on the offset voltage caused by the imbalance of the differential input section or the influence of the deviation in the process of each MOSFET used for the current mirror. It is possible that ₆ = 0.

At this time, in the conventional circuit of FIG. 4, i ₃ = i ₄
Since = 0, i ₅ = i ₇ = 0 at the same time. This is MO
This is because the SFETs 19 and 21 each form a current mirror circuit.

Therefore, g _m6 = r _o1 ^-1 = r _o2 ^-1 = r _o6 ^-1 = r _o7 ^-1 = 0 and s ₁ = s ₂ = 0. In other words, the positions of the two poles overlap and the phase shifts by 180 °, resulting in an operational amplifier with no phase margin. Since the DC gain in this case is infinite, it has a function as an amplifier.

As described above, the circuit of FIG. 4 has a drawback that the stability of the circuit is impaired when both the MOSFETs 19 and 21 are in an operation state close to OFF.

On the other hand, in the circuit of the first embodiment of the present invention, the bias circuit section 64 can maintain the minimum bias current for the MOSFET 19, so that the MOSFET 21 can also maintain the minimum bias current. Therefore, i ₁ = i ₂ = i ₃ = i ₄ = i ₆ = 0
In such a case, i ₇ ≠ 0 and r _o7 ⁻¹ ≠ 0.

In this case, the two poles in equation (7) are s ₁ = 0,
Since s ₂ ≠ 0, there is no overlap. That is, by appropriately adjusting the bias current, an operational amplifier having a sufficient phase margin can be constructed.

The present invention is not limited to the embodiment shown in FIG. 1, and is constituted by, for example, only the MOSFET 41 of the bias circuit section 64, and the gate voltage for this MOSFET 41 may be supplied from another circuit or externally supplied. You may

[Effects of the Invention] As is apparent from the above, according to the present invention, it is possible to perform a class B operation and have a sufficiently wide output voltage range,
Moreover, it is possible to realize a stable operational amplifier having a sufficient phase margin even if a process variation occurs.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the operational amplifier of the present invention, FIG. 2 is a small signal model diagram of the circuit shown in FIG. 1 or 4, and FIG. 3 is an example of a conventional class B operational amplifier. FIG. 4 is a circuit diagram showing another example of a conventional class B operational amplifier. 26,27,96,97 …… Positive / negative power supply line, 25,95 …… Bias terminal, 10 to 21,40 to 42,81 to 91 …… MOSFET.

Claims (1)

(57) [Claims] 1. A differential amplifier which is supplied with a differential input and amplifies the differential input, a level inverting unit which inverts the level of the output from the differential amplifier, and an output from the level inverting unit. And level shifter means for changing the operating point level of the output from the level inverting means, and outputs from the differential amplifying means and the level shifter means to the gates of the first and second conductivity type MOSFETs, respectively. An operational amplifier having an output amplifying means for supplying and amplifying an output from the differential amplifying means, a bias means for generating a bias current of a constant level, and a level shifter means according to an output of the level inverting means. The bias current is added to the flowing current, and a current corresponding to the bias current is caused to flow through one of the MOSFETs in the output amplification means. Operational amplifier.