JP2541186B2 - Automatic phase adjustment circuit - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview page 3 Industrial field of application page 3 Conventional technology page 10 Problems to be solved by the invention page 11 Means for solving problems page 12 Action 14 pages Example Page 21 (a) First embodiment of the present invention Page 21 (b) Second embodiment of the present invention Page 34 [Outline] For a data discriminating circuit that discriminates and outputs data by a window that is in phase synchronization with input data. Of the automatic phase adjustment circuit, the test data generating section for generating a test data sequence by shifting the phase of one data of the input data sequence, and the discrimination obtained as an output by inputting the test data sequence into the data discrimination circuit. By providing a detection unit that detects an irregular phase of data and an adjustment unit that automatically adjusts the delay time of the variable delay circuit, the phase shift between the input data and the window is automatically detected and adjusted. .

[Industrial applications]

The present invention relates to a data discriminating circuit for discriminating input data using a clock phase-synchronized with the input data as a window, and an automatic phase adjusting circuit for automatically detecting and adjusting a phase shift of the window (clock) with respect to the input data. Regarding

A data discrimination circuit that discriminates input data with a clock synchronized with the input data and outputs the discrimination data is widely used. For example, in a read system of a magnetic disk device, a signal read by a magnetic head from a magnetic disk is amplified by an amplifier, and AGC (automatic gain control)
The circuit keeps the amplitude constant, the filter removes unnecessary high-frequency noise, and the A / D (analog / digital) converter converts it to binarized pulses for use as input data for the data discrimination circuit.

In this description, it is assumed that one pulse is one data, and the input data sequence is this data (pulse) sequence. In particular, when focusing on one data, it will be referred to as a data pulse hereinafter.

The data discrimination circuit (hereinafter abbreviated as DDC1) is generally a second
With the configuration shown in the figure, a PLL (phase-locked loop) circuit (hereinafter abbreviated as PLL) 8 is used as a phase synchronization circuit that follows the phase of the input data. A clock that is phase-synchronized with the average timing of the data pulse is created, and this is used as a window to discriminate the input data by a data discriminator (hereinafter abbreviated as DD) 9 to obtain output data synchronized with the clock. ing.

The variable delay circuit (hereinafter abbreviated as DLY) 5 generally has a variable delay time and is for adjusting the relative phase of the clock output from the PLL 8 and the input data.
It's in front of L8, but it can be in front of DD9 or both.

The data discriminating circuit DDC1 is an object to be phase-adjusted by the automatic phase adjusting circuit of the present invention and is not the content of the present invention, but an example in which the phase relationship is simplified in advance to simplify the following description. I will explain it and put it.

FIG. 3 shows an example thereof. In the figure, DI is the input data, DL is the output of the delay circuit DLY5, W is the window created by the PLL8 clock that synchronizes with the phase of the input data DI, and DO is the discriminator DD9 that receives the input data through the window W. The output waveform as a result of discrimination is shown. Tw is the window period (width), Td is the delay time, Tp is the leading edge of the window and the leading edge of the data pulse of the normal phase of input data DI (average phase without jitter). Indicates the time interval of.

In this example, the data pulse of the input data DI arrives at a cycle three times the window cycle Tw, and the relative phase between the window and the input data is at the center of the window before the data pulse of the normal phase of the input data. It shows a case where Td is adjusted by DLY5 so that the edge comes (2Tp = Tw). It is assumed that the windows are therefore given the repetition numbers 0, 1 and 2 so that the data pulse having the normal phase is discriminated at the center of the window 0.

The numbers attached are numbers indicating individual data pulses of the input data DI, and indicate normal phase data pulses, indicate data pulses leading the normal phase, and indicate data pulses delayed from the normal phase. In the following description, the 0 level of the waveform will be referred to as the L level and the 1 level will be referred to as the H level because it relates to digital signals.

Explaining the state of phase synchronization, the leading edge of the output waveform of DLY5 is synchronized with the leading edge of the data pulse of each individual input data DI, and the waveform reaches the trailing edge after maintaining the H level for the delay time Td. Give rise to DL.

The window W shows the input data as indicated by the double arrow.
DL corresponding to the data pulse (,) of the DI normal phase, which corresponds only to the trailing edge of the DL waveform and corresponds to the data pulse (,) that is not in the normal phase, that is, the phase is shifted due to jitter or the like.
It is not synchronized with the trailing edge of the waveform.

This is due to the remarkable characteristic of the PLL circuit, that is, in general, the PLL circuit synchronizes with the average phase of the input data pulse (and therefore also the period), and the phase due to occasional jitter or the like may occur. This is because it has the property of not following a shifted data pulse.

The output data DO is output in a cycle corresponding to the window immediately after the window in which the data pulse of the input data is discriminated. Therefore, if the numbers are assigned corresponding to the window numbers, the result is as shown in the figure.

3 (a), (b) and (c) show that when the phase shift of the data pulse of the input data DI is smaller than (1/2) Tw and equal to (1/2) Tw, respectively, The case is larger than (1/2) Tw.

In the same figure (a), the leading edge of the data pulse is in the window 0, and therefore the output data DO data pulse is 0. In the same figure (c), the leading edge of the data pulse is within the window 2, so the data pulse of the output data DO is 2, and conversely, the leading edge of the data pulse is the window 1
Therefore, the data pulse of the output data DO becomes 1.

In the same figure (b), since the leading edge of the data pulse comes to the boundary between window 2 and 0, there are cases where it is discriminated by window 2 (shown by a dotted line) and when it is discriminated by window 0 (shown by a solid line). However, the probability that 50% will occur for 50% of the output data will appear for 50% of the output data, and the leading edge of the data pulse will come to the boundary between window 1 and 0, so if it is discriminated in window 1 ( (Indicated by dotted lines) and window 0
If it is discriminated by (indicated by the solid line), it will occur at a probability of 50%, and the output data will also appear at 50% of 1,0.

The phase shift of the data pulse of the input data due to jitter or the like, such as the data pulse shown in FIG.
Generally, both the leading phase and the lagging phase occur equally when viewed stochastically around the phase.

In order to maximize the permissible range without biasing to any phase difference between the advanced phase and the delayed phase, in this case, Tp = (1 /
2) Must be Tw. The adjustment setting of the delay time Td so that the leading edge of the data pulse of the normal phase of the input data DI comes to the center of the window W is due to such a request.

As described above, in the data discriminating circuit DDC1 including the PLL8 and the data discriminator DD9, the relative phase between the input data DI and the clock (window) CL is set in advance, and the jitter of the input data is generally set. It is desirable to set the phase relationship such that Tp = (1/2) Tw in the example of FIG. Therefore, the phase relationship of the clock with respect to the input data DI must always be adjusted to the optimum relative phase.

[Conventional technology]

In the data discriminating circuit DDC1 including the PLL8 and the data discriminator DD9, the detection display of the phase shift is necessary to perform the adjustment setting of Td by DLY5 for the Tp setting for the normal input data as described above.

However, there is no simple and appropriate method, and input data DI and clock CL are used with the conventional measuring instruments such as oscilloscope.
The delay time Td of DLY5 was adjusted by visually observing the waveform of the window W and visually observing the phase shift, and automatic adjustment was not desirable.

However, the method based on the waveform observation using the oscilloscope has an advantage that the relative phase between the input data DI and the window W can be arbitrarily adjusted and set if necessary.

[Problems to be solved by the invention]

Conventionally, the adjustment of the window phase of the data discriminating circuit has been rarely necessary after the factory adjustment in the reading system of the magnetic disk device, etc.

However, in recent years, the data transfer rate has been improved, the cycle of the input data DI has been shortened, and therefore the window width Tw has tended to decrease. For example, the window width Tw is about 20 ns. In this way, as the window width becomes smaller, even a slight timing shift due to changes in the external environment (temperature, humidity), aging of components, etc., which have not been a problem in the past, causes a phase shift that cannot be ignored. It has become necessary to adjust automatically more frequently than before, that is, when the power is turned on, when maintenance is performed, or when there is an instruction from the central control unit (CPU). ing.

In such a case, automatic adjustment is necessary, but there is a problem that automatic adjustment cannot be performed by the above-described conventional measuring method.

The present invention does not require visual inspection with an expensive high-bandwidth measuring instrument, and automatically detects not only the deviation from the center phase of the window, but also the deviation from a predetermined optimum phase other than the center if necessary, and An object is to provide an automatic phase adjustment circuit that can be adjusted.

[Means for solving problems]

FIG. 1 is a diagram for explaining the principle of the present invention. In the drawing, the same components as those in FIG. 3 are indicated by the same symbols.

2 is a test data generator (hereinafter abbreviated as TDG),
As will be described later, the test data TD is generated by shifting the phase of at least one data (data pulse) with respect to a data string of a constant cycle having a predetermined cycle as a unit.
Reference numeral 3 denotes a phase shift detection unit (hereinafter abbreviated as PDC), which inputs the test data TD to the data discrimination circuit DDC1 and detects the phase shift by detecting the phase irregularity of the output data DO obtained as the discrimination result. Is. Reference numeral 4 denotes a phase adjustment unit (hereinafter abbreviated as AJC), which designates a delay time to a variable delay circuit, which will be described later, based on the result of phase shift detection by PDC3. 5 is a variable delay circuit that can specify the delay time (unlike in the case of FIG. 3, it is taken out from the data discrimination circuit, but since the essential action does not change, it is also abbreviated as DLY5 below). , For adjusting the relative phase of the input data DI and the window W in the data discriminating circuit DDC1. Reference numerals 6 and 7 are switching circuits (hereinafter abbreviated as SWI and SWO) for pulling the input and output lines of the data discrimination circuit DDC1 into the test data generation unit TDG2 and the phase shift detection unit PDC3 when phase adjustment is required. And the phase adjustment unit A
Controlled by JC4.

That is, according to the present invention, the switching circuits SWI6 and SWO7 and the test data generator TDG2 for generating a special test data string are used.
And a phase shift detection unit PDC3 that detects a phase shift by detecting the phase irregularity of the output data DO that is the discrimination data of the data discrimination circuit DDC1 based on this test data string,
Variable delay circuit DL that adjusts the phase shift of the DDC1 window
It is provided with Y5 and an adjusting unit AJC4 which gives a delay time instruction to DLY5 based on the phase shift detection result of PDC3.

[Action]

First, a method of detecting the deviation of the leading edge of the data pulse of the normal phase input data DI from the center of the window W, which is the basic principle of the present invention, will be described. Next, the normal phase input data DI will be described. Window W of the leading edge of the data pulse of
After explaining a method of detecting a deviation from a predetermined phase other than the center of, the automatic adjustment method of the window phase will be described.

(A) Detecting the deviation of the leading edge of the data pulse of the input data DI of the normal phase from the center of the window W In this case, conventionally, the test data string for measuring the phase deviation is The data train having a predetermined cycle is generated with the same fixed cycle as the window cycle Tw as a unit cycle (Tu). In the present invention, the phase of at least one data pulse of the test data series is shown in FIG. 1/2 of the window period Tw, like the data pulse in (b)
The test data DT that is shifted by exactly the same amount as is generated and output.

In FIG. 3B, when the leading edge of the data pulse of the input data DI of the normal phase is set to come to the center of the window W, and the data pulse of the input data DI Phase shift is 1 / of window period Tw
The case exactly equal to 2 has already been explained.

FIG. 4 shows the case where the leading edge of the data pulse of the input data DI having the normal phase is not set to come to the center of the window W. FIG. 7A shows the case where the window W is advanced, that is, Td is shorter and Tp is longer than in the normal case.
Is when the window W is delayed, that is, when Td is adjusted longer and Tp is adjusted shorter than in the normal case.
FIG. 3B shows the same as FIG. 3B for comparison with FIGS.

4 (a) and 4 (c), the window phases are deviated, so that the allowable range for the phase deviation of the data pulse of the input data DI is biased, and in FIG. 4 (a), As the output data DO, a data pulse with 0 attached to the data pulse of the phase advance and a data pulse attached with 1 to the data pulse of the delay phase are output. On the contrary, in the same figure (c), as the output data DO,
A data pulse with 2 is output for the data pulse of the phase advance, and a data pulse with 0 is output for the data pulse of the phase delay.

Therefore, a test data string (test pattern, hereinafter abbreviated as TDA) that includes a data pulse with a lead phase of (1/2) Tw in the normal phase data string and a (1/2) Tw ) Prepare a test data string (test pattern, hereinafter abbreviated as TDB) including a data pulse whose phase is only Tw,
Alternately output both lengths alternately to form one cycle, repeat this cycle and input the test data sequence TD that is continuously output to the data discrimination circuit DDC1 and pay attention to the output data DO number (corresponding window number) Then, when the phase of W is advanced, the DO numbers are all 0 in TDA and all the phases are normal, and in TDB it is 1 for the delayed data pulse, so that the phase delay is included. Become.

When the phase of W is normal (when the center of W coincides with the leading edge of the normal phase input data), looking at the number of DO, TDA shows 2 or 0 for the data pulse of the phase advance.
Is for 50% and includes phase lead, and in TDB, 0 or 1 is for 50% and includes phase delay for a delayed data pulse.

When the phase of W is delayed, the number of DO becomes 2 for the data pulse of the advanced phase in TDA to include the advance of the phase, and all the numbers become 0 in TDB and the phases are all normal.

Therefore, from the test data generator TDG2,
If the test data sequence TD in which TDA and TDB are alternated is input for a plurality of cycles and the phase shift detection unit PDC3 detects the phase irregularity of the output data DO, the phase shift of the window W from the normal phase can be detected. Yes, the phase can be adjusted by adjusting Td with DLY5.

(B) Detecting the deviation of the leading edge of the data pulse of the input data DI of the normal phase from the predetermined phase other than the center of the window W As described above, the PLL 8 generally follows the phase of the input data DI. Therefore, when the average period of the input data DI is different, the period (frequency) of the output clock CL also has the property of being synchronized with the average period (frequency) of the input data. Therefore, the DD9 that operates with the clock created by the PLL8 also operates synchronously, and the DDC1 also responds synchronously.

By combining this frequency synchronization property and the method (a), the phase shift can be detected in this case as described below.

In the case of (a), a test data string of a predetermined cycle is generated with the unit cycle Tu being the same fixed cycle as the window cycle Tw during operation, but in the case of (b), the unit cycle Tu As a result, the test data string TD is generated using a cycle different from the window cycle Tw during operation.

Even for the test data string of this different unit cycle, DD
Since C1 responds in synchronism, if the same operation as in (a) is performed, at the leading edge of the data pulse of the normal phase in the test data string of this unit cycle, the W It will be possible to detect if there is a center.

The adjustment is performed by adjusting Td by DLY5. If the adjusted delay time Td is kept as it is during operation, during operation, the phase deviated from the center of W becomes a normal phase. The leading edge of the data pulse of the input data DI comes.

Unit cycle Tu and window cycle to show the quantitative relationship
When the ratio of Tw is α and S is the deviation of the predetermined phase from the central phase of W, Tu = αTw (1) S = (1/2) (1-α) Tw (2). Numerical examples will be given below. When α = 0.7, S = + 0.15Tw, and when α = 1.3, S = −0.15Tw. + Indicates that the leading edge of the data pulse of the input data DI having the normal phase comes to the phase advanced from the center of W,
-Indicates the opposite.

Needless to say, the case of α = 1 is the case of (a), and S = 0.

(C) Automatic adjustment of window phase According to the method of (a) or (b), test data TD
Output data DO, which is the discrimination data obtained by inputting to DDC1
The direction of the phase shift can be detected by detecting the occurrence of the asymmetric phase of the test data TDA and TDB separately. The phase shift detection unit PDC3 is arranged to generate pulses when an irregular phase is detected, and the adjustment unit AJC4 decides to count these pulses respectively for a predetermined time period of a plurality of TD cycles, and for each predetermined time period elapsed. In addition, if the difference between these two count values is taken, the direction of the phase shift (also qualitatively the amount) can be known. Therefore, the delay time designation is selected and the variable delay circuit DL is selected.
Adjustment can be performed by specifying the delay time Td of Y5. Specifically, the switching circuits SWI6 and SWO7 are operated to input the test data TD to DDC1, the irregular phase of the discrimination data is detected, the delay time is selected and designated by the above method, and the confirmation is performed after the designation. Therefore, repeat the operation,
If the adjustment becomes excessive or deficient, the selection is specified again, and if the difference between the two count values is within a certain value, the adjustment is completed, the delay time specification in this case is held, and the switching circuit SWI6, S
Automatic adjustment is performed by switching WO7 to the operating state.

〔Example〕

(A) Description of the first embodiment of the present invention In the first embodiment, the relative phase is automatically adjusted so that the leading edge of the data pulse of the normal phase of the input data DI comes to the center phase of the window W. The case will be described. That is, in the above equations (1) and (2), α = 1, and thus Tu = Tw, S =
This is the case of 0. Therefore, the unit cycle of the test data string TD needs to be equal to the window cycle Tw during operation of the DDC1. In this example, it is assumed that the test data sequence TD outputs data pulses at a cycle three times as long as a unit (window) cycle.

In the following, the numerical examples of the present embodiment show the case where the standard window frequency (1 / Tw) at the time of operation of the DDC1 is 48 MHz and the above assumption is made.

FIG. 7 is a circuit configuration diagram of an embodiment of the present invention and shows a configuration of an automatic phase adjustment circuit. In the figure, those shown in FIG. 1 are indicated by the same symbols.

In the figure, the data discrimination circuit DDC1 is also drawn to show the connection relationship. Unlike the case of FIG. 1, the variable delay circuit DLY5 is shown as being incorporated in the data discriminating circuit DDC1.

In the test data generator TDG2 in the figure, 11 is an oscillator (hereinafter abbreviated as OS), which is composed of a crystal oscillator or the like and oscillates a reference clock BCL (for example, 9.6 MHz), and 12 is a phase comparator ( Hereinafter referred to as PHC), 13 is a voltage controlled oscillator (hereinafter referred to as VCO
, 14 is a frequency divider (hereinafter abbreviated as FDT, divided into 1/10 in this example), and 10 is a PLL circuit (hereinafter abbreviated as PLLT) including 12, 13 and 14 as main elements. That is, the test clock TCL (96 MHz, which is 10 times the TCB in this example) that is ½ of the unit period of the test data string is synchronously created.
17 is also a frequency divider (hereinafter abbreviated as FDA, in this example, the output of FDT14 is divided into 1/4096), and 18 is a control circuit (hereinafter CON
Is abbreviation), receives the output clock CCL of FDA17, and controls a counter to be described later in any of five-, six-, and seven-ary, and 15 is a counter (hereinafter abbreviated as CTR), and CON18 of The test clock TCL is counted according to the counter control signal of the quinary, hexadecimal, and hexadecimal to generate a test data string TD, and 16 is a driver (abbreviated as DR below) that shapes the output of CTR15 and DDC1 It is for sending to.

In the phase shift detection unit 3 in the figure, reference numeral 19 denotes an irregular phase detection circuit (hereinafter abbreviated as IRD), which is composed of a counter.
By monitoring the time interval of each data pulse in the output data DO (that is, the discrimination data string) output from the DDC1 by counting the test clock TCL, the abnormality of the time interval, that is, the phase irregularity was detected. When the detection signal pulse DS
, 21 and 21 are gates (hereinafter abbreviated as GA and GB), which selectively output the pulse signal DS output when the IRD 19 detects the phase irregularity of the discrimination data by the control of CON18.

In the phase adjustment unit 4 of the figure, 22 is a frequency divider (hereinafter abbreviated as FDC) that frequency-divides the output clock CCL of the FDA 17 and outputs the clock ACL, and 23 and 24 are GA20 and GB2, respectively.
A counter (hereinafter abbreviated as CTRA, CTRB) that counts for one cycle of the clock ACL in response to the output pulse DPA, DPB of 1.
5 is compared by taking the difference between the outputs of CTRA23 and CTRB24, and selects the delay time of the variable delay circuit DLY5 to specify the designated output DLS.
Is a comparison circuit (hereinafter abbreviated as COM) that creates a. 26 receives the adjustment instruction AJS from the outside of this circuit configuration, switches the switching circuits SWI6, SWO7 from the operating state and pulls in, and when the automatic adjustment is completed, returns the switching circuits SWI, SWO to the operating state and gives an external adjustment completion instruction. A switching control circuit that outputs AJE (hereinafter abbreviated as SC).

Next, the operation of the configuration of the embodiment shown in FIG. 7 will be described with reference to the waveform chart of the main part of FIG.

If the cycle of the clock TCL output from PLLT10 is T,
In order to shift the phase by 1/2 of the window (in this case, unit) cycle Tw, it is necessary that T = (1/2) Tw. According to the assumption of this example, the cycle of the data pulse of the test data string TD. Is 2 × 3 × T or 6T.

From the counter CTR15 that counts the test clock TCL,
A data pulse is output every 6T in hexadecimal, every 5T in quinary, and every 7T in hex. The control circuit CON18 divides the test clock TCL into 1/40960 by the frequency dividers FDT and FDA, that is, controls the count number of the CTR15 by the control clock CCL generated every 40960T.

CON18 normally directs CTR15 to hexadecimal, and when the control clock CCL arrives, the CTR15 ends the hexadecimal counting (that is, sees the rising edge of the test data pulse), and CT
Instruct the R15 to be in quinary and see the end of counting in CTR15 in quinary.
Instruct to advance, and after seeing the end of the 7-decimal count, return to the 6-indication. Therefore, the output test data sequence TD of the CTR17, which had a period of 6T, changes to 5T, 7T and returns to 6T (FIG. 5 (a)).
Generate a test pattern TDA as shown in. That is, the test pattern TDA includes approximately 6826 data pulses, and only one of the data pulses is a test pattern advanced in phase by T.

When the next control clock CCL arrives, CON18, which was instructing hexadecimal, turns 7 this time due to the completion of hexadecimal counting of CTR15.
When the CTR15 counts up to the 7th base, the next 5th base is commanded. When the 5th count finishes, the normal 6th base is restored.
Therefore, as the test data string TD of the CTR15, the test pattern TDB as shown in FIG. 5 (b), which changes from the period 6T to 7T and 5T and returns to 6T, is generated. That is, the test pattern TDB also includes approximately 6826 data pulses,
Only one of the data pulses becomes a test pattern whose phase is delayed by T. Therefore, the test pattern TDA and the test pattern TDB are alternately output from the CTR15,
The one pair forms one cycle of the test data sequence TD.

Test data TDA on DDC1 whose window phase is normal,
The case where the TDB is input is shown in FIGS. 5 (a) and 5 (b), respectively. In FIG. 5, CS is the counter C of the control circuit CON20.
A schematic representation of the counting instruction to TR, DS is a pulse output when the irregular phase detection circuit IRD19 detects the irregular phase of the output data DO discriminated by DDC1, and DPA and DPB are the gate GA20 respectively. , Shows the output of GB21.

The circled numbers in TDA and TDB indicate individual data pulses. The data pulses are out of phase by half the window period Tw, and the others are regular phases. In such a case, as described above, the data pulse is discriminated by an adjacent window with a probability of 1/2 as shown by a dotted line, and the data pulse of the corresponding output data DO is phase shifted as shown in the figure. Cause irregularities.

The irregular phase included in this output data DO is detected by the irregular phase detection circuit IRD19 by the above-mentioned method, and the pulse D
S is generated and DS is output to both gates GA20 and GB21.
On the other hand, from the control circuit CON18 to the gate GA20, GB21,
A signal is output depending on whether the test data TD currently being output is TDA or TDB.
Only S is selected to output the pulse DPA, and GB21 selects only DS in TDB and outputs the pulse DPB.

Figure 6 is drawn to show the passage of time in units of the TDA and TDB cycles, and the test data string TD is continuous.
This is the case when inputting to DDC1, and shows the generation status of DPA and DPB in gates GA20 and GB21. In the figure, TD is a test data string, and the periods of TDA and TDB are shown by abbreviated as A and B.

FIG. 5B shows the case where the window phase described in FIG. 5 is normal, and as an example, the discrimination of the phase displacement data pulse included in the test data sequence TD in the adjacent window is TD.
The figure shows the case where each cycle of A and TDB occurs alternately, that is, with a probability of 1/2.
A and DPB are generated at the same rate per unit time. Therefore, when the counters CTRA23 and CTRB24 count the result of counting one cycle of the output ACL of the frequency divider FDC22 (between a plurality of cycles of the test data TD) by the comparator COM25 and compare them, D is 0. Or, the phase becomes very small and there is no phase shift, indicating that the delay time of the variable delay circuit DLY5 is adjusted.

The figure (a) shows the case where the window phase lags behind the normal case. As described above, in TDA, the phase-advanced data pulse (of FIG. 5) is discriminated in the previous adjacent window 2. , The output data DO includes a data pulse whose phase has advanced, all of them are discriminated by the normal window 0 in TDB, and the output data DO does not have a phase disturbance. Therefore counter CT
1 of output ACL of frequency divider FDC22 by RA23 and CTRB24
Comparing the results of counting during the period by the comparator COM25 and comparing them with each other results in D> 0, which indicates that the window phase is delayed and it is necessary to reduce the delay time of the variable delay circuit DLY5.

FIG. 7C shows a case where the window phase is ahead of the normal case, and as described above, in TDB, the delayed data pulse (shown in FIG. 7) is delayed by the adjacent window 0
The output data DO includes a data pulse having a delayed phase, and the TDA distinguishes it in the normal window 0, so that the output data DO does not have a phase disturbance. Therefore the counter CTRA
When the result of counting the output ACL of the frequency divider FDC22 for one cycle by 23, CTRB24 is compared by the comparison circuit COM25 with the difference D, D <0, the phase of the window is advanced, and the variable delay circuit DLY5 Indicates that the delay time needs to be increased.

As described above, the delayed phase, the advanced phase, and the normal state of the window of the data discrimination circuit are represented by the signs D, +,-, and 0 (that is, D> 0, D <0, and D = 0). The COM25 can produce an output DLS for adjusting the delay time Td of DLY5.

The variable delay circuit DLY5 has various types such as one that is made variable by selecting the resistance value that constitutes the time constant of the mono-multivibrator, one that is made variable by selecting the tap of the delay line with taps, etc. However, as an example, a delay line with a tap is shown in FIG.

In FIG. 8, 27 and 28 are delay lines with taps (hereinafter D respectively).
LM and DLV), and 29 is a selection circuit (hereinafter abbreviated as SEL) that performs selective connection of taps according to an instruction DLS from COM25 and holds until the next DLS arrives, connected as shown in the figure. There is. In the adjustment with the tapped delay line DLM27, as shown in the figure, the selection circuit SEL29 selectively connects the central tap (3 in the example in the figure) of the plurality of taps of the tapped delay line DLV28. It shall be adjusted and connected (indicated by the dotted line) in the above condition.

Although the DLV 28 has 5 taps in this example, it is shown that the width of the automatic adjustment of the delay time Td by the DLS is +, -2 steps by the adjustment of the DLM 27 at the time of manufacturing.
Therefore, in this example, the COM 25 may be, as the DLS, an instruction to move the tap selectively connected by the SEL 29 by + or -1 step.

Although the operation of each unit has been described above, the procedure for performing the automatic phase adjustment is summarized assuming that the automatic phase adjustment circuit of the present invention is incorporated in the magnetic disk device together with the data discrimination circuit DDC1. And as shown in the flowchart of FIG.

The power-on instruction, inspection instruction, or instruction from the main control unit (CPU) is sent to the AJS switching control circuit SC26.
, The automatic adjustment operation is started when AJS is received, SWI6 and SWO7 are operated, and the input and output of DDC1 are pulled into the automatic adjustment circuit. After that, as shown in the flowchart of FIG. 9, after one cycle of ACL, if D is 0, S
The automatic adjustment operation is completed by restoring WI6 and SWO7 and transmitting AJE, which means the completion of adjustment. D is not 0, but +,-
In case of any number of
The d is adjusted by one step, and the same operation is repeated in the next cycle of the ACL, and when D becomes 0, the above-mentioned end operation is performed.

As for the division ratio of the frequency divider FDC that determines the period of the ACL, as can be seen from the above description, the irregular phase detection pulse DPA,
It suffices that the comparison of the count values by the CTRA and CTRB of DPB be sufficiently accurate. Considering the count values as about 2 decimal digits, 1/16
Therefore, both count values for one cycle of ACL are about 73 at maximum.

(B) Description of the Second Embodiment of the Present Invention In the second embodiment, the leading edge of the data pulse of the input data DI having the normal phase is located at a predetermined phase other than the center of the window W. This is a case where it is detected whether or not the phases are aligned.

Such window phase setting actually occurs, for example, when reading data from a magnetic disk due to delay time distortion or the like caused by the relationship between frequency characteristics of the disk as a storage medium and the head and other phases. This is necessary when there is a bias in the advance or delay of the jitter.

In this example, the case where S = + 0.15Tw when α = 0.7 and S = −0.15Tw when α = 1.3 shown in the description of the above equations (1) and (2) will be described as an example. That is, there are cases where the leading edge of the data pulse of the input data DI of the normal phase is advanced from the center of the window during operation by 15% of the window cycle Tw during operation and is behind, and this setting is normal. That is the case.

The leading edge of the data pulse of the normal phase input data DI is 15% of the window period Tw from the center of the window during operation.
Explain the case where it is normal to just proceed. Also in this case, the circuit configuration of the automatic phase adjustment circuit shown in FIG. 7 is the same, and the division ratio of each frequency divider is also the same.

However, since the unit period Tu of the test data sequence TD is 0.7 = Tw in case of α = 0.7, the oscillation frequency of the oscillator OS11 needs to be set to 1 / 0.7 accordingly. , TCL, CCL, ACL each cycle is 0.7 times. In practice, changing the oscillation frequency of the oscillator OS11 is often possible only by replacing the crystal oscillator.

With the test data sequence TD generated in this way,
Since the adjusted Td is returned to the operating state as described above, the detection and adjustment of the phase shift of the window can be performed by performing the same operation as in the first embodiment of (a). It can be done automatically.

The leading edge of the data pulse of the normal phase input data DI is 15% of the window period Tw from the center of the window during operation.
A case will be described where it is assumed that the delay is normal. Also in this case, the circuit configuration of the phase shift detection circuit shown in FIG. 7 is the same, and the division ratio of each frequency divider is also the same. However, the unit period Tu of the test data string TD must be 1.3Tw because α = 1.3, so that the oscillation frequency of the oscillator OS11 needs to be 1 / 1.3, and therefore BCL , TCL, CCL, ACL cycle is 1.3 times each.

With the test data sequence TD generated in this way,
As described above, since the adjusted Td is returned to the operating state while being held, the window phase shift can be detected and adjusted also in this case by performing the same operation as in the embodiment (a). .

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention, and these modifications are not excluded from the present invention.

〔The invention's effect〕

As described above, according to the present invention, the deviation of the phase of the window of the data discrimination circuit from the optimum phase is determined not only when the optimum phase is at the center of the window but also when it is at an arbitrary phase within the window. Also, by incorporating a simple circuit into the device without using a measuring instrument such as a synchroscope, it is possible to perform automatic adjustment not only at power-on and maintenance / inspection, but also at every instruction from the central control unit. There is an effect to say.

Therefore, there is an effect that the reading and transferring of data becomes faster, the window width becomes narrower, and the phase shift due to environmental changes and aging that cannot be ignored can be automatically and rapidly adjusted.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of a data discrimination circuit, FIGS. 3 and 4 are explanatory diagrams of the operation of the data discrimination circuit, and FIG. FIG. 6 is an explanatory diagram of a phase shift detection operation, FIG. 7 is a circuit configuration diagram of an embodiment of the present invention, FIG. 8 is an explanatory diagram of a variable delay circuit, and FIG. 9 is a flowchart of an automatic adjustment operation, 1, 2, 7, In FIG. 8, 1 is a data discrimination circuit DDC, 2 is a test data generator TDG,
3 is a phase shift detection unit PDC, 4 is a phase adjustment unit AJC, 5 is a variable delay circuit DLY, 6 is a switching circuit SWI, and 7 is a switching circuit.
SWO, 8 is a PLL circuit PLL, 9 is a data discriminator DD, 10 is a PLL circuit PLLT, 11 is an oscillator OS, 12 is a phase comparator PHC, 13 is a voltage controlled oscillator VCO, 14 is a frequency divider FDT, and 15 is a counter. CT
R, 16 are drivers DR, 17 is a frequency divider FDA, 18 is a control circuit CON, 19 is an irregular phase detection circuit IRD, and 20 and 21 are gates G, respectively.
A, GB, 22 are frequency dividers FDC, 23, 24 are counters CTRA,
CTRB, 25 is a comparison circuit COM, 26 is a switching control circuit SC, 27
Is a delay line DLM with taps, 28 is a delay line DLV with taps, and 29 is a selection circuit SEL.

Claims (3)

(57) [Claims] 1. A clock is created by a phase synchronization circuit that follows and synchronizes with the phase of input data, the input data is discriminated using the clock as a window, and output as output data.
A test data generation unit that is added to a data discrimination circuit having a variable delay circuit and generates test data, a first switching circuit that switches between input data and test data and inputs the data to the data discrimination circuit, and output of the data discrimination circuit A second switching circuit that switches the data output destination between input data input and test data input, a phase shift detection unit that detects the phase difference between the output data and the test data, and a phase difference adjustment instruction, The first switching circuit is switched so that the test data is input to the data discriminating circuit, and the second switching circuit is switched so that the output data is output to the phase shift detection circuit. Change the setting value of the variable delay circuit according to the phase difference, and after that,
An automatic phase adjustment circuit, comprising: a phase adjustment unit that switches the first switching circuit to input data and switches the second switching circuit to an output destination when input data is input. 2. A counting circuit which counts in a half cycle of a unit cycle and generates data when counting a designated number of times, and a number of times corresponding to a cycle in which input data is input to the counting circuit, And a control circuit that sequentially sets the number of times and the number of times that the difference is 1, and a test data generating unit that generates a test data string including data whose phase is shifted by a period corresponding to half of the unit period. The automatic phase adjustment circuit according to claim (1). 3. The number of times +1 is added to the number of times corresponding to the cycle of input data to the counting circuit, and -1 is added to the number of times.
Is set by the control circuit, and the phase of at least one data is advanced by at least 1
The automatic phase adjustment circuit according to claim (2), further comprising a test data generation unit that outputs a test data sequence in which the phase of one data is delayed.