JP2537799Y2 - Frequency discriminator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an improvement of a frequency discriminator using a phase locked loop circuit realized by digital signal processing using a digital signal processor.

[Outline of the invention]

In the frequency discriminator using the phase locked loop circuit, the head of the input single tone signal is disturbed by noise and the like, and locked to a frequency different from the normal frequency that the phase locked loop circuit tries to detect. As a result, the frequency discrimination could not be performed as expected. The present invention provides a solution to the above problem.
After the power of the input single tone signal is detected, the frequency tracking operation of the phase locked loop circuit is initialized at regular intervals.

According to the present invention, by repeating the frequency tracking operation of the phase locked loop circuit from the initial state at regular intervals, it becomes possible to lock the phase locked loop circuit once locked to another frequency to the normal frequency again. . This enables correct frequency discrimination without being affected by the disturbance of the input single tone signal.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional technology of a frequency discriminator using a digital signal processor.

A single tone signal to be discriminated is input from an input signal terminal 1 to a phase locked loop circuit 3, and the phase of the input single tone signal from the phase locked loop circuit 3 and free-running oscillation in the phase locked loop circuit 3 The phase error value signal 5 with the frequency phase is extracted. This phase error value signal 5 is input to the phase error value discriminating circuit 4, and the frequency of the input single tone signal is discriminated by the phase error value to obtain frequency discrimination outputs 2, 2 ', 2 ".

[Problems to be solved by the invention]

In the prior art, since the frequency discrimination is performed by the phase error signal component 5 of the phase locked loop circuit 3, the head of the input single tone signal is disturbed by noise or the like, and the phase locked loop circuit 3 tries to detect. It locks to the normal frequency f at n · f (n: an even natural number) and outputs an erroneous phase error signal.

As described above, the phase locked loop circuit 3, which has once locked to the wrong frequency, cannot lock to the normal frequency even after the disturbance of the input signal has disappeared. As a result, the expected frequency discrimination is performed. Had the drawback that it was not possible.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to enable correct frequency discrimination without being affected by disturbance of an input single tone signal.

[Means for solving the problem]

FIG. 1 is a block diagram showing the overall configuration of the present invention. In the figure, a single tone signal to be discriminated is input from an input signal terminal 1 to a phase locked loop circuit 3, and the input single tone signal phase and the phase locked loop circuit 3 are output from the phase locked loop circuit 3.
The phase error value signal 5 with respect to the free-running oscillation frequency phase is taken out. The phase error value signal 5 is input to the phase error value identification circuit 4 to discriminate the frequency of the input signal based on the phase error. At the same time, after detecting the signal power of the input single tone signal by the power detection circuit 6, the timer circuit 7 is started, and the timer circuit 7 sends the phase locked loop signal to the phase locked loop circuit 3 at regular intervals. This is to initialize the frequency tracking operation of the circuit 3.

[Action]

As a result, the head of the input single tone signal is disturbed for some reason, and the phase locked loop circuit 3 is once locked to a frequency different from the frequency to be detected, and is incorrectly discriminated by the phase error value identification circuit 4. Even if you do
After the phase locked loop circuit 3 is initialized at regular intervals by the timer circuit 7 and the disturbance of the input single tone signal is reduced, the phase locked loop circuit 3 is reset from the initial state while a single tone signal without disturbance is being input. Since the frequency tracking operation of the locked loop circuit can be performed, the phase locked loop circuit can be locked at the normal frequency.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

This embodiment uses a digital signal processing technique, and is largely composed of an A / D converter 21, a digital signal processing processor 26, and a microprocessor 27.

An input signal applied to the signal input terminal 1, that is, a single tone signal to be discriminated is converted from an analog signal into a quantized signal by an A / D converter 21 and then input to a digital signal processor 26. The phase error value signal 5 is input as an output of the digital signal processor 26 to a phase error discriminating circuit composed of a microprocessor 27 to obtain frequency discrimination outputs 2, 2 ', 2 ". A phase locked loop circuit, a power detection circuit 6 and a timer circuit 7 are formed.

The phase-locked loop circuit compares the output of the A / D converter 21 with the output of the voltage-controlled oscillator 24, which will be described later, and removes harmonic components and noise from the output signal of the phase comparator 22. And a voltage controlled oscillator 24 whose oscillation frequency is controlled by the phase error signal voltage output from the loop filter 23.

In this embodiment, the voltage-controlled oscillator 24 is composed of two adders, a delay element 28, and a computing unit 25 which outputs a cosine value with an input as an argument, and a coefficient a indicates the free-running oscillation frequency of the voltage-controlled oscillator. It is a value to be determined.

On the other hand, the signal applied to the signal input terminal 1 and quantized by the A / D converter 21 is input to the power detection circuit 6 and a power detection result 29 is obtained. The power detection result 29 is connected to the timer circuit 7, and the voltage controlled oscillator initialization signal 30 output from the timer circuit 7 is connected to the delay element 28 of the voltage controlled oscillator 24.

The operation of the present invention with the above configuration will be described below with reference to the time chart of FIG. The appearance of power in the input signal 31 turns on the power detection result 29. The operation of the timer circuit 7 is started by triggering the power detection result 29 from OFF to ON, and at the same time, the frequency tracking operation of the phase locked loop circuit 3 is performed. Start. The timer circuit 7
As shown in the timer circuit operation 33, the time-up is repeated at regular time intervals, and the voltage-controlled oscillator initialization signal 30 is generated at each time-up.

As described above, the voltage-controlled oscillator initialization signal 30 is connected to the delay element 28 in the voltage-controlled oscillator 24,
Is initialized to zero, thereby initializing the voltage-controlled oscillator 24. That is, as for the operation of the voltage controlled oscillator 24, as shown in FIG. 2, its oscillation output frequency is set by an argument given to a computing unit 25 which outputs a cosine value. The delay element 28 holds the argument given to the arithmetic unit 25 and feeds back the held value to the first-stage adder in the voltage-controlled oscillator 24. Here, the voltage controlled oscillator initialization signal 30 from the timer circuit 7 is applied to the delay element 28, and the held value is set to zero, so that the value fed back to the first-stage adder becomes zero. Initialization in the control oscillator 24 is performed. While the power of the input signal 31 is present, the power detection result 29 is ON, during which the timer circuit 7
Repeats the above operation. When the power of the input signal 31 is extinguished, the power detection result 29 is turned off, and this is used as a trigger to stop the timer circuit operation 33 and the voltage controlled oscillator initialization signal 30. By receiving the phase error value signal 5 output from the phase locked loop circuit 3 by the above operation,
When the phase error discriminating circuit constituted by the microprocessor 27 is turned on after the lapse of the tracking time t by the first frequency tracking operation of the phase locked loop circuit as shown in the frequency discrimination output A35, the frequency discrimination output B36
As shown in the figure, it is not possible to discriminate the first time in the phase-locked loop circuit, and after the voltage-controlled oscillator is initialized,
As shown in the frequency discrimination output C37 when it is turned on after the tracking time t and the first tracking operation of the phase locked loop circuit was turned on for erroneous discrimination, but erroneous discrimination was recognized by initializing the voltage-controlled oscillator. Then, control is performed to turn off the frequency discrimination output at the next initialization of the voltage controlled oscillator.

[Effect of the invention]

According to the present invention, even if the phase locked loop circuit that generates the phase error value signal necessary for frequency discrimination locks once to a frequency different from the frequency to be detected due to disturbance of the input signal, etc. The frequency can be locked to the correct frequency after the disturbance of the signal has subsided, and regular frequency discrimination can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention, FIG. 2 is a diagram showing one embodiment of the present invention, FIG. 3 is a time chart showing the operation of one embodiment of the present invention, and FIG. FIG. 2 is a block diagram illustrating a configuration of a technology. 1: Input signal terminal, 2, 2 ', 2 ": Frequency discrimination output, 3: Phase locked loop circuit, 4: Phase error value discrimination circuit, 6: Power detection circuit, 7: Timer circuit, 21: A / D A converter, 22: a phase comparator, 23: a loop filter, 24: a voltage controlled oscillator, 25: a cosine value calculator, 26: a digital signal processor, 27: a microprocessor.

Claims (1)

(57) [Scope of request for utility model registration] An oscillator for generating an internal oscillation signal; and a phase comparator for comparing a phase of an input signal with a phase of the internal oscillation signal to generate a phase error value signal. A phase-locked loop circuit for applying a frequency following operation to the input signal, and discriminating a frequency of the input signal based on the phase error value output from the phase-locked loop circuit. A frequency discriminator comprising a phase error value discriminating circuit for outputting a frequency discriminating signal, comprising: a detecting circuit for detecting the input signal and outputting a detection signal; During the period, an initialization signal is given to the oscillating means in the phase locked loop circuit at regular intervals, and
A frequency discriminator comprising: a timer circuit that controls the frequency follow-up operation for an input signal of the locked loop circuit to be repeated from an initial state.