JP2536572B2 - Sort processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sorting apparatus, and in particular, in a stepwise merging process, there is no error in the sorting order of records output as sorted record strings, The present invention relates to a sort processing device equipped with sort check means for checking in synchronization with record output from a sort circuit.

[Conventional technology]

Generally, data handled in database processing is called a record. However, when the number of records is extremely large, or when a plurality of databases are to be processed, processing with a general-purpose electronic computer requires a huge amount of time. Therefore, a sort processing device for directly executing a part or the whole of database processing by hardware to speed it up is disclosed, for example, in Japanese Patent Laid-Open No. 61-42031.

FIG. 3 shows the configuration of the sort processing device disclosed in the above-mentioned Japanese Patent Laid-Open No. 61-42031. In the figure, 11 is a sort circuit, 12 is a buffer memory, 50 is a control circuit, 51 is an input register, 52 is an output register, 53 is a bank address generation circuit, 54 is a source input / output switching circuit, and 55 is a read circuit. Address generating circuit, 56 write address generating circuit, 57 address switching circuit, 58 data switching circuit, 59 switching control line (ST), 60 bank address line (BA), 61 I phase signal line (I), 62 is a II phase signal line (II), 63 is a state control line (INT), 64 is a sort input / output switching signal line (PUP), 65 is an input control line (PUSH), 66 is an output control line (POP), and 67 is Shows the data input / output line (DIO).

The sorting circuit 11 stores k records, compares the stored records with each other, and outputs the maximum or minimum record among the k stored records. The buffer memory 12 is a storage circuit for storing the sorted record string sorted by the sorting circuit 11.

The sorting process consists of an initial sorting stage and a merging stage, and is designated by a switching control line (ST) 59. In the initial sorting stage, a large number of sorting target records are sorted by the sorting circuit 11 with the number of records corresponding to the capacity of the sorting circuit 11 as a unit, and the result is stored in the buffer memory 12 as a sorted record string.

In the merging step, a plurality of record strings stored in the buffer memory 12 in the initial sorting step are merged using a sorting circuit. The number of record rows that can be merged at one time is defined by the capacity of the sort circuit 11, and if the sort circuit 11 can store k records, k records can be merged at one time.

Since the record string stored in the buffer memory 12 in the initial sort stage is equal to the number k of records that can be sorted at one time by the sort circuit 11, a maximum of k ² records are sorted at once by the initial sort stage and the merge stage. be able to. If you want to sort more than k ² records,
The output record string obtained by the processing in the above-described merge step is stored again in the buffer memory 12, and the record string consisting of a maximum of k ² records is merged again using the sort circuit 11.

In this way, by performing the merging process of merging k record strings at a time for i stages including the initial sorting stage, a maximum of k ⁱ records are merged until the buffer memory 12 is full. be able to.

FIG. 4 uses the sort processing device shown in FIG.
It shows the flow of processing when sorting a large number of records. As shown in the figure, this is an example in which processing of three stages including an initial sort stage, a first merge stage, and a second merge stage is performed. The display in the figure shows the sort circuit 11 and the buffer memory 12 that are repeatedly used.

The sorted record string stored in the buffer memory 12 is represented by a triangle whose height is the size of the record for determining the size relation of the records. A maximum of k ³ records can be sorted by a three-step merge process using a sort circuit capable of sorting k records.

In the above description, the method of repeating the stepwise merge processing by using one buffer memory and one sort circuit has been described. However, a plurality of merge processing circuits as shown in FIG. There is also a known method for performing high-speed sorting by operating the. In this method, k = 2 is set in order to reduce the hardware amount of the merge processing circuit per stage.
Way merge is common.

By the way, the records to be processed by the sort processing device are often required to have extremely high reliability with respect to the sorting result, such as an individual name and a deposit balance. As a method of guaranteeing the reliability of the content of a record, a technique such as parity check, which is widely used in general-purpose computers, is known.

On the other hand, as a problem peculiar to the sort processing device, there is a problem that it is necessary to guarantee that there is no error in the output order of the finally output records. For this purpose, it is necessary to inspect the output order of the records output from the sort processing device, and the method is, for example, “Design and Implementation” by K. Iwata et al.
of a Two−Way Merge− Sorter and its Application
to Relational Database Processing "(ICOT Technical
The method disclosed in Report TR-066, 1984) can be mentioned.

This method uses a device as shown in FIG. 5, and arranges a sorting checker for checking the sorting result after the 12 sorting cells. The output of the sorting checker is connected to the merger.

That is, this method (apparatus) is configured to check whether there is an error in the final output stage of the sort processing apparatus.

[Problems to be Solved by the Invention]

In the above-mentioned conventional technique, since it is checked that there is no error in the sort order of the records when the sort process is completed, there is a problem that a time delay occurs after the sort error occurs until the error is detected. It was In particular, when the number of records to be sorted is large, there is a problem that the time until the detection of sort error becomes too long to ignore.

Further, in the conventional sort processing device that performs repeated merge processing, the record string output by the merge processing of the previous stage is used as the input of the merge processing of the next stage, so a sort error is discovered after proceeding to the last merge processing. It becomes difficult to find out at what stage the error occurred,
There was also a problem that it was difficult to analyze the cause.

For example, in the example of the sorting process shown in FIG. 4, in the output record string of the first merging stage, the record strings that should be arranged in the order of j, i, k ... j, k ...
They are in the wrong order. When all the records are sorted by performing the second-stage merging process including this record string, the records input from other input record strings are inserted between the records i, j, and k.

Therefore, when the output order of the final output record string is checked, it is possible to detect that there is an error in the magnitude relationship before and after the record j, but it is not possible to determine at what stage the error occurred, so an error occurs. There is a problem that it is difficult to elucidate the cause of the occurrence.

Even when a pipeline operation is performed using a plurality of merge processing circuits, there is a problem that a similar time delay occurs, and it is difficult to determine at what stage of the merge processing circuit an error has occurred. There was also a problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-described problems in a conventional sort processing device and to prevent a sort error from occurring in a process of a merge operation that is repeatedly executed. An object of the present invention is to provide a sort processing device having a mechanism capable of detecting the error without a time delay.

[Means for solving the problem]

The above object of the present invention is to provide a sorting means capable of storing a maximum of k input records when k is an integer greater than 1, and extracting a minimum or maximum record from the input records. A record storage unit for storing a record string, and an input operation for reading up to k top records of each sorted record string and inputting them to the sort unit, and an output operation for outputting a record from the sort unit. In a sort processing device for merging a plurality of record strings stored in the record storage means by repeating a merge operation that alternately executes and, it is confirmed that there is no error in the sorting order of the records output from the sort means. And a sort processing device provided with sort check means for checking in synchronization with the output of the record. Thus it is achieved.

[Action]

In the sort processing apparatus of the present invention, by providing a means for checking that the records output from the sorting means are sorted in a specified order in synchronization with the record output, a sort error is immediately generated in the process of the merge processing. Can be detected. As a result, it is possible to prevent the erroneously sorted record string from being sent to the next stage, and to easily find the cause of the error. Further, it is possible to interrupt the merge process in which a record string that has been erroneously sorted is input to suppress the meaningless continuation of the sort process.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a sort processing apparatus showing an embodiment of the present invention. In the figure, 21 is a comparison transfer unit (hereinafter also simply referred to as “unit”), 22 is a memory, 23 is a data transfer path, 24 is a comparator, 25 is a comparison result holding flag, 26
Is a data transfer path switching signal, 27 is a left data transfer line, 28 is a right data transfer line, 29 is a memory data line, 30 is a comparison result output line, 31 is an OR gate, and 32 is a sort error detection signal.

The sorting circuit 11 has a memory 22 for storing two records.
Is composed of a one-dimensional array of the comparison transfer unit 21 including a comparator 24 and the like for comparing between records, and k records are stored in the entire sorting circuit to perform comparison / transfer processing.
It realizes the function of outputting the maximum or minimum record among the stored records.

The memory 22 is divided into MA and MB into two for storing two records per unit, and each is connected to the data transfer path 23 by a memory data line 29. The data transfer path 23 realizes bidirectional transfer of records between the memory data line 29, the left and right adjacent data transfer lines 27 and the right data transfer line 28 which perform data transfer with the comparison transfer units adjacent in the left and right directions. It is a switching circuit for.

The comparator 24 inputs two records and determines three magnitude comparison circuits (A, B,
C). Of these, the output of the comparison circuit C is set in the comparison result holding flag 25, and controls the switching of the data transfer path 23 as the data transfer switching signal 26. Comparison circuit A,
The output of B is the sort error detection signal 3 via the OR gate 31.
2 is generated and output to the outside of the sort circuit 11.

A sort processing circuit (not shown) detects that an error has occurred in the output order of the records from the sort circuit 11 by the sort error detection signal 32 output from the sort circuit 11, and records in the wrong order. If is output, fault processing such as immediately stopping the merge operation is performed.

The storage (input) of records in the sorting circuit 11 is
Records are input from the outside of the sort circuit to the comparison transfer unit at the left end, and records are transferred to the right between the comparison transfer units connected in a one-dimensional array. When sorting in ascending order, 2 stored in each comparison transfer unit
Of the records, the larger one is transferred to the right, and when sorting in descending order, the smaller one is transferred to the right.

In each comparison transfer unit, the record transferred from the left side is stored in the memory emptied by the transfer to the right side. At that time, the record that stays in the unit without being involved in the transfer is compared with the record input by the transfer,
The record to be transferred next is determined based on the size relationship.

Regarding the output of the record, the transfer direction is reversed from that at the time of storage, the record is input from the adjacent comparison transfer unit on the right, and the record is output to the adjacent comparison transfer unit on the left. The leftmost unit outputs the maximum or minimum record of all the records stored in the sort circuit. Regarding the record to be transferred to the left, the smaller one of the two records stored in each unit is transferred at the time of ascending sort, and the larger one is transferred at the descending sort.

The sort check, which is a feature of the sort processing apparatus of the present invention, is performed at least at the leftmost comparison transfer unit 21 in synchronization with the output of the record when the record is output. The contents of the check are the records output from the unit (hereinafter,
The “output record” is a record that remains in the own unit (hereinafter, “residual record”) and a record that is input to the own unit from the left adjacent unit (hereinafter, “record”).
Check that it is smaller (during ascending sort) or larger (descent descending sort) than "input record".

FIG. 2 is a diagram for explaining the sort check operation performed during the output operation. At the time of output operation, the data transfer path in the comparison transfer unit 21 forms a data transfer path so that a record is input from the right adjacent unit and output to the left. Reference numeral 33 in FIG. 2 is a switching circuit for selectively outputting a record stored in either one of the memories divided into two according to the data transfer path switching signal obtained from the comparison result.

The comparison circuit A compares the output record with the residual record, the comparison circuit B compares the output record with the input record, and the comparison circuit C compares the residual record with the input record.

At least, the result of the comparison circuit A and the comparison circuit B in the comparison transfer unit at the left end can check whether or not the order of the records output from the sort circuit 11 is properly aligned in a desired order. The result of the comparison circuit C is stored in the comparison result holding flag, and the data transfer path is controlled so that the sorting process is performed normally.

When the sort check is performed by the leftmost unit of the sort circuit including the one-dimensional array of the comparison transfer unit shown in the above embodiment, it is possible to detect that an error has occurred in the order of the records output from the sort circuit. It does not continue the subsequent merging process with the record string erroneously merged as an input. Furthermore, by performing a sort check on multiple units that make up the sort circuit,
It is possible to shorten the time from the occurrence of sort error to the detection of error. As a result, it is easy to deal with the occurrence of a failure, and it is effective in improving the reliability of the sort processing device.

In the above description of the embodiment, the case where the one-dimensional array of the comparison transfer unit is used for the sorting circuit is shown.
A circuit that stores k records and outputs the maximum or minimum record according to the size relation of the stored records, for example, a sort circuit is configured using an associative memory or the like, and merge processing is performed as shown in the conventional method. Even with the configuration, the features of the sorting apparatus of the present invention can be realized by inspecting the order of records output from the sorting circuit.

〔The invention's effect〕

As described above, according to the present invention, when k is an integer greater than 1, a maximum of k input records can be stored, and a minimum or maximum record can be extracted from the sorting means, A record storage unit for storing a presorted record sequence, and an input operation of reading up to k top records of each sorted record sequence and inputting to the sort unit, and a record from the sort unit. In a sort processing device for merging a plurality of record strings stored in the record storage means by repeating a merge operation that alternately executes an output operation to output, the sorting order of the records output from the sort means is incorrect. Since there is a sort check unit that checks that there is no record in synchronization with the output of the record, it is repeated In process of that merge operation, with no time delay from the occurrence of the sort error, in which a marked effect of realizing a sort processing apparatus having a mechanism capable of detecting the error.

[Brief description of drawings]

FIG. 1 is a block diagram of a sort processing apparatus showing an embodiment of the present invention, FIG. 2 is a view for explaining a sort check operation performed at the time of an output operation in the sort processing apparatus, and FIG. 3 is a conventional sort processing apparatus. FIG. 4 is a configuration diagram showing an example, FIG. 4 is a diagram showing a processing flow of the conventional sort processing apparatus shown in FIG.
FIG. 5 is a block diagram showing an example of a conventional sort processing device in which a sorting checker is arranged at the subsequent stage of the sorting cell. 11: Sort circuit, 12: Buffer memory, 21: Comparison transfer unit, 22: Memory, 23: Data transfer path, 24: Comparator, 25: Comparison result holding flag, 26: Data transfer path switching signal, 27:
Left data transfer line, 28: right data transfer line, 29: memory data line, 30: comparison result output line, 31: OR gate, 32: sort error detection signal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kiyoshi Yata 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa factory (72) Inventor Naohiko Shimizu 1 Horiyamashita, Hadano, Kanagawa Hitachi, Ltd. Kanagawa factory (72) Inventor Hideaki Takeda 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Haruo Hayami 1-1-6 Uchiyuki-cho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (1)

(57) [Claims] 1. A sort means capable of storing a maximum of k input records (an integer greater than k: 1), and a minimum or maximum record of the input records, and a presorted record string. And a record storing means for reading the first record of each sorted record string up to k in number and inputting to the sorting means, and an output operation for outputting records from the sorting means alternately. In a sort processing device for merging a plurality of record strings stored in the record storing means by repeating the merge operation to be executed, it is confirmed that there is no error in the sorting order of the records output from the sorting means. A sort processing device comprising a sort check means for checking in synchronization with an output.