JP2534722B2 - External synchronization method - Google Patents

Description

The present invention relates to an external synchronization means for a local area network having a duplicated loop (hereinafter referred to as a duplicated loop run).

〔Overview〕

The present invention, in an external clock synchronization system of a local area network having a duplicated loop system, is provided with an external synchronization circuit for each loop system, and each output is given to an external synchronization circuit of another loop system for external synchronization. The two loop systems can be operated independently.

[Prior Art] Conventionally, as shown in FIG. 2, the external synchronizing means of the duplex loop run is configured from an external synchronizing clock source 1 to an external synchronizing circuit 4.
The two clocks a and b are input to the input circuit, the selection circuit 41 of the external synchronizing circuit 4 selects one of the input clocks a and b, and this is branched into two systems to provide the outputs j and k. The clocks j and k output from the selection circuit 41 are input to the PLO circuits 42 and 43 of the two systems,
Externally synchronized two-system loop run driving clocks m and n are output to the outputs of 42 and 43. The clocks m and n for driving the two loop runs are further selected by the selection circuit 44.
To the output circuit p and s, the output clock p is used as the clock of the 0-system loop 5, and the output clock s is set to 1 The clock of the system loop 6 is used.

[Problems to be solved by the invention]

In such a conventional external synchronizing means, in the case of a system in which the 0-system and the 1-system are completely independent, the 0-system and the 1-system have a common part, which is disadvantageous.

The present invention eliminates such drawbacks, and an object of the present invention is to provide an external synchronization system in which the 0 system and the 1 system can be separated and operated independently.

[Means for solving problems]

The present invention relates to an external synchronization circuit provided corresponding to each of duplicated loop-shaped paths of a local area network, and one of the external synchronization circuits is an external synchronization circuit instead of a phase comparison clock signal from a clock source. It is characterized in that it is provided with a selection means capable of giving a clock signal related to the driving clock signal from the other side of the circuit to the oscillator of its own circuit.

[Action]

One of the external synchronizing circuits supplies a driving clock signal having a predetermined phase relationship with this clock signal to a loop-shaped path corresponding to the one external synchronizing circuit based on the phase comparison clock signal from the clock source. However, instead of the phase comparison clock signal from this clock source, the drive clock signal can be generated based on a signal obtained by dividing the drive clock signal output from the other external synchronization circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment.

As shown in FIG. 1, this embodiment is provided corresponding to each of an external synchronous clock source 1 which is a clock source for generating a phase comparison clock signal and a duplicated loop-shaped path. PLO circuits 22 and 32 which are oscillators for oscillating the driving clock signals supplied to each of the duplicated loop-shaped paths while maintaining a predetermined phase relationship with the clock clock signal and the phase comparison clock signal from the clock source. In place of the above, the selection circuits 21 and 31 which are selection means capable of giving a clock signal related to the driving clock signal from the other external synchronization circuit to the oscillator of the own circuit.
And external synchronization circuits 2 and 3 having The two clocks a and b from the external synchronous clock source 1 are input to the 0-system external synchronous circuit 2 and the 1-system external synchronous circuit 3, respectively. In the 0-system external synchronizing circuit 2, the 0-system selecting circuit 21 selects the clock a and the clock h and outputs the clock c. Normally, the clock a is selected and the clock h is selected when the clock a is disconnected. select. Here, the clock h is obtained by dividing the clock f externally synchronized by the 1-system external synchronizing circuit 3 by the 1-system dividing circuit 33. The output clock c of the 0-system selection circuit 21 is input to the 0-system PLO circuit 22 and outputs the externally synchronized 0-system driving clock e. The clock e is also input to the 0-system frequency dividing circuit 23, is output as a phase comparison clock g, and is input to the 1-system external synchronizing circuit 31. Further, when the clock a is cut off, the output clock g of the 0-system frequency divider 23 is inhibited. The 1-system external synchronization circuit 3 also operates similarly to the 0-system external synchronization circuit 2.

Therefore, even if the clock a input to the 0-system external synchronization circuit 2 is disconnected, the clock is synchronized with the clock h, and when the clock b input to the 1-system external synchronization circuit 3 is disconnected, it is synchronized with the clock g. However, the clock of the external synchronization clock source 1 can be synchronized. However, when the clocks a and b are cut off from both systems, each of the 0 system and the 1 system runs independently.

〔The invention's effect〕

As described above, according to the present invention, each system has an external synchronization circuit, and the output of each system is input to another system for external synchronization, so that the common circuit section of each system of the external synchronization circuit is eliminated. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional example. 1 ... External synchronization clock source, 2 ... 0 system external synchronization circuit,
3 ... 1-system external synchronization circuit, 4 ... External synchronization circuit, 5 ...
0 system loop, 6 …… 1 system loop, 21 …… 0 system selection circuit,
22 …… 0 system PLO circuit, 23 …… 0 system divider circuit, 31 …… 1 system selection circuit, 32 …… 1 system PLO circuit, 33 …… 1 system divider circuit, 4
1,44 …… Selection circuit, 42,43 …… PLO circuit.

Claims (1)

(57) [Claims] 1. A clock source connected to a local area network having a duplicated loop-like path, for generating a phase comparison clock signal, and a predetermined phase relationship with this phase comparison clock signal,
And an external synchronization circuit having an oscillator for generating a driving clock signal supplied to each of the duplicated loop-shaped paths. One of the external synchronizing circuits is provided corresponding to one of the external synchronizing circuits, and instead of the phase comparison clock signal from the clock source, the clock signal relating to the driving clock signal from the other of the external synchronizing circuits is supplied to the oscillator of its own circuit. An external synchronization system characterized by having a selection means that can be given.