JP2533638B2 - Circuit board manufacturing method - Google Patents

Circuit board manufacturing method

Info

Publication number
JP2533638B2
JP2533638B2 JP1063107A JP6310789A JP2533638B2 JP 2533638 B2 JP2533638 B2 JP 2533638B2 JP 1063107 A JP1063107 A JP 1063107A JP 6310789 A JP6310789 A JP 6310789A JP 2533638 B2 JP2533638 B2 JP 2533638B2
Authority
JP
Japan
Prior art keywords
plating
substrate
semiconductor element
power supply
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1063107A
Other languages
Japanese (ja)
Other versions
JPH02241043A (en
Inventor
宏 斉藤
茂成 高見
充弘 可児
二郎 橋爪
達彦 入江
芳正 檜村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1063107A priority Critical patent/JP2533638B2/en
Publication of JPH02241043A publication Critical patent/JPH02241043A/en
Application granted granted Critical
Publication of JP2533638B2 publication Critical patent/JP2533638B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体素子を実装する回路基板の製造方法
に関するものである。The present invention relates to a method for manufacturing a circuit board on which a semiconductor element is mounted.

［従来の技術］ 従来、半導体素子を搭載したパッケージの静電気対策
として、金属キャップ封止を行い、この金属キャップを
アースに接続させてシールド効果を持たせたり、基板内
にわざわざシールド回路を導体ペースト印刷法等により
形成し、端子をアースに接続する構造としている。[Prior Art] Conventionally, as a measure against static electricity in a package mounted with a semiconductor element, a metal cap is sealed and the metal cap is connected to the ground to have a shield effect, or a shield circuit is purposely provided in a conductor paste. It is formed by a printing method or the like, and has a structure in which the terminal is connected to the ground.

第４図は金属キャップ22を用いた従来例を示してい
る。基板21の上面にはペースト23にて半導体素子24が搭
載され、その周囲にはパターン回路25が形成してある。
半導体素子24とパターン回路25とはワイヤー26にて接続
してある。この半導体素子24及びパターン回路25を覆う
ように基板21上に金属キャップ22を接着等により固定し
ている。基板21下面からはパターン回路25と接続されて
いる端子27が多数垂設され、また、金属キャップ22と接
続したアース端子28を形成している。FIG. 4 shows a conventional example using the metal cap 22. A semiconductor element 24 is mounted on the upper surface of the substrate 21 with a paste 23, and a pattern circuit 25 is formed around the semiconductor element 24.
The semiconductor element 24 and the pattern circuit 25 are connected by a wire 26. A metal cap 22 is fixed on the substrate 21 by adhesion or the like so as to cover the semiconductor element 24 and the pattern circuit 25. A large number of terminals 27 connected to the pattern circuit 25 are vertically provided from the lower surface of the substrate 21, and a ground terminal 28 connected to the metal cap 22 is formed.

第５図は他の従来例を示し、半導体素子24等は基板21
上に実装され、また、基板21上に接着剤32にて封止キャ
ップ31を固定し、基板21内には信号ライン層33とパワー
ライン層34との間にシールド層35を形成している。尚、
パワーライン層34は１層目で、シールド層35は２層目
で、信号ライン層33は３層目にて構成してある。また、
基板21の下面から各層33,34から夫々対応した端子36,37
が垂設され、シールド層35からはアース端子38が垂設さ
れている。FIG. 5 shows another conventional example, in which the semiconductor element 24, etc. is the substrate 21.
The sealing cap 31 is mounted on the substrate 21 with the adhesive 32 fixed on the substrate 21, and the shield layer 35 is formed between the signal line layer 33 and the power line layer 34 in the substrate 21. . still,
The power line layer 34 is the first layer, the shield layer 35 is the second layer, and the signal line layer 33 is the third layer. Also,
From the bottom surface of the substrate 21, the corresponding terminals 36 and 37 from the layers 33 and 34, respectively.
And a ground terminal 38 is provided vertically from the shield layer 35.

［発明が解決しようとする課題］ 上記の従来例においては、工程が多く、最初からシー
ルド回路を設計しておかなければならず、実装面積も大
きいという問題があった。[Problems to be Solved by the Invention] In the above-described conventional example, there are problems that the number of steps is large, the shield circuit must be designed from the beginning, and the mounting area is large.

本発明は、上述の点に鑑みて提供したものであって、
シールド回路を容易に形成することを目的とした回路基
板の製造方法を提供するものである。The present invention is provided in view of the above points,
Provided is a method for manufacturing a circuit board, which aims to easily form a shield circuit.

［課題を解決するための手段及び作用］ 本発明は、メッキ給電部が格子状に形成され、その内
側に半導体素子が実装される実装部とメッキ給電部との
間にパターン回路が形成されたワークサイズ基板のメッ
キ給電部上を切断して個々の基板に形成し、この基板に
おける半導体素子と接続されるパターン回路とメッキ給
電部との間のメッキリードを切断し、メッキ給電部と接
続され半導体素子とは接続されないメッキリードを切断
せずに該メッキリードに接続される端子をアース端子と
し、残されたメッキ給電部をシールド回路として利用し
ているものである。[Means and Actions for Solving the Problems] In the present invention, the plating power feeding portion is formed in a grid shape, and a pattern circuit is formed between the mounting portion on which the semiconductor element is mounted and the plating power feeding portion. The work size board is cut on the plating power supply section to be formed on each board, and the plating lead between the pattern circuit connected to the semiconductor element on this board and the plating power supply section is cut to connect to the plating power supply section. The plating lead not connected to the semiconductor element is not cut, but the terminal connected to the plating lead is used as a ground terminal, and the remaining plating power supply portion is used as a shield circuit.

［実施例］ 以下、本発明の実施例を図面を参照して説明する。第
２図はワークサイズ基板１を示し、本実施例では９個の
基板２が形成される。メッキ給電部３は格子状に形成さ
れていて、その内側に基板２を形成している。基板２の
略中央部には半導体素子を実装する実装部４が形成され
ており、実装部４とメッキ給電部３との間にはメッキに
よりパターン回路５が形成されている。このワークサイ
ズ基板１は図中の破線に示す方向に切断されるものであ
り、４回の切断回数で第１図（ｂ）に示すような周囲に
メッキ給電部３を残した基板２が形成される。第１図
（ａ）は従来の基板２を示しており、従来ではメッキ給
電部３を残さずに切断していたため、メッキ給電部３を
切断するために12回の切断回数を要していた。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a work size substrate 1, and in this embodiment, nine substrates 2 are formed. The plating power supply part 3 is formed in a grid shape, and the substrate 2 is formed inside thereof. A mounting portion 4 for mounting a semiconductor element is formed in a substantially central portion of the substrate 2, and a pattern circuit 5 is formed between the mounting portion 4 and the plating power feeding portion 3 by plating. This work size substrate 1 is cut in the direction shown by the broken line in the figure, and a substrate 2 having a plating power supply part 3 left around is formed by four times of cutting as shown in FIG. 1 (b). To be done. FIG. 1 (a) shows a conventional substrate 2, which has conventionally been cut without leaving the plating power supply part 3, so that 12 times of cutting was required to disconnect the plating power supply part 3. .

すなわち、メッキ工程時には、ワークサイズ基板１の
メッキ給電部３より電流が印加され、個々の基板２内に
パターン回路の表面がメッキされてパターン回路５が形
成される。そして、上記のように、従来破棄していたメ
ッキ給電部３を周囲に残し、ワークサイズ基板１から個
々の基板２に切断する。さらに、第１図（ｃ）に示すよ
うに、半導体素子を実装する実装部４とメッキ給電部３
とを接続していたパターン回路５をカッティングして、
周囲のメッキ給電部３とパターン回路５とを電気的に絶
縁する。図中の６がカッティングした部分を示してい
る。尚、パターン回路５のカッティングは表面のメッキ
リードのみ切断するものであり、ダイシング・ソーで数
10μｍの深さでカッティングする。That is, at the time of the plating step, a current is applied from the plating power supply portion 3 of the work size substrate 1 to plate the surface of the pattern circuit in each substrate 2 to form the pattern circuit 5. Then, as described above, the work-size substrate 1 is cut into individual substrates 2 while leaving the plating power feeding portion 3 which has been conventionally discarded, around. Further, as shown in FIG. 1 (c), the mounting portion 4 for mounting the semiconductor element and the plating power feeding portion 3 are mounted.
Cutting the pattern circuit 5 that was connected to
The surrounding plating power supply part 3 and the pattern circuit 5 are electrically insulated. In the figure, 6 indicates the cut portion. In addition, the cutting of the pattern circuit 5 is to cut only the plating lead on the surface, and a dicing saw is used for cutting.
Cut to a depth of 10 μm.

このとき、基板２に接合された端子の中でソケットに
取り付けるため、端子に鍔が形成され、半導体素子と電
気的に接続していない端子があり、この端子はメッキ工
程時に給電するためだけに使用したメッキリード７によ
って接続されている。また、このこの端子はメッキリー
ド７を介して周囲のメッキ給電部３に接続されている。
つまり、この利用価値のないメッキリード７を新たにア
ース端子用のメッキリードとして利用するものである。
従って、メッキリードのカッティングはアース接地用の
パターンが基板２周囲に残されたメッキ給電部（シール
ド回路）３と接続した部分以外を行う。以上の工程によ
り基板２の周囲には、アース端子と接続されたシールド
回路（メッキ給電部３）が形成できる。At this time, among the terminals joined to the substrate 2, since the terminals are attached to the socket, a flange is formed on the terminals and there is a terminal that is not electrically connected to the semiconductor element. This terminal is used only for supplying power during the plating process. It is connected by the used plating lead 7. Further, this terminal is connected to the surrounding plating power supply portion 3 via the plating lead 7.
That is, the plating lead 7 having no utility value is newly used as a plating lead for the ground terminal.
Therefore, the cutting of the plating lead is performed except for the portion where the grounding pattern is connected to the plating power supply portion (shield circuit) 3 left around the substrate 2. Through the above steps, a shield circuit (plating power supply section 3) connected to the ground terminal can be formed around the substrate 2.

アース端子８は第３図に示すように、メッキ給電部３
であるシールド回路とスルーホール９を介して接続され
ている。尚、8aは鍔である。この第３図は、シールド回
路が形成されている基板２をキャップ10を封止樹脂11を
介して封止したパッケージを示している。12は半導体素
子である。また半導体素子12に接続されたパターン回路
５はスルーホール９を介して端子13と接続されている。
キャップ10の封止面からのノイズや静電気をシールド回
路（メッキ給電部３）を通してアース端子８から放電す
る。尚、メッキ給電部３と接続しているアース端子８
は、１本又は数本以上であり、パッケージ部品をプリン
ト基板と接合する際に、そのプリント基板のパターンに
より任意に選択して接続するようにしている。The ground terminal 8 is, as shown in FIG.
Is connected to the shield circuit via the through hole 9. Incidentally, 8a is a tsuba. FIG. 3 shows a package in which the substrate 2 on which the shield circuit is formed is sealed with the cap 10 through the sealing resin 11. 12 is a semiconductor element. The pattern circuit 5 connected to the semiconductor element 12 is connected to the terminal 13 through the through hole 9.
Noise and static electricity from the sealing surface of the cap 10 are discharged from the ground terminal 8 through the shield circuit (plating power supply part 3). The ground terminal 8 connected to the plating power supply unit 3
Is one or several or more, and when the package component is joined to the printed board, it is arbitrarily selected and connected according to the pattern of the printed board.

このように、パッケージ外部からのノイズ、静電気が
半導体素子12と接続したパターン回路５に伝達されず、
基板２に接続されたアース端子８から放電されるため、
電気的障害が阻止できると共に、静電耐圧が向上する。
従って、信頼性が向上する。また、従来廃棄されていた
メッキリードのメッキ給電部３を有効に利用でき、シー
ルド回路が容易に形成でき、このため、新たにシールド
回路をパターン及び基板２に設計したり、遮蔽板、金属
キャップ等を使用する必要がないものである。更に、ワ
ークサイズの基板から個々の基板２を切断により分離す
る際に、切断の位置を多少変更し、メッキリードのカッ
ティングを行うだけで良く、切断の工程は従来と同数以
下でよく、工程が簡略化できるものであり、従って、パ
ッケージにシールド効果を持たせることによるコストア
ップはほとんどない。In this way, noise and static electricity from the outside of the package are not transmitted to the pattern circuit 5 connected to the semiconductor element 12,
Since the ground terminal 8 connected to the board 2 is discharged,
The electrical failure can be prevented and the electrostatic breakdown voltage is improved.
Therefore, reliability is improved. In addition, the plating power supply part 3 of the plating lead, which has been conventionally discarded, can be effectively used, and the shield circuit can be easily formed. Therefore, the shield circuit can be newly designed on the pattern and the substrate 2, the shield plate, the metal cap. It is not necessary to use etc. Further, when the individual substrates 2 are separated from the work-sized substrate by cutting, the cutting position may be slightly changed and the plating leads may be cut, and the number of cutting steps may be equal to or less than the conventional one. It can be simplified, and therefore, the cost is hardly increased by providing the package with the shielding effect.

［発明の効果］ 本発明は上述のように、メッキ給電部が格子状に形成
され、その内側に半導体素子が実装される実装部とメッ
キ給電部との間にパターン回路が形成されたワークサイ
ズ基板のメッキ給電部上を切断して個々の基板に形成
し、この基板における半導体素子と接続されるパターン
回路とメッキ給電部との間のメッキリードを切断し、メ
ッキ給電部と接続され半導体素子とは接続されないメッ
キリードを切断せずに該メッキリードに接続される端子
をアース端子としていることにより、外部からのノイ
ズ、静電気が半導体素子と接続したパターン回路に伝達
されず、基板に接続されたアース端子から放電されるた
め、電気的障害が阻止できると共に、静電耐圧が向上
し、従って、信頼性が向上するものであり、また、従来
廃棄されていたメッキリードのメッキ給電部を有効に利
用でき、シールド回路が容易に形成でき、このため、新
たにシールド回路をパターン及び基板に設計したり、遮
蔽板、金属キャップ等を使用する必要がないものであ
る。更に、ワークサイズの基板から個々の基板を切断に
より分離する際に、切断の位置を多少変更し、メッキリ
ードのカッティングを行うだけで良く、切断の工程は従
来と同数以下でよく、工程が簡略化できるものであり、
従って、パッケージにシールド効果を持たせることによ
るコストアップはほとんどないという効果を奏するもの
である。[Advantages of the Invention] As described above, the present invention provides a work size in which a plating power feeding portion is formed in a grid shape and a pattern circuit is formed between the mounting portion on which the semiconductor element is mounted and the plating power feeding portion. A semiconductor element connected to the plating power supply section is cut by cutting the plating power supply section of the board to form an individual board, and cutting the plating lead between the pattern circuit connected to the semiconductor element on the substrate and the plating power supply section. Since the terminal connected to the plating lead without cutting the plating lead is connected to the ground terminal without disconnecting the plating lead, noise and static electricity from the outside are not transmitted to the pattern circuit connected to the semiconductor element and are connected to the substrate. Since it is discharged from the ground terminal, it can prevent electrical failure and improve electrostatic withstand voltage, thus improving reliability. It is possible to effectively use the plating power supply part of the plating lead, and to easily form the shield circuit, so it is not necessary to newly design the shield circuit on the pattern and the board, or to use a shield plate, a metal cap, or the like. Is. Furthermore, when separating individual substrates from a work-sized substrate by cutting, it is only necessary to slightly change the cutting position and cut the plating leads. Can be
Therefore, there is almost no increase in cost due to the package having the shield effect.

【図面の簡単な説明】[Brief description of drawings]

第１図は本発明の実施例の説明図であり、同図（ａ）は
従来の基板の平面図、同図（ｂ）（ｃ）は夫々本発明の
基板の平面図、第２図はワークサイズ基板の平面図、第
３図は本発明の実施例の断面図、第４図は従来例の断面
図、第５図は他の従来例の断面図である。 １はワークサイズ基板、２は基板、３はメッキ給電部、
４は実装部、５はパターン回路、７はメッキリード、８
はアース端子、12は半導体素子である。FIG. 1 is an explanatory view of an embodiment of the present invention. FIG. 1A is a plan view of a conventional substrate, FIGS. 1B and 1C are plan views of the substrate of the present invention, and FIG. 3 is a plan view of a work size substrate, FIG. 3 is a sectional view of an embodiment of the present invention, FIG. 4 is a sectional view of a conventional example, and FIG. 5 is a sectional view of another conventional example. 1 is a work size substrate, 2 is a substrate, 3 is a plating power supply unit,
4 is a mounting part, 5 is a pattern circuit, 7 is a plated lead, 8
Is a ground terminal, and 12 is a semiconductor element.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 橋爪 二郎 大阪府門真市大字門真1048番地 松下電 工株式会社内 (72)発明者 入江 達彦 大阪府門真市大字門真1048番地 松下電 工株式会社内 (72)発明者 檜村 芳正 大阪府門真市大字門真1048番地 松下電 工株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jiro Hashizume 1048 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works Co., Ltd. (72) Tatsuhiko Irie, 1048 Kadoma, Kadoma City, Osaka Matsushita Electric Works Co., Ltd. 72) Inventor Yoshimasa Hinomura Matsuda Electric Works Co., Ltd. 1048 Kadoma, Kadoma City, Osaka Prefecture

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】メッキ給電部が格子状に形成され、その内
側に半導体素子が実装される実装部とメッキ給電部との
間にパターン回路が形成されたワークサイズ基板のメッ
キ給電部上を切断して個々の基板に形成し、この基板に
おける半導体素子と接続されるパターン回路とメッキ給
電部との間のメッキリードを切断し、メッキ給電部と接
続され半導体素子とは接続されないメッキリードを切断
せずに該メッキリードに接続される端子をアース端子と
した回路基板の製造方法。1. A plating feed portion of a work-size substrate having a plating feed portion formed in a grid pattern and having a pattern circuit formed between the mounting portion on which a semiconductor element is mounted and the plating feed portion. Then, cut the plating lead between the pattern circuit connected to the semiconductor element and the plating power supply section on this board, and cut the plating lead connected to the plating power supply section and not connected to the semiconductor element. A method for manufacturing a circuit board, in which a terminal connected to the plating lead without using the grounding terminal is used.
JP1063107A 1989-03-15 1989-03-15 Circuit board manufacturing method Expired - Lifetime JP2533638B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1063107A JP2533638B2 (en) 1989-03-15 1989-03-15 Circuit board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1063107A JP2533638B2 (en) 1989-03-15 1989-03-15 Circuit board manufacturing method

Publications (2)

Publication Number Publication Date
JPH02241043A JPH02241043A (en) 1990-09-25
JP2533638B2 true JP2533638B2 (en) 1996-09-11

Family

ID=13219739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1063107A Expired - Lifetime JP2533638B2 (en) 1989-03-15 1989-03-15 Circuit board manufacturing method

Country Status (1)

Country Link
JP (1) JP2533638B2 (en)

Also Published As

Publication number Publication date
JPH02241043A (en) 1990-09-25

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