JP2531808Y2 - Ripple voltage reduction device - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ripple voltage reducing device used for a flow measuring device or the like.

[0002]

2. Description of the Related Art FIG. 7 shows an example of a conventional flow measuring device. In the figure, a turbine rotor 2 of a flow meter 1 rotates according to a flow rate of a fluid to be measured supplied through a supply line 3. A flow sensor 4 is provided on the outer periphery of the turbine rotor 2. The flow rate data A detected by the flow rate sensor 4 is input to the detection circuit 5 and converted into an electric signal. A pulsing circuit 6 is provided at the subsequent stage of the detection circuit 5, and the electric signal obtained by the detection circuit 5 is shaped into a waveform and output as a PWM signal (pulse signal) B. A scaler 7 is connected to the output side of the pulsing circuit 6. The output side of the scaler 7 has an F / I
A circuit (frequency / current conversion circuit) 8 is connected, and receives the pulse signal (PWM signal B).

The F / I circuit 8 includes a one-shot multivibrator circuit 9, an integration circuit 10, and a voltage / current conversion circuit.
The integration circuit 10 converts the PWM signal B sent through the one-shot multivibrator circuit 9 into a DC voltage, and the voltage / current conversion circuit 11 converts the data into a flow rate data A. The corresponding DC current I _OUT in a predetermined working current range is converted and output.

The period and amplitude of the PWM signal B are fixed, while a time width corresponding to the flow rate is set. In addition, in the integration circuit 10, the time constant of the PWM signal B is determined, but in order to make the response of the PWM signal B faster,
The value is kept short.

[0005]

In the above-described flow rate measuring device, the time constant of the integrating circuit 10 is shortened, so that the change in the PWM signal B, which is the input signal, is quickly followed, so that the ripple is reduced. There is a characteristic that the voltage increases.
In particular, in the reference current range E substantially in the middle of the working current range D, the above characteristics become remarkable. Constant frequency PWM
When this characteristic was verified using the signal B, a result was obtained that the ripple voltage might exceed the allowable value in the reference current region E as shown in FIG. In this case, the voltage was measured with a load resistance of 500Ω, but the DC current I _OUT
F. for 4 to 20 mA. In order to keep S (error with respect to Full Scale) at 1%, the allowable value is 500Ω × 16mA = 80mV. This allowable value is indicated by a dotted line F in FIG.

The present invention has been made in view of the above problems, and has as its object to provide a ripple voltage reduction device capable of reducing a ripple voltage with a time constant of an integration circuit being shortened.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an integrating circuit for converting a PWM signal indicating flow rate data into a DC current within a preset operating current range and outputting the DC signal. Before the current conversion circuit, the P
A comparison is made as to whether or not the WM signal falls within a reference current range set substantially in the middle of the working current range.
A cycle setting unit for changing and setting the cycle of the M signal is provided.

[0008]

With this configuration, when it is determined that the PWM signal falls within the reference current range, the cycle setting unit can change the cycle of the PWM signal and set the value to a shorter value, thereby preparing the integration circuit. The frequency that the gain decreases as the frequency increases and, consequently, the period decreases,
Since the gain decreases along with the gain characteristics, the ripple voltage can be reduced in the reference current region.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a ripple voltage reducing device according to an embodiment of the present invention; FIG. FIG.
The same members and portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In this case, the integration circuit 10
Is an operational amplifier (not shown) for a CR filter (not shown)
And has a frequency-gain characteristic in which the gain decreases as the frequency increases (as the period becomes shorter), and the time constant is set to a short value. To obtain excellent responsiveness.

In the figure, a pulsating circuit 6 and an integrating circuit 10
The arithmetic unit 20 is interposed between the two. Arithmetic unit 20
Is constituted by a microcomputer, a flow rate calculation circuit 21, a PWM signal cycle / width / amplitude setting circuit 22, and a PWM signal output circuit 23
2 to 4 are performed by operating the circuits based on a preset program.

The flow rate calculation circuit 21 includes a timer counter 24,
And a timer starting circuit 25. The timer counter 24 receives the signal from the pulsing circuit 6 and starts counting by inputting an activation signal from the timer activation circuit 25, and outputs the value to the PWM signal cycle / width / amplitude setting circuit 22.

[0012] The PWM signal cycle / width / amplitude setting circuit 22
A period setting register / comparator 26 for performing processing such as determining the period of the PWM signal B;
It roughly comprises a width setting register / comparator 27 for performing processing such as determining the width of the WM signal B, and an amplitude setting register / comparator 28 for performing processing such as determining the amplitude of the PWM signal B. The cycle setting register comparator 26, is set the period T _a in the initial state, the width setting register comparator 27, the width T _a1 in the initial state is designed to be set.

The width setting register / comparator 27 compares the data from the timer counter 24 with the width _Ta1, and outputs a signal to the PWM signal output circuit 23 when they match. Further, the width setting register / comparator 27 includes a first specified value G (for example, 8 mA) and a second specified value corresponding to the minimum value and the maximum value of the reference current range E set at the substantially middle portion of the working current range D, respectively. H (for example, 20 mA) is set, the input PWM signal B is compared with a first specified value G and a second specified value H, respectively, and the PWM signal B is set to a first specified value G and a second specified value. between the values H, i.e. when it is determined to have entered a reference current region E, as well as changing the width of the PWM signal B to a width T _b1 set shorter width T _b1 than the width T _a1, cycle setting register comparator 26 to the period T _a shorter period T
Set the _b to change the cycle of the PWM signal B the period T _b.

That is, when the DC current I _OUT is expected to enter the reference current region E as it is, the period of the PWM signal B is shortened in the reference current region E, whereby the integration circuit 10 ( Low-pass filter)
By having the frequency-gain characteristic in which the gain decreases as the frequency increases (as the cycle becomes shorter), the ripple voltage R decreases, and it is possible to prevent the ripple voltage R from exceeding an allowable value in the portion. In this embodiment, the width setting register / comparator configured as described above is used.
27 forms a cycle setting unit.

The arithmetic unit 20 executes the width match interrupt process and the cycle match interrupt process in a subroutine process as described later. However, if the width match interrupt process has been executed one or more times, the PWM The signal B is changed from H level to L level, the amplitude is determined, and the PWM signal B is output.

The width setting register / comparator 27
Is, the PWM signal B is less than the first predetermined value G, or is the second predetermined value H above, namely when it is determined that it has not entered the reference current range E, the cycle of the PWM signal B is set to the period T _b and that you are in the condition maintaining the initial setting state, that maintains a set of width T _a1, and to cycle setting register comparator 26 to maintain the setting of the period T _a.

The cycle setting register comparator 26 compares the data with the period T _a from the timer counter 24, while outputting a signal to the PWM signal output circuit 23 to a consistent point in time, again clears the timer counter 24 Start counting from zero. In the figure, reference numeral 29 denotes an ammeter for measuring the DC current I _OUT .

Next, the details of the arithmetic processing of the arithmetic unit 20 will be described with reference to the flowcharts of FIGS.

[0019] In step S1, when it is power-on reset, the following steps S2, sets the period T _a of the PWM signal B the period setting register comparator 26. Then in step S3, setting the period T _a1 of the PWM signal B to width setting register comparator 27 starts the timer counter 24 in step S4.

The HALT mode is entered in step S5. This mode is released by performing the width match interrupt process or the cycle match interrupt process.

When the count value of the timer counter 24 matches the set value of the cycle setting register / comparator 26, a cycle match interrupt process is performed (step S6), and the PWM signal B
Is changed from the L level to the H level, the amplitude is determined, and the PWM signal B is output (step S7). Next, it is determined whether or not the data input to the width setting register / comparator 27 is greater than or equal to the first specified value G (step S8). If YES is determined, the process proceeds to step S9.
Proceed to step 2 to execute the process.

In step S9, it is determined whether or not the data input to the width setting register / comparator 27 is equal to or less than the second specified value H. If the determination is YES, the process proceeds to step S10. If the determination is NO, the process proceeds to step S12. Proceed to perform the processing.

[0023] In step S10, the period T _a shorter period T _b is set to the period setting register comparator 26 P
The period of the WM signal B by changing settings in the period T _b, performs the process of step S11. In step S11, the width _Tb1 shorter than the width _Ta1 is set in the width setting register / comparator 27, the width of the PWM signal B is set to this width _Tb1 , and the process enters the HALT mode in step S15.

[0024] If it is determined NO in step S8 or step S9, the period of the PWM signal B is determined whether the period T _b (step S12), the cycle period setting register comparator 26 determines that the YES T _a set to the period T _a of the PWM signal B (step S13). Next, the width _Ta1 is set in the width setting register / comparator 27, and the PWM is set.
The width of the signal B is set to this width _Ta1 (step S14),
The process proceeds to the HALT mode in step S15. In this case, when the value of the timer counter 24 matches the value of the period register / comparator, the timer counter 24 is cleared and restarts counting from zero. If NO is determined in the step S12, the step S14 is executed.

When the value of the timer counter 24 and the value of the width setting register counter match, a width match interrupt process is executed (step S16), and in the next step S17, the number of times of the period match interrupt process is performed once or more. Judge whether or not
If YES is determined, step S18 is executed. Steps
In S18, the PWM signal B is changed from H level to L level,
The amplitude is determined and the PWM signal B is output.
Execute the ALT mode. If NO is determined in the step S17, the step S19 is executed.

In the ripple voltage reduction device configured as described above, when the timer counter signal S as shown in FIG. 5 is input to the timer counter 24, the PWM signal B is determined based on the above-described determination processing in steps S8 and S9. It is determined whether or not the current range E is entered, and both steps S8 and S9
And YES, that is, DC current I _{OUT and} PWM
If it is determined that the signal B is in the reference current range E,
S10 and performs the process of step S11, the period of the PWM signal B is shorter in the period T _b, and will be shortened by the width of the width T _b1.

For this reason, the gain decreases in accordance with the frequency-gain characteristic that the gain decreases as the frequency of the integrating circuit 10 increases, and the ripple voltage R can be reduced in the reference current range E. The ripple voltage R can be reduced with the time constant of 10 set short.

In the flow measuring device shown in FIG.
_{If OUT} is at the reference current range E, although the ripple voltage R 8 there may exceed the allowable value, the apparatus according to the present invention, the DC current I _OUT i.e. PWM signal B is the reference current range If it is determined that it is at E, the processing shown in steps S10 and S11 is performed to set the cycle and width of the PWM signal B to be short. The gain decreases due to the frequency-gain characteristic that the gain decreases, and the ripple voltage R falls within the allowable value in the reference current region E as shown in FIG. For this reason,
The ripple voltage R can be reduced with the time constant of the integration circuit 10 set short.

In this embodiment, the case where the present invention is applied to a turbine type flow meter is described as an example. However, the present invention is not limited to this, and any other type using a PWM signal B can be used. It can be applied to the flowmeters.

[0030]

The present invention is a ripple voltage reduction device configured as described above. Therefore, when it is determined that the PWM signal enters the reference current region E, the period setting unit can change the period of the PWM signal. By setting the value to be short, the gain decreases along the frequency-gain characteristic that the gain decreases as the frequency of the integrator circuit increases, and the ripple voltage can be reduced in the reference current range E. Thus, the ripple voltage can be reduced in a state where the time constant of the integrating circuit is set short.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically illustrating a ripple voltage reducing device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the content of a calculation process of a calculation device of the ripple voltage reduction device.

FIG. 3 is a flowchart showing the content of a cycle coincidence interrupt process among the content of the arithmetic processing of the arithmetic device.

FIG. 4 is a flowchart showing the content of a width match interrupt process among the content of the arithmetic processing of the arithmetic device.

FIG. 5 is a signal waveform diagram in each section of the ripple voltage reduction device.

FIG. 6 is a waveform chart showing a ripple voltage obtained by the ripple voltage reduction device.

FIG. 7 is a block diagram schematically illustrating an example of a conventional flow measurement device.

FIG. 8 is a waveform chart showing a ripple voltage obtained by the flow measurement device.

[Explanation of symbols]

 B PWM signal 10 Integrator 11 Voltage / current converter 20 Arithmetic unit 27 Width setting register / comparator

Claims (1)

(57) [Scope of request for utility model registration] 1. A PWM signal indicating flow rate data, which is converted into a DC current within a preset use current range and output, is provided before the integration circuit and the voltage / current conversion circuit.
A comparison is made as to whether or not the WM signal falls within a reference current range set substantially in the middle of the working current range.
A ripple voltage reduction device comprising a cycle setting unit for changing and setting the cycle of the M signal.